ACE Compiler TM

Auspy Custom Emulator Compiler

Overview
Mapping todays complex ASICs or SoCs
into multiple-FPGA prototypes faces the
challenge of finding a partition
solution that
(1) meets the constraints of the target
prototyping platform such as FPGA
capacity, the clock distribution and
limited connectivity in-between FPGAs.
(2) is timing-correct.

RTL may be exported as the other option

to further optimize timing on individual
FPGAs with the FPGA synthesis.
The whole process could be completely
automatic, or could be done manually on
portion of the design for reasons such
as anticipation of future design
changes, target system interface or
preferred grouping and followed with the
automation to finish the compilation.

Compilation flow

DomainDomain-driven automatic partition

ACE Compiler, with its hierarchical

domain-driven technology, produces
solutions which not only efficiently map
big designs into the target prototyping
platform, but also run at the top
performance.

ACE Compiler distributes clocks across

the prototyping platform with the
mimimum skew. Schemes of loop-back,
generator duplication or isolation are
applied on internally generated clocks
to balance the skew reaching every FPGA.

RTL/gate

Encapsulate synthesis

Board file

ACE Compiler could also limit the number

of clock domains partitioned into each
FPGA to ensure sufficient clock buffers
to drive every clock in FPGAs.
Gated, latch-generated or divided clocks
will be automatically converted. The
conversion could be cascaded or crossing
the hierarchies.

Partition

Board routing

RTLs

Encapsulated FPGA P&R

Timing model

Prototyping

ACE Compiler flow

The design is imported modularly through
the encapsulated synthesis with the
embedded commercial FPGA synthesis tool.
The successive partition step breaks the
design into multiple FPGAs with the
optimized timing while honoring the
platform constraints. The board routing
then assigns inter-FPGA signals to
traces and consequently fixes the FPGA
pin locations. The encapsulated FPGA P&R
generates the programming bit-streams.

Combinatorial hops crossing FPGAs will

be minimized by the auto-partition to
achieve the high system performance.
To achieve the overall target prototype
performance, the timing budget effort
will calcuate and prepare timing
constraints on every FPGA to be
synthesized, placed and routed.
WireWire-sharing
ACE Compiler is able to insert wiresharing logic to relieve FPGA pin
limits. The correct timing could be
achieved with the domain-based wiresharing and the exclusion of the
combinatorial hopping signals. Variety
of custom wire-sharing schemes are
supported.

Auspy Development Inc. 10430 S. De Anza Blvd., Suite 275, Cupertino, CA 95014 Phone: 408-252-5813 Email: npc@auspy.com URL: http://www.auspy.com

Datasheet
Hierarchical approach
ACE Compiler adopts hierarchical
approach on all its operations to manage
the design complexities. The memory
required to run ACE Compiler on any big
designs is usually less than the memory
required by FPGA P&R of a single FPGA.
ACE Compiler has automatically
partitioned a 40 million gate design in
hours on a 32-bit Linux workstation.
Automatic Board routing
ACE Compiler will automatically routes
through FPGAs to complete the
connections for those signals without
the direct paths to the target FPGAs.
ACE Compiler is capable of assigning
board connections through cables, fieldprogrammable interconnect devices or bus
switches.
If the design has more tri-state buses
than the hardware platform supports, ACE
Compiler implements each tri-state bus
in a focal FPGA after routing all the
tri-state and enable signals from
driving partitions to this FPGA.
Clocks will be assigned to low-skew
traces automatically. LVDS board traces
are automatically identified and
assigned to those LVDS-pair signals.
Probe
ACE Compiler brings out any internal
signals to FPGA pins for probing. Three
types of probes are supported :
1) Permanent probes selected before
partition and its pin requirement will
be taken into account by partition.
2) Incremental probes selected after
partition and will be brought to unused
FPGA pins.
3) Fast probes - selected after FPGA P&R
and will be brought to unused FPGA pins
with fast incremental FPGA P&R.

Copyright 2006 Auspy Development Inc. All rights reserved.

Features
Automatic partition and board routing.
RTL, gate-level or mixed language.
Encapsulated synthesis with commercial
FPGA synthesis tools.
Parallel synthesis and FPGA P&R.
Hierarchical approach to handle very
large designs.
Domain-driven partition produces lowskew clock distribution, converts gated
clocks, minimizes the combinatorial hops
crossing FPGAs and selects signals for
the high-performance wire-sharing.
Multiple reports on the timing
characteristics of the partition.
Timing budget to generate FPGA timng
constraints to achieve the target
prototyping performance.
Logic replication for pin-efficient
partition.
Impact analysis assisting manual
partition.
Global logic trimming.
Automatic routing through FPGAs,
cables and programmable bus switches.
Probing any internal signal.
Fast incremental design changes.
Simulatable at every step.
GUI or script execution.
Work for custom or commercial
boards/emulators.
Integration
The encapsulated synthesis is integrated
with commercial synthesis tools from
Altera, Mentor Graphics, Synopsys and
Xilinx.
The encapsulated FPGA P&R is integrated
with Altera and Xilinx P&R tools.
ACE Compiler supports FPGA's from the
Altera StratixII/StratixIII families and
Xilinx Virtex4/Virtex5 families.
Platform
Linux
Windows
Solaris