Overview

Decoding

Part 2 Combinational Logic

Decoding - the conversion of an n-bit input

code to an m-bit output code with
n m 2n such that each valid code word
produces a unique output code

Circuits that perform decoding are called
decoders

Here, functional blocks for decoding are

Functions and functional blocks

Rudimentary logic functions
Decoding using Decoders

Implementing Combinational Functions
with Decoders

Encoding using Encoders

Selecting using Multiplexers

called n-to-m line decoders, where m 2n, and

generate 2n (or fewer) minterms for the n input
variables

Implementing Combinational Functions

with Multiplexers
Chapter 3 10

Decoder Examples

Chapter 3 11

Decoder Examples

2-to-4-Line Decoder
Note that the 2-4-line made up of 2 1-to-2-line decoders and 4 AND gates.

1-to-2-Line Decoder
A

D0 D1

A0

D0 5 A
0
1

1
0

0
1

D1 5 A

(a)

(b)

A1 A0

D0 D1 D2 D3
A1

0
0
1
1

0
1
0
1

1
0
0
0

0
1
0
0

0
0
1
0

0
0
0
1

D0

=A 1 A 0

D1

=A 1 A 0

D2

=A 1 A 0

D3

=A 1 A 0

(a)

(b)

Chapter 3 12

Decoder Expansion

Chapter 3 13

Decoder Expansion - Example 1

General procedure given in book for any decoder with n

inputs and 2n outputs.

This procedure builds a decoder backward from the outputs.

The output AND gates are driven by two decoders with their
numbers of inputs either equal or differing by 1.

These decoders are then designed using the same procedure
until 1-to-2-line decoders are reached.

3-to-8-line decoder
Number of output ANDs = 8
Number of inputs to decoders driving output ANDs = 3
Closest possible split to equal

2-to-4-line decoder

1-to-2-line decoder

2-to-4-line decoder

Number of output ANDs = 4

Number of inputs to decoders driving output ANDs = 2

Closest possible split to equal
Two 1-to-2-line decoders

The procedure can be modified to apply to decoders with the

number of outputs 2n
Chapter 3 14

See next slide for result

Chapter 3 15

Decoder Expansion - Example 1

Result

4 2-input ANDs

Decoder Expansion - Example 2

8 2-input ANDs
D0

A0

D1
A1

D2
D3

2-to-4-Line
decoder

D4
D5

A2

D6

1-to-2-Line decoders

D7

3-to-8 Line decoder

Chapter 3 16

Chapter 3 17

Decoder Expansion - Example 2

7-to-128-line decoder
Number of output ANDs = 128
Number of inputs to decoders driving output ANDs = 7
Closest possible split to equal

Decoders

4-to-16-line decoder

3-to-8-line decoder

4-to-16-line decoder

Application

Number of output ANDs = 16

Number of inputs to decoders driving output ANDs = 4

Closest possible split to equal
2 2-to-4-line decoders

Complete using known 3-8 and 2-to-4 line decoders

Chapter 3 18

BCD TO 7-SEGMENT DECODER

Decimal output
LED

BCD input

01
00
1 01

Chapter 3 19

Decoder with Enable

In general, attach m-enabling circuits to the outputs

See truth table below for function
Note use of Xs to denote both 0 and 1
Combination containing two Xs represent four binary combinations

BCD-to7-Segment
Decoder

Alternatively, can be viewed as distributing value of signal EN to

EN
1 of 4 outputs
A

In this case, called a
A
demultiplexer
D
1

Electronic decoders are available in IC form.

This decoder translates from BCD to decimal.
Decimals are shown on a 7-segment LED display.
This IC also drives the 7-segment LED display.

EN A 1 A 0
0
1
1
1
1

X
0
0
1
1

X
0
1
0
1

D 0 D 1 D2 D 3
0
1
0
0
0
(a)

0
0
1
0
0

0
0
0
1
0

D1

0
0
0
0
1

D2
D3
(b)

Chapter 3 21

So what good is a decoder?

Do the truth table and equations look familiar?
A

0
0
1
1

0
1
0
1

Q0 Q1 Q2 Q3
1
0
0
0

0
1
0
0

0
0
1
0

Q0
Q1
Q2
Q3

0
0
0
1

= A B
= A B
= A B
=AB

Decoders are sometimes called minterm generators

For each of the input combinations, exactly one output is true
Each output equation contains all of the input variables
These properties hold for all sizes of decoders

Arbitrary functions can be implemented with decoders. If a

sum of minterms equation for a function is given, a decoder
(a minterm generator) is used to implement that function

Combinational Logic Implementation Decoder and OR Gates

Implement m functions of n variables with:
Sum-of-minterms expressions
One n-to-2n-line decoder
m OR gates, one for each output

Approach 1:
Find the truth table for the functions
Make a connection to the corresponding OR from the
corresponding decoder output wherever a 1 appears in
the truth table

Approach 2
Find the minterms for each output function
OR the minterms together
Chapter 3 23

Design example: Addition

Lets make a circuit that adds three 1-bit inputs X, Y and Z

We will need two bits to represent the total; lets call them C and S, for
carry and sum. Note that C and S are two separate functions of the
same inputs X, Y and Z

Decoder-based Adder

3-to-8 decoders implement
C(X, Y, Z) = m(3, 5, 6, 7)

and

S(X, Y, Z) = m(1, 2, 4, 7)

Here are a truth table and sum-of-minterms equations for C and S

0 + 1 + 1 = 10

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
0
0
1
0
1
1
1

0
1
1
0
1
0
0
1

C(X,Y,Z) = m(3,5,6,7)
S(X,Y,Z) = m(1,2,4,7)
1 + 1 + 1 = 11

Active States and Bubbles

Primarily applies to control signals; used to denote when
a condition is active or enabled

Active State - signal state (0 or 1) that indicates the
assertion of some condition or action

A signal is asserted when it is in the active state

A signal is negated when it is in the inactive state
Active-1 (active high) is when active state is logic 1
Active-0 (active low) is when active state is logic 0

Signal Naming Conventions

The problem is how to distinguish between
active-1 and active-0 signals.
Use suffix of _0; (i.e A_0) after signal name
Use suffix of _LO or _L
Use suffix of _BAR

No matter what you use, BE CONSISTENT!

Symbol pins without bubbles denote active-1 signals

Symbol pins with bubbles denote active-0 signals

Signal Naming

Active Levels For Pins

Be Careful!

A variation of the standard decoder

The decoders weve seen so far are active-high decoders.
EN

S1

S0

Q0

Q1

Q2

Q3

1
1
1
1

0
0
1
1

0
1
0
1

1
0
0
0

0
1
0
0

0
0
1
0

0
0
0
1

An active-low decoder is the same thing, but with an inverted EN input

and inverted outputs
G

The output equations for an active-low decoder are mysteriously similar,

yet somehow different
=
=
=
=

(S1 S0)
(S1 S0)
(S1 S0)
(S1 S0)

=
=
=
=

Y1

Y2

Y3

2-to-4 Active-Low Decoder

Active-Low Decoders
Q3
Q2
Q1
Q0

Y0

S1 + S0
S1 + S0
S1 + S0
S1 + S0

Y0

Y1

Y2

Y3

0
0

Y0
Y1
Y2
Y3

= (S1 + S0) + G
= (S1 + S0) + G
= (S1 + S0) + G
= (S1 + S0) + G

It turns out that active-low decoders generate maxterms

So we can use active-low decoders to implement arbitrary functions too,
but as a product of maxterms, i.e., f(x,y,z) = M(4,5,7)

Complete 74x139 Decoder

Summary of Decoders
n

A n-to-2 line decoder generates the minterms of an n-variable function

As such, decoders can be used to implement arbitrary functions
Later on well see other uses for decoders too

Some variations of the basic decoder include:
Adding an enable input
Using active-low inputs and outputs to generate maxterms

We also talked about:
Applying our circuit analysis and design techniques to understand and
work with decoders
Using block symbols to encapsulate common circuits like decoders
Building larger decoders from smaller ones

Overview

Encoding

Part 2 Combinational Logic

Encoding - the opposite of decoding - the conversion of an m-bit

input code to a n-bit output code with n m 2n such that each
valid code word produces a unique output code

Functions and functional blocks

Rudimentary logic functions
Decoding using Decoders

Circuits that perform encoding are called encoders

Implementing Combinational Functions

with Decoders

Encoding using Encoders

Selecting using Multiplexers

Implementing Combinational Functions
with Multiplexers

An encoder has 2n (or fewer) input lines and n output lines which
generate the binary code corresponding to the input values

Typically, an encoder converts a code containing exactly one bit
that is 1 to a binary code corresponding to the position in which
the 1 appears.

Chapter 3 36

Binary Encoders

An encoder is a digital function that performs the inverse operation
of a decoder

Only one input can have the

value of 1 at any given time

Chapter 3 37

Octal-to-Binary Encoder

This encoder has eight inputs, one for each of the octal digits.

Three outputs that generate the corresponding binary number.

D7
D6
A2
D5
D4 8 to 3 A1
D3 Encoder
A0
D2
D1
D0

Octal-to-Binary Encoder

Encoding - Example

Octal-to-Binary Encoder
It is assumed that only one input has a value of 1 at any given
time, so that the table has only eight rows with specified output
values.
For the remaining rows, all of the outputs are dont cares.

A0 = D1 + D3 + D5 + D7,
A2 = D4 + D5 + D6 + D7
A1 = D2 + D3 + D6 + D7

Chapter 3 41

Encoder - Example

Encoder Example (continued)

A decimal-to-BCD encoder
Inputs: 10 bits corresponding to decimal digits 0
through 9  (D0, , D9)
Outputs: 4 bits with BCD codes
Function: If input bit Di is a 1, then the output
(A3, A2, A1, A0) is the BCD code for i,

The truth table could be formed, but

alternatively, the equations for each of the
four outputs can be obtained directly.

Input Di is a term in equation Aj if bit Aj is 1 in

the binary value for i.

Equations:
A3 = D8 + D9
A2 = D4 + D5 + D6 + D7
A1 = D2 + D3 + D6 + D7
A0 = D1 + D3 + D5 + D7 + D9

F1 = D6 + D7 can be extracted from A2 and A1.

Is there any cost saving???

Chapter 3 42

ELECTRONIC ENCODER - DECIMAL TO

BCD

Chapter 3 43

Encoders & Decoders

BCD Output
Decimal input

01
0
00
11

A0

O0

A0

O0

A1

O1

A1

O1

A2

O2

A2

A3

7
5
3

Decimal
to
BCD
Encoder

ENCODER

O2
DECODER

O3

A4

O4

A5

O5

A6

O6

A7

O7

Encoders are available in IC form.

This encoder translates from decimal input to BCD output.

ONLY ONE INPUT

ACTIVATED AT A
TIME

ONLY ONE OUTPUT

ACTIVATED AT A
TIME

BINARY CODE OUTPUT

BINARY CODE INPUT

Encoder - Problem

But!

If more than one input value is 1, then the

encoder just designed does not work.

Theres one masla with the

Encoders 

What can be the possible solution for this

problem???

Chapter 3 46

Chapter 3 47

Priority Encoders

This ambiguity is resolved if priority is established so that only one
input is encoded, no matter how many inputs are active at a given point
of time.

The priority encoder includes a priority function.

The operation of the priority encoder is such that if two or more inputs
are active at the same time, the input having the highest priority will
take precedence.

Priority Encoders

An encoder that can accept all possible combinations of input values

and produce a meaningful result is a Priority Encoder.

Among the 1s that appear:
Chapter 3 48

It selects the most significant input position containing a 1 and responds

with the corresponding binary code for that position.

Chapter 3 49

4-Input Priority Encoder

Priority Encoder

A priority encoder is a combinational circuit that implements a priority
function

More than one input

lines are asserted

Code of highest priority

line asserted
50

51

4-Input Priority Encoder

4-Input Priority Encoder

53

Priority Encoder 5 Inputs

Priority Encoder 5 Inputs

Priority encoder with 5 inputs (D4, D3, D2, D1, D0) - highest priority to most
significant 1 present - Code outputs A2, A1, A0 and V, where V indicates at
least one 1 present.
Outputs
No. of MinInputs
terms/Row D4 D3 D2 D1 D0 A2 A1 A0
V
1

Could use a K-map to get equations, but can

be read directly from table and manually
optimized if careful:
A2 = D4
A1 = D4 D3 + D4 D3D2 = D4F1, F1 = (D3 + D2)
A0 = D4 D3 + D4 D3 D2 D1 = D4(D3 + D2D1)
V = D4 + F1 + D1 + D0

16
1
X
X
X
X
1
0
0
1

Xs in input part of table represent 0 or 1; thus table entries correspond to
product terms that are not minterms. The column on the left shows that all 32
minterms are present in the product terms in the table
Chapter 3 54

74x148 8-Input Priority Encoder

Chapter 3 55

Cascaded Priority Encoders

Chapter 3 57

Overview

Selecting Using Multiplexers

Part 2 Combinational Logic

Multiplexers (MUX)

Functions and functional blocks

Rudimentary logic functions
Decoding using Decoders

Device that allows digital information from

several sources to be routed onto a single line
for transmission over a single output line

Implementing Combinational Functions

with Decoders

Encoding using Encoders

Selecting using Multiplexers

Implementing Combinational Functions
with Multiplexers

Uses data select lines which permits digital data

on any one of the inputs to be switched to the
output line
Multiplexers are also known as data selectors

Chapter 3 58

Multiplexers (MUX)

Multiplexers (MUX)

A multiplexer selects information from an

input line and directs the information to an
output line

A typical multiplexer has n control inputs
(Sn 1, S0) called selection inputs, 2n
information inputs (I2n 1, I0), and one
output Y

A multiplexer can be designed to have m
information inputs with m < 2n as well as n
selection inputs

A n-to-1 multiplexer sends one of n input lines to a single output line

A multiplexer has two sets of inputs:

n data input lines

s=log2n select lines, to pick one of the n data inputs

Chapter 3 60

Multiplexers (MUX)

A Practical MUX Circuit

Multiplexers, (or MUXs) are used to choose between resources

A Real-Life Example:
In the old days before networking, several computers could share one
printer through the use of a switch.

Chapter 3 63

Mechanical Equivalent of MUX

Multiplexers - Representation
0

MUX

Y
0
1
2
3

Chapter 3 64

Multiplexers - Representation

Chapter 3 65

2-to-1-Line Multiplexer

Since 2 = 21, n = 1

The single selection variable S has two values:
S = 0 selects input I0
S = 1 selects input I1

The equation:
Y = S I0 + SI1

The circuit:

Enabling
Circuits

Decoder
I0

Y
S
I1
Chapter 3 66

2-to-1-Line Multiplexer (continued)

Note the regions of the multiplexer circuit shown:

Chapter 3 67

4 to 1 Multiplexer

Function Table

1-to-2-line Decoder
2 Enabling circuits
2-input OR gate

To obtain a basis for multiplexer expansion, we combine

the Enabling circuits and OR gate into a 2 2 AND-OR
circuit:
1-to-2-line decoder
2 2 AND-OR

In general, for an 2n-to-1-line multiplexer:

n-to-2n-line decoder
2n 2 AND-OR

Select Inputs
S1
S0
0
0
0
1
1
0
1
1

Output
Z
I0
I1
I2
I3

Z = S1 S 0 I 0 + S1S 0 I1 + S1 S 0 I 2 + S1S 0 I 3
Chapter 3 68

Chapter 3 69

10

4 to 1 Multiplexer (Internal)

Example: 4-to-1-line Multiplexer

2-to-22-line decoder

22 2 AND-OR
Decoder

S1

4 3 2 AND-OR

S0
S1
S0

Decoder

I0

I1

Y
I2

I3

70

Chapter 3 71

74x151 8-to-1 Multiplexer

Multiplexer Width Expansion

Select vectors of bits instead of bits

Use multiple copies of 2n 2 AND-OR in parallel

Example:
4-to-1-line
quad multiplexer
4 3 2 AND-OR

I 0,0

Y0

.
.
.

4 3 2 AND-OR

I 3,0

A0

2-to-4-Line decoder

A1

D0

I 0,1

.
.
.
D3

.
.
.

Y1

4 3 2 AND-OR

I 3,1
I 0,2

Y2

.
.
.
4 3 2 AND-OR

I 3,2
I 0,3
.
.
.

Y3

I 3,3

73
Chapter 3 72

74x151 8-to-1 Multiplexer

Expanding Multiplexers

11

Implementing functions with multiplexers

Muxes can be used to implement arbitrary functions

One way to implement a function of n variables is to use an 2^n-to-1 mux:
For each minterm mi of the function, connect 1 to mux data input Di.
Each data input corresponds to one row of the truth table
Connect the functions input variables to the mux select inputs. These
are used to indicate a particular input combination

For example, lets look at f(x,y,z) = m(1,2,6,7).

x

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
1
1
0
0
0
1
1

There are three inputs, so well need a 4-to-1 mux

The basic setup is to connect two of the input variables (usually the
first two in the truth table) to the mux select inputs
Y

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
0
0
1
0
1
1
1

Z S

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
1
1
0
1
0
0
1

x and y are the same, so f is a function of z only.

When xy=00, f=z

When xy=01, f=z
When xy=10, f=0
When xy=11, f=1

0
0

0
1

0
1

0
0

1
1

0
1

1
0

1
1

0
0

0
1

0
0

1
1

1
1

0
1

1
1

Multiplexer-based carry

We can set the multiplexer data inputs D0-D3, by fixing X and Y
and finding equations for C in terms of just Z.
X

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
0
0
1
0
1
1
1

When XY=00, C=0

When XY=01, C=Z
When XY=10, C=Z
When XY=11, C=1

C = X Y D0 + X Y D1 + X Y D2 + X Y D3
= X Y 0 + X Y Z + X Y Z + X Y 1
= X Y Z + X Y Z + XY
= m(3,5,6,7)

Q=XYD0 + XYD1 + XYD2 + XYD3

Heres the same thing, but for the sum function S(X,Y,Z)

0
0
0
0
1
1
1
1

group the rows into pairs. Within each pair of rows,

With S1=X and S0=Y, then

Multiplexer-based Sum
X

Step 1: Find the truth table for the function, and

x
0
0

Step 3: Connect the equations above for f(z) to the

data inputs D0-D3.

Lets implement the adder carry function, C(X,Y,Z), with muxes

0
0
0
0
1
1
1
1

We can actually implement f(x,y,z) = m(1,2,6,7) with

just a 4-to-1 mux, instead of an 8-to-1

Step 2: Connect the first two input variables of the

truth table (here, x and y) to the select bits S1 S0
of the 4-to-1 mux.

Example: Multiplexer-Based Adder

A more efficient way

When XY=00, S=Z

When XY=01, S=Z
When XY=10, S=Z
When XY=11, S=Z

Summary of Muxes

A n-to-1 multiplexer routes one of n input lines to a single output
line

Just like decoders,
Muxes are common enough to be supplied as stand-alone devices for
use in modular designs.
Muxes can implement arbitrary functions

We saw some variations of the standard multiplexer:

Smaller muxes can be combined to produce larger ones
We can add active-low or active-high enable inputs

S = X Y D0 + X Y D1+ X Y D2 + X Y D3
= X Y Z + X Y Z + X Y Z + X Y Z
= m(1,2,4,7)

As always, we use truth tables and Boolean algebra to analyze

things

12

Three-state Buffers

Selecting based on 3-state buffers

Output = LOW, HIGH, or Hi-Z

Wire can be considered disconnected

Can tie multiple outputs together if at most one at a time is
enabled

Different flavors:

Sharing a Wire

Three-State Drivers 74x541

Driver Application

Three-State Transcievers

13

Transciever Application

14