Project Proposal

Overview :
The MIPS (Microprocessor without Interlocked Pipeline Stages) architecture evolved from research on
efficient processor organization and VLSI integration at Stanford University. Their prototype chip
proved that a microprocessor with five-stage execution pipeline and cache controller could be
integrated onto a single silicon chip, greatly improving performance over non-pipelined designs. At the
same time, a research group at Berkeley designed the RISC-I chip based on pretty much the same
ideas. Today, the acronym RISC is interpreted as "regular instruction set computer", and the RISC ideas
are used in every current microprocessor design.
The key concepts of the original MIPS architecture are:
five-stage execution pipeline: fetch, decode, execute, memory-access, write-result
regular instruction set, all instructions are 32-bit
three-operand arithmetical and logical instructions
32 general-purpose registers of 32-bits each
no status register or instruction side-effects
no complex instructions (like stack management, string operations, etc.)
optional co-processors for system management and floating-point
only the load and store instruction access memory
flat address space of 4 GBytes of main memory (2^32 bytes)
memory-management unit (MMU) maps virtual to actual physical addresses
optimizing C compiler replaces hand-written assembly code
hardware structure does not check dependencies - not "foolproof"
but software tool chain knows about hardware and generates correct code
One of the key features of the MIPS architecture is the regular register set. It consists of the 32-bit
wide program counter (PC), and a bank of 32 general-purpose registers called r0..r31, each of which is
32-bit wide. All general-purpose registers can be used as the target registers and data sources for all
logical, arithmetical, memory access, and control-flow instructions. Only r0 is special because it is
internally hardwired to zero. Reading r0 always returns the value 0x00000000, and a value written to r0
is ignored and lost.
The MIPS architecture has no separate status register. Instead, the conditional jump instructions test the
contents of the general-purpose registers, and error conditions are handled by the interrupt/trap
mechanism. Two separate 32-bit registers called HI and LO are provided for the integer multiplication
and division instructions.

We are planning to implement MIPS16 architecture (a simple 16 bit RISC architecture) that uses 16 bit
instructions encoding. We will be examining an implementation that includes a subset of the core MIPS
instruction set:
The memory-reference instructions load word (lw) and store word (sw) .
The arithmetic-logical instructions add, sub, and, or, and slt .
The instructions branch equal (beq) and jump (j) .

Approach to Plan for Design:

Our design will be a mix of synthesized verilog and custom circuits.
There will be an on-chip RAM in our design. So no ROM will be needed
To implement the processor we basically need Registers and memory cells (can be derived from
D Flip-flops ), ALU (arithmetic logic unit), MUX (2x1 & 4x1). We have basic gates (NAND,
NOR, XOR), pass transistor, enabled inverter, MUX (multiplexer), D Flip-flop etc. in our
library. We can obtain the ALU from basic gates.

Block Diagram :
The chip is partitioned into two top-level units: the controller and datapath, as shown in the block
diagram in Figure 2. The controller comprises the control FSM, the ALU decoder, and the two gates
used to compute PCEn. The ALU decoder consists of combinational logic to determine ALUControl.
The 8-bit datapath contains the remainder of the chip. It can be viewed as a collection of word slices or
bit slices. A word slice is a column containing an 8-bit flip-flop, adder, multiplexer, or other element.
Alternatively, the datapath can be viewed as eight rows of bit slices. Each bit slice has one bit of each
component, along with the horizontal wires connecting the bits together.

Illustration 1: MIPS Computer System

The chip partitioning is influenced by the intended physical design. The datapath contains most of the
transistors and is very regular in structure. We can achieve high density with moderate design effort by
handcrafting each word slice or bit slice and tiling the circuits together. Building datapaths using word

slices is usually easier because certain structures, such as the zero detection circuit in the ALU, are not
identical in each bit slice. However, thinking about bit slices is a valuable way to plan the wiring across
the datapath. The controller has much less structure. It is tedious to translate an FSM into gates by
hand, and in a new design, the controller is the most likely portion to have bugs and last minute
changes. Therefore, we will specify the controller more abstractly with a hardware description language
and automatically generate it using synthesis and place & route tools.

Illustration 2: Top-level MIPS block diagram

Data Sheet for External Interface :

External Interface : Oscillator, VGA, SRAM

1 pin for Oscillator
4 pins for communication with SRAM via SPI
5 pins for VGA
10 pins to interface with device

Illustration 3: External Interface

Testing chips :
To test the different circuit blocks, we will use verilog testbench and check the functionality of the
blocks. And to test our chip, there are several ways like
Plugging into a VGA screen
Use LEDs
Using External I/O signals
Using I/O pad might be a good idea as we are communicating to the chip through them. We can utilize
the unused pads and connect chip signals to check them individually.