IJSTE - International Journal of Science Technology & Engineering | Volume 2 | Issue 06 | December 2015

ISSN (online): 2349-784X

Modified Ultra-Low Power NAND Based

Multiplexer and Flip-Flop
Amit Saraswat
M. Tech Student
Department of Electronics and Communication
Chandigarh Engineering College, Mohali, Punjab, India

Chanpreet Kaur
Assistant Professor
Department of Electronics and Communication
Chandigarh Engineering College, Mohali, Punjab, India

Abstract
In this paper an ultra-low power NAND based multiplexer and flip flop is proposed. The modified design is compared to
conventional 4*1 multiplexer and shows dynamic and static power reduction up to 32.077% and 45.055% respectively while for
JK flip flop, dynamic and static power reduction up to 84.25% and 92.47%respectively. Simulations have been done on 270C
temperature and 50MHz frequency. With every selection line input dynamic power consumption is calculated, static power
consumption, delay and power delay product. The simulations have been carried out on Tanner EDA.
Keywords: NAND LATCH, FLIP FLOP, PDP, Low Power VLSI, CMOS Technology
________________________________________________________________________________________________________

I. INTRODUCTION
With the advancement of technology in VLSI design power consumption is the major issue but there is always trade-off between
power, delay and area. Designers are concerned about choosing appropriate technology to fulfil the requirements of applications.
The interest in the low power chips and systems is booming with a rapidly expanding market. Power is the rate at which energy
is delivered or exchanged. There is keen requirement of the low power systems to enhance their working capability and thereby,
save power and utilize it in the efficient manner. There are various reasons for the requirement of lower power VLSI design one
of them is as technology continues to scale down to the deep submicron process, leakage power consumption has become a
major concern in designing CMOS VLSI circuits because of reduced threshold voltage and device geometry... This results in
necessity for development of new techniques for reducing the leakage power dissipation in VLSI design. These constraints of
low power can be fulfill by using sleepy stack leakage reduction technique with DTCMOS and RBB to achieve maximum
possible static power reduction with optimized results in terms of output waveform, dynamic power consumption and delay.

II. NAND GATE BASED JK MASTER SLAVE FLIP FLOP AND 4*1 MULTIPLEXER
The input latch in Fig. 1, called the "master," is activated when the clock pulse is high. During this phase, the inputs J and K
allow data to be entered into the flip-flop, and the first-stage outputs are set according to the primary inputs. When the clock
pulse goes to zero, the master latch becomes inactive and the second-stage latch, called the "slave," becomes active. The output
levels of the flip-flop circuit are determined during this second phase, based on the master-stage outputs set in the previous
phase.Since the master and the slave stages are effectively decoupled from each other with the opposite clocking scheme, the
circuit is never transparent, i.e., a change occurring in the primary inputs is never reflected directly to the outputs.

Fig. 1: Schematic of Conventional JK Master Slave Flip flop

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Modified Ultra-Low Power NAND Based Multiplexer and Flip-Flop

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III. NAND BASED 4*1 MULTIPLEXER

In electronics a multiplexer (or MUX) is a device that selects one of several analog or digital input signals and forwards the
selected input into a single line. A multiplexer of 2n inputs has n select lines, which are used to select which input line to send to
the output. Multiplexers are mainly used to increase the amount of data that can be sent over the network within a certain amount
of time and bandwidth. A multiplexer is also called a data selector. A 4*1 multiplexer has a Boolean equation where I0, I1, I2
and I3 are the four inputs, A and B are the selector inputs and designed using inverters, 3 inputs and 4 inputs NAND gate.

Fig. 2: Schematic of Conventional NAND based 4*1 Multiplexer

IV. DESIGN AND IMPLEMENTATIONS

JK Master-Slave Flip-flop and 4*1 MUX using 2 Input NAND Gate sleepy stacks with RBB and without RBB are designed. The
JK master-slave flip-flop and 4*1 MUX has been designed with NAND gate shown in Fig. 3 and Fig.4.

Fig. 3 NAND based JK Master-Slave Flip-flop circuit diagram

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Modified Ultra-Low Power NAND Based Multiplexer and Flip-Flop

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Fig. 4: NAND based 4*1 Multiplexer Circuit Diagram

In that NAND gate sleepy stack leakage reduction technique with DTCMOS and RBB is used to achieve maximum possible
static power reduction with optimized results in terms of output waveform, dynamic power consumption and delay.

V. SIMULATION AND RESULTS

Static power consumption, dynamic power consumption, propagation delay and power delay product for JK masterslave flip-flop
and 4*1 multiplexer on 65nm technology with .8v Vdd supply with dual threshold PMOS and NMOS (High-Vth_PMOS=393.9mV, Low-Vth_PMOS=-83mV, high_Vth_NMOS=345mV and Low-Vth_NMOS=37mV) and with reverse body biasing
approach were measured. By parametric analysis on tanner EDA 14.1 it was found that static power consumption is minimum
with -2.2V reverse body bias voltage in the pull down network. While simulations we have used high Vth and low Vth
transistors with W/L=1.5 i.e. with minimum possible size of the transistor. Although there is trade-off between dynamic power
consumption and transistor width but still we have achieved dynamic power consumption because of reduced body effect. High
Vth transistors has provided the low leakage but the greater delay whereas low Vth has provided the speed but with higher
leakage. Simulations have been done on 270C temperature and 50MHz frequency. Table II to table V shows the results of 4*1
multiplexer withdifferent configurations of selection lines. With every selection line input we have calculated dynamic power
consumption, static power consumption, delay and power delay product and it is clear from the tables that except propagation
delay (PDP) of the circuit we are achieving reduction in all the parameters i.e. dynamic power consumption, static power
consumption and PDP in every state we are getting dynamic power reduction and static power reduction but on the cost of
increased propagation delay in the circuit.

VI. OUTPUT WAVEFORMS

j k_D T C M O S

v (J )

1. 1
1. 0

Volt age (V)

0. 9
0. 8
0. 7
0. 6
0. 5
0. 4
0. 3

0. 2
0. 1
0. 0
0

10

15

20

Time ( ns)

j k_D T C M O S

v (K )

1. 1
1. 0

Volt age (V)

0. 9
0. 8
0. 7
0. 6
0. 5
0. 4
0. 3
0. 2
0. 1

0. 0
0

10

15

20

Time ( ns)

j k_D T C M O S

1. 1

v ( C lk )

1. 0

Volt age (V)

0. 9

0. 8
0. 7
0. 6
0. 5
0. 4
0. 3
0. 2
0. 1
0. 0
0

10

15

20

Time ( ns)

j k_D T C M O S

1. 1

v (Q

v (Q

_B a r )

1. 0
0. 9

Volt age (V)

0. 8
0. 7
0. 6
0. 5
0. 4
0. 3
0. 2
0. 1
-0 . 0
-0 . 1
-0 . 2
0

10

15

20

Time ( ns)

j k_D T C M O S

1. 1
1. 0

Volt age (V)

0. 9
0. 8
0. 7
0. 6
0. 5
0. 4
0. 3
0. 2
0. 1
0. 0
0

10

15

20

Time ( ns)

Fig. 5: Output Waveform of JK Master Slave Flip Flop

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Modified Ultra-Low Power NAND Based Multiplexer and Flip-Flop

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Fig.6 Output Waveform of 4*1 Multiplexer

VII. RESULTS
Static power consumption, dynamic power consumption, propagation delay and power delay product for JK master slave flipflop and 4*1 multiplexer on 65nm technology with 1.1v Vdd supply with dual threshold PMOS and NMOS (HighVth_PMOS=-393.9mV, Low-Vth_PMOS=-83mV, high- Vth_NMOS=345mV and Low-Vth_NMOS=37mV).
Table I to table III shows the results of 4*1 multiplexer with different configurations of selection lines.
Table I
Percentage Dynamic power saving for 4*1
Dynamic power(nW) with DTCMOS & RBB

Dynamic power(nW) without DTCMOS & RBB

Percentage Saving (%)

3.5677e-006

4.4875e-006

20.49

A. Multiplexer with RBB and without RBB

Table - II
Percentage dynamic power saving for 4*1 Multiplexer
Dynamic power(nW) without DTCMOS & RBB

Dynamic power(nW) with Modified Design

Percentage Saving (%)

4.4875e-006

3.0480e-006

32.077

Without RBB and modified design.

Table - III
Percentage Static power saving for 4*1 Multiplexer with RBB and without RBB
State

Static power(nW) with DTCMOS & RBB

Static power(nW) without DTCMOS & RBB

Percentage Saving (%)

00

8.1139e-007

1.3165e-006

38.3

01
10
11

1.0290e-006
1.1479e-006
1.2425e-006

1.3088e-006
1.3145e-006
1.3163e-006

21.37
12.67
5.6

VIII. CONCLUSION
Design implemented by using RBB and DTCMOS stack with sleep shows dynamic and static power reduction up to 20.49% and
38.3% respectively for 4*1 multiplexer while for JK flip flop, dynamic and static power reduction up to 77% and 43.163%
respectively when compared to conventional design. When modified design is compared to conventional 4*1 multiplexer it
shows dynamic and static power reduction up to 32.077% and 45.055% respectively while for JK flip flop, dynamic and static
power reduction up to 84.25% and 92.47%respectively.

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