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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 62, NO. 6, JUNE 2015

Seven-Level PWM Inverter Employing

Series-Connected Capacitors Paralleled
to a Single DC Voltage Source
Jin-Sung Choi and Feel-soon Kang, Member, IEEE

AbstractThis paper presents an effective circuit conguration of a multilevel inverter that can increase the
number of output voltage levels with a reduced number of
circuit components. The proposed seven-level pulsewidthmodulation inverter consists of a single dc voltage source
with a series of capacitors, diodes, active switches for synthesizing output voltage levels, and an H-bridge cell. After
theoretical analysis, we carry out computer-aided simulations and experiments to verify the validity of the proposed
approach. Here, we also introduce a modied switching
strategy to solve the capacitor voltage unbalancing that
occurs in series-connected capacitors.
Index TermsInverters, multilevel systems, phase disposition (PD), pulsewidth modulation (PWM), total harmonic
distortion (THD).

I. I NTRODUCTION

ECENTLY, multilevel inverters have received great attention from the industry using high-voltage and highpower applications, which are the first motivation of multilevel
inverter studies.
The second motive is that multilevel inverters can synthesize
stepped output voltages similar to a sinusoidal wave. Many
numbers of voltage levels ensure a high-quality output voltage,
which shows a good total harmonic distortion (THD) with low
dv/dt stress and a small size of output filter. However, it needs
a large number of circuit components [1][5]. In conventional
multilevel inverters, a cascaded H-bridge multilevel inverter
(CHB) is one of the best approaches to increase the number of
output voltage levels due to modularization and easy expansion
[6], [7]. However, when a CHB increases H-bridge cells, it
also increases the number of switches and independent input
dc voltage sources. One of the solutions to reduce the number
of components in a CHB is to use asymmetrical dc voltage

Manuscript received April 17, 2014; revised August 19, 2014; accepted October 20, 2014. Date of publication November 14, 2014; date
of current version May 8, 2015. This work was supported by the Basic
Science Research Program through the National Research Foundation
of Korea funded by the Ministry of Education, Science and Technology
under Grant 2012R1A1A2006120.
J.-S. Choi was with Hanbat National University, Daejeon 305-719,
Korea. He is now with New Power Plasma Company, Ltd., Pyeongtaek
451-852, Korea.
F. Kang is with the Department of Electronics and Control Engineering, College of Information Technology, Hanbat National University,
Daejeon 305-719, Korea (e-mail: feelsoon@hanbat.ac.kr).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TIE.2014.2370948

Fig. 1.

Circuit configuration of the proposed seven-level PWM inverter.

sources [8], [9]. When dc voltages are scaled in power of

three, it can maximize the number of output voltage levels.
However, it still increases independent dc voltage sources to
generate higher output voltage levels. To solve this problem,
a multilevel inverter employing a cascaded transformer was
introduced in [10]. It also uses a combination of asymmetrical
voltage sources to synthesize multilevel output voltages. The
most advantageous achievement is that it just employs a single
dc voltage source. However, the cascaded transformer makes
the system bulky because it operates in a low frequency. To
alleviate this problem, a multilevel inverter using four floating
power supplies was introduced in [11]. However, it needs a
front-end transformer to obtain independent dc voltage sources.
To overcome this problem, transformerless circuit topologies
were presented in [12][18]. Usually, these kinds of multilevel
inverters were modified and developed from the CHB. In [12],
a packed U-cell multilevel inverter was presented. It shows
very good performance in the reduction of circuit components.
However, it increases conduction losses when it generates each
voltage level because the circulating current passes through
three switching devices in each level generation. Moreover, the
voltage across the capacitor has big ripples, although it uses
a bulky capacitor of 5000 F. Multilevel inverters employing
bidirectional switches and series-connected capacitors were
proposed in [13] and [14]. Theoretically, they can generate a
large number of output voltage levels over 125 levels with a
reduced number of circuit components. However, each capacitor needs individual dc-to-dc converters to obtain dc voltage
sources. A modular multilevel converter was introduced in
[15]. It has a good modular characteristic; thus, it is easy to
be extended to high voltage levels. However, it increases the
number of bulky capacitors and switches compared with other
counterparts. A multilevel inverter employing series-connected

0278-0046 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

CHOI AND KANG: PWM INVERTER EMPLOYING CAPACITORS PARALLELED TO SINGLE DC VOLTAGE SOURCE

3449

Fig. 2. Generation of each output voltage level and load current path. (a) Vdc . (b) 2Vdc /3. (c) Vdc /3. (d) 0. (e) Vdc /3. (f) 2Vdc /3. (g) Vdc .
(h) Opposite current flow at the Vdc and 2Vdc /3 levels. (i) Opposite current flow at the Vdc /3 level. (j) Opposite current flow at the zero level.
(k) Opposite current flow at the Vdc /3 level. (l) Opposite current flow at the Vdc level.

dc voltage sources was proposed in [16]. It consists of a

level-generating stage and a polarity selection part to reduce
the switching losses. However, it fails to reduce the number
of dc voltage sources when it increases the output voltage
levels. A multilevel inverter using switched series/parallel dc
voltage sources was introduced in [17]. Although it can increase
the number of output voltage levels, the switching pattern is
complex, and it increases conduction losses. A photovoltaic
multilevel inverter using series-connected capacitors was investigated in [18]. It does not explain how to balance the capacitor
voltage, although the dc-link voltage is controlled by the frontend boost converter.
Most of the previous approaches given in [12][18] use
series-connected capacitors. It is a useful way to minimize the
number of independent dc voltage sources when it increases
the number of output voltage levels once it solves the capacitor
voltage unbalancing problem.
In this paper, we present an effective circuit configuration
of a multilevel inverter that can increase the number of output
voltage levels with a reduced number of circuit components.
It consists of a single dc voltage source paralleled to seriesconnected capacitors, two diodes, three switches for synthesizing output voltage levels, and an H-bridge cell. To verify
the validity of the proposed approach, we carry out computer-

aided simulations and experiments. Here, we also introduce

a modified pulsewidth modulation (PWM) control scheme to
solve the capacitor voltage unbalancing that occurred in seriesconnected capacitors.
II. P ROPOSED S EVEN -L EVEL PWM I NVERTER
A. Circuit Conguration
Fig. 1 shows a circuit configuration of the proposed sevenlevel PWM inverter. It has a single dc voltage source, which is
divided by three capacitors connected in series. Let us assume
that all components are ideal and that the circuit is in a steady
state. Each capacitor voltage is equal to Vdc /3. Then, we can
obtain seven levels in the output voltage wave, i.e., Vdc , 2Vdc /3,
Vdc /3, 0, Vdc /3, 2Vdc /3, and Vdc . The switches in an
H-bridge cell (S1 S4 ) work to determine the polarity of the output voltage with the highest (or lowest) voltage level, i.e., Vdc
(or Vdc ). Other voltage levels are generated by S5 , S6 , and S7 .
B. Generation of Output Voltage Levels
For better understanding, every current path for generating
seven levels is given in Fig. 2. Here, the highlighted line

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and the bigger symbol caption mean the conducting line and
components, respectively.
Level Vdc : Fig. 2(a) shows a current path when the output
voltage is Vdc . Three capacitors connected in series supply
energy to the output load. It discharges through S1 and S4 . If a
load is an inductive load and the direction of the load current is
opposite, the current flows through DS1 and DS4 , and it charges
the capacitor stack, as given in Fig. 2(h).
Level 2Vdc /3: Fig. 2(b) shows a current path when the
output voltage is 2Vdc /3. Two capacitors C2 and C3 feed
the output load. It discharges through S5 , D1 , and S4 . When
the direction of the load current is opposite, there is no current
path under this switching state. At this time, the load current
flows through DS1 and DS4 , and it charges the capacitor stack,
as given in Fig. 2(h). Regardless of the load current flows, the
output voltage is clamped as the 2Vdc /3 level by the switching
state given in Fig. 2(b).
Level Vdc /3: Fig. 2(c) shows a current path when the output
voltage is Vdc /3. The lower end capacitor (C3 ) supplies energy
to the output load. It discharges through DS6 , S7 , D1 , and S4 .
If the direction of the load current is opposite, the load current
flows through D2 , S7 , DS5 , and DS4 , as shown in Fig. 2(i).
Level 0: To generate a zero level, two switching schemes
can be considered. The basic idea to generate a zero level is
voltage cancelation. Fig. 2(d) shows a current path when it synthesizes a zero level. When S2 and S4 turn on simultaneously,
the output voltage becomes zero. The other method is to turn
S1 and S3 on at the same time. When the direction of the load
current is opposite, the current will flow, as shown in Fig. 2(j).
Level Vdc /3: Fig. 2(e) shows a current path when it produces the Vdc /3 level. The upper capacitor (C1 ) supplies
energy to the output load. If the direction of the load current
is opposite, the current flows, as shown in Fig. 2(k).
Level 2Vdc /3: Fig. 2(f) shows a current path when the
output voltage is 2Vdc /3. Two capacitors C1 and C2 supply
energy to the output load. When the load current reverses, it
flows through DS2 and DS3 , as given in Fig. 2(l). Regardless of
the load current flows, the output voltage sustains the 2Vdc /3
level by the switching state given in Fig. 2(f).
Level Vdc : Fig. 2(g) shows a current path when the output
voltage is Vdc . Three capacitors connected in series supply
energy to the output load. If the load current is opposite,
the current flows through DS2 and DS3 , and it charges the
capacitor stack, as given in Fig. 2(l).

C. General Switching Scheme

Fig. 3 shows a general phase-disposition switching scheme
for controlling the proposed seven-level PWM inverter. It uses
a reference and three carrier waves, which have the same
frequency and amplitude but different offset voltages [19], [20].
Table I lists the switching patterns for generating seven output
voltage levels. By comparing the reference and each carrier
wave, it produces command signals (Ca , Cb , and Cc ). As shown
in Table I, when vcar1 and vcar2 are lower than vref , Ca , and Cb
become 1, and vcar3 is 1 when it is higher than vref . One cycle
of the reference voltage is divided into six modes according to

Fig. 3. Switching pattern for generating the seven-level PWM output

voltage.

the output voltage levels, and the corresponding period (Pn ) for
each mode is determined by
Mode 1 : P1 = 0 < t < 1 and P5 = 4 < t <

(1)

Mode 2 : P2 = 1 < t < 2 and P4 = 3 < t < 4 (2)

Mode 3 : P3 = 2 < t < 3

(3)

Mode 4 : P6 = < t < 5 and P10 = 8 < t < 2 (4)

Mode 5 : P7 = 5 < t < 6 and P9 = 7 < t < 8

(5)

Mode 6 : P8 = 6 < t < 7 .

(6)

By the logical combination of Ca , Cb , Cc , and Pn , it generates switching signals (Sn ). The period (Pn ) of each mode
varies in terms of switching angle n , which is determined by
the modulation index (Ma ). By using logical expressions AND,
OR, and NOT , each switching signal is determined by
S1 = Ca (P6 + P10 ) + Cc P3

(7)

S2 = Ca (P1 + P5 ) + Cc P8
S3 = P6 + P7 + P8 + P9 + P10

(8)
(9)

S4 = P1 + P2 + P3 + P4 + P5
S5 = Cb (P2 + P4 ) + Cc P3

(10)
(11)

S6 = Cb (P7 + P9 ) + Cc P8
S7 = Ca (P1 + P5 + P6 + P10 )

(12)

+ Cb (P2 + P4 + P7 + P9 ).

(13)

CHOI AND KANG: PWM INVERTER EMPLOYING CAPACITORS PARALLELED TO SINGLE DC VOLTAGE SOURCE

TABLE I
O UTPUT VOLTAGE L EVELS ACCORDING TO THE S WITCHING S TATE

As shown in Fig. 3, S1 works at Mode 3 (vout = 2Vdc /3 or

Vdc ) and Mode 4 (vout = 0 or Vdc /3). S2 works at Mode 1
(vout = 0 or Vdc /3) and Mode 6 (vout = 2Vdc /3 or Vdc ).
S3 works at Modes 46, where vout is negative. S4 works
at Modes 13, where vout is positive. Hence, S3 and S4 are
operating at the same frequency with the reference (vref ).
S5 works at Mode 2 (vout = Vdc /3 or 2Vdc /3) and Mode 3
(vout = 2Vdc /3 or Vdc ). S6 works at Mode 5 (vout = Vdc /3
or 2Vdc /3) and Mode 6 (vout = 2Vdc /3 or Vdc ). S7
works at Mode 1 (vout = 0 or Vdc /3), Mode 2 (vout = Vdc /3
or 2Vdc /3), Mode 4 (vout = 0 or Vdc /3), and Mode 5
(vout = Vdc /3 or 2Vdc /3).
Table II shows switching angle n according to modulation
ratio Ma . To synthesize the seven levels on the output voltage
wave, one reference and three carrier waves are used. Hence,
modulation ratio Ma is given by
Am
Ma =
(14)
3Ac
where Ac is the amplitude of a carrier wave, and Am is the
amplitude of a reference wave. Thus, the output voltage is
defined by
vout = Ma sin t.

(15)

When Ma is lower than 0.33, the output voltage has three

levels. Between 0.33 and 0.66, the output voltage has five levels,
and with an Ma higher than 0.66, it shows seven output voltage
levels.

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TABLE II
S WITCHING A NGLES ACCORDING TO THE M ODULATION I NDEX

Fig. 4. Equivalent circuit of the proposed seven-level inverter and

the operational waveform. (a) Equivalent circuit with average currents.
(b) Output voltage and lagging load current.

D. Origin of Capacitor Voltage Unbalance

The voltage balancing of series-connected capacitors acting
as an energy tank is very important to generate exact output
voltage levels in the proposed multilevel inverter. Thus, we first
find the origin of the capacitor voltage unbalance.
Fig. 4(a) shows the equivalent circuit of the proposed sevenlevel inverter. Fig. 4(b) describes the stepped output voltage and
the lagging load current. Assuming that the sinusoidal lagging

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load current is iout = Im sin(t ), then the average input

node current i1 is given by

 3
1
Im
cos cos 3 .
I1(avg) =
iout d(t) =
(16)
2

Similarly, the average input node currents i2 and i3 are given

as follows:
3
1
Im
cos (cos 2 cos 3 ) (17)
I2(avg) =
iout d(t) =
2

2
2

I3(avg) =

1
2

iout d(t) =

Im
cos (cos 1 cos 2 ).

(18)

At this time, each capacitor voltage should be regulated so

that each capacitor supplies the average current per cycle as
follows:
Im
cos cos 3
(19)
IC1(avg) = I1(avg) =

Im
cos cos 2 (20)
IC2(avg) = I1(avg) + I2(avg) =

IC3(avg) = I1(avg) + I2(avg) + I3(avg)

Im
cos cos 1 .
=
(21)

Hence, IC1(avg) < IC2(avg) < IC3(avg) for 1 < 2 < 3 .

It means that more charges flow from lower capacitor C3 than
upper capacitors C1 and C2 . This is the main reason for the
voltage unbalancing in the series-connected capacitors of the
proposed circuit topology. Hence, each capacitor voltage should
be regulated to feed the appropriate amount of average current
by satisfying
IC1(avg) = IC2(avg) = IC3(avg) .

(22)

is directly related to the voltage regulation across C1 and C3 .

Fig. 5(a) shows the modified control method for regulating the
C2 voltage. It controls the amplitude of the carrier wave (vcar2 ),
which is compared with the reference (vref ). The range of the
amplitude is determined by
vcar1_ max = vcar2_ min vcar2

From the relationship of (19)(21), we obtain

IC2(avg) cos 3
IC2(avg)
cos 1
=
=
IC1(avg) cos 2
IC3(avg)
cos 2
IC3(avg) cos 3
=
.
IC1(avg) cos 1

Fig. 5. Modified control scheme for capacitor voltage balancing.

(a) Variation of Cb according to the amplitude of vcar2 . (b) Geometrical
relation between the carrier wave (vcar2 ) and the reference (vref ).

vcar2_ max = vcar3_ max .

(23)

From (23), we can know that the capacitor voltage unbalancing occurs depending on just the switching angles of 1 , 2 ,
and 3 regardless of the load conditions. In other words, the
difference between the charging and discharging of the seriesconnected capacitors is determined by the switching angles. It
means that the different periods for each voltage level are the
cause of the capacitor voltage unbalance [21][24], [28].
E. Modied Switching Scheme for Voltage Balancing
To solve the capacitor voltage unbalancing, we introduce
a modified switching pattern for the proposed multilevel inverter. The main idea of the proposed control strategy is to
regulate the charging and discharging rate of capacitor C2 . It
ensures the voltage regulation of C2 and the voltage balance of
the upper and lower capacitors. Because C2 locates between
C1 and C3 , the charging and discharging current of C1 and
C3 should flow through C2 . Thus, the voltage regulation of C2

(24)

As shown in Fig. 5(a), control signal Cb changes its duty

ratio according to the different amplitudes of vcar2 . The duty
ratio of Cb is directly related to the duty ratios of S5 and S7 for
the +2Vdc /3 level generation, as given in (11), (13), and Fig. 3.
When S5 turns on, as shown in Fig. 2(b), the output voltage
becomes +2Vdc /3. This period is a discharging time of C2 . On
the other hand, when S5 turns off and S7 turns on, as shown
in Fig. 2(c), the output voltage level becomes +Vdc /3, which
allows the charging of C2 .
Fig. 5(b) shows two carrier waves that have different amplitudes, i.e., Vp,1 and Vp,2 , respectively. We assume that the
carrier frequency is very high so that the amplitude of the
consecutive intersections of the reference and the carrier wave
at positions i and i is constant. Then, the mathematical
relation for the pulsewidth of Cb according to the variation of
the amplitude of vcar2 is found using a geometrical relation, as
shown in the right-hand side of Fig. 5(b). From the geometry of
the triangle ABC, we have
hy1 = Vp, 1 , hy2 = Vp, 2 , hx = Vp, ref sin i y =

T
o . (25)
2k

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TABLE III
S PECIFICATION OF THE S IMULATION AND E XPERIMENT

Here, k means the number of pulses. T is the period of the

+2Vdc /3 level. o means the carrier frequency. Then, each
pulsewidth (d1 and d2 ) of the ith pulse is given by
d1 = x 1

d2 = x 2 .

(26)

Since 1 = 1 and 2 = 2 , then we have

hx
hy1 hx
hy2
,
.
=
=
x1
y
x2
y

(27)

Fig. 6. Simulation results with the general switching scheme, and the
capacitor voltage unbalancing and its effect on the output voltage levels.
(a) Output voltage (vout ) with disappearing voltage levels. (b) Voltage
unbalancing in series-connected capacitors.

Substituting (25) into (27) produces

d1 =

1
1
T
T
o
o
Vp, ref sin i , d2 =
Vp, ref sin i .
2k Vp, 1
2k Vp, 2
(28)

Therefore, the difference between d1 and d2 is given by



1
T
1
o Vp, ref sin i
d = d1 d2 =

. (29)
2k
Vp, 1
Vp, 2
In (29), the difference (d) of both pulsewidths is inversely
proportional to the amplitude of the carrier wave (vcar2 ). Thus,
we can find that the duty ratio of Cb can be proportionally controlled by the amplitude of vcar2 . It means that the duty ratios of
S5 and S7 are also proportionally controlled by the amplitude
of vcar2 . Thus, the proposed control method, which controls the
amplitude of vcar2 , is a reasonable way to manage the voltage
across the middle capacitor. In summary, when the amplitude of
vcar2 increases, the pulsewidth of Cb decreases. Then, the duty
ratio of S5 increases, resulting in the increase in the discharging
period of C2 . On the other hand, when the amplitude of vcar2
decreases, the pulsewidth of Cb increases. Then, the duty ratio
of S5 decreases, and S7 increases, resulting in the increase in
the charging period of C2 . During the negative voltage level
(2Vdc /3), S6 works for the same operation instead of S5 .
III. S IMULATION AND E XPERIMENTAL R ESULTS
To verify the validity of the proposed seven-level PWM
inverter, we carried out computer-aided simulations using PSIM
and experiments using a prototype of 1 kW. The input dc
voltage is set to dc 150 V; hence, each capacitor voltage is

Fig. 7. Simulation results with the modified switching method.

(a) Output voltage (vout ) with seven levels. (b) Balanced voltage in
series-connected capacitors.

divided into dc 50 V in an ideal case. The frequency of an output

voltage is set to 60 Hz. The specifications of the simulation and
experiment are given in Table III.
Fig. 6 shows the simulation results of the output voltage
and the capacitor voltage with a general switching method. In

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Fig. 8. Simulation results of the voltage across the switching devices

when it synthesizes the seven output voltage levels with Ma = 1.0.

Fig. 9.

Prototype for the experiment.

Fig. 11. Experimental results with a resistive load, the output voltages
before and after filtering, and the FFT result. (a) Ma = 0.6. (b) Ma =
1.0. (c) Ma = 1.4.

Fig. 10. Experimental result and each capacitor voltage of the seriesconnected capacitors.

Fig. 6(a), we can find that the middle voltage levels (2Vdc /3)
disappeared as time goes by. At 0.25 s, the output voltage level
shows just five levels similar to that of a five-level PWM inverter, which has two series-connected capacitors. It means that

only the upper and lower capacitors (C1 and C3 , respectively)

are charged as Vdc /2, but the middle capacitor (C2 ) failed to
charge up because of insufficient charging time, as shown in
Fig. 6(b).
Fig. 7 shows the simulation results of the output voltage and
the capacitor voltages with the modified switching scheme. The
output voltage shows exactly seven levels, as given in Fig. 7(a).
We can know that the modified switching method works well;
thus, each capacitor voltage is maintained at near Vdc /3 (50 V),
as shown in Fig. 7(b).
Fig. 8 shows the simulation results of the voltage across
the switching devices when it produces seven output voltage
levels with Ma = 1.0. The blocking voltage of S5 and S6 is

CHOI AND KANG: PWM INVERTER EMPLOYING CAPACITORS PARALLELED TO SINGLE DC VOLTAGE SOURCE

Fig. 12. Experimental results with an inductive load, the output voltages before and after filtering, and the load current according to the
modulation index. (a) Ma = 0.6. (b) Ma = 1.0. (c) Ma = 1.4.

about 66% of the input dc voltage. The blocking voltage of S7

is about 33% of the input dc voltage. However, the blocking
voltage of the H-bridge switches (S1S4 ) is equal to the input
dc voltage, and it is proportional to the output voltage. Thus, the
proposed circuit topology is unsuitable to apply high-voltage
applications. In addition, we need careful attention to reduce
the conduction losses in the middle switches and reverse the
recovery losses caused by the turning off of the diodes during
switching.
To prove the actual performance of the proposed seven-level
PWM inverter with the modified switching scheme, we carry
out experiments using a prototype shown in Fig. 9. To generate
exact switching signals, the proposed system employs a digital
controller using a DSP 28335, and it adds an output LC filter
because it is insufficient to produce a sinusoidal output voltage
wave with only seven levels, but the size of the filter is smaller
than typical inverters.
Fig. 10 shows the experimental result of each capacitor
voltage. The voltage across the middle capacitor (C2 ) maintains
Vdc /3 (50 V). Other capacitor voltages also support Vdc /3,
with some voltage ripples affected by an input voltage source
(Vdc ). From this result, we know that the modified switching
scheme sufficiently solves the voltage unbalancing problem that
occurred in series-connected capacitors.

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Fig. 13. Experimental results with a rectifier load, the output voltages
before and after filtering, and the load current according to the modulation index. (a) Ma = 0.6. (b) Ma = 1.0. (c) Ma = 1.4.

Fig. 11 shows the experimental waveforms of the output

voltages before and after filtering with a fast Fourier transform
(FFT) result. Here, the output load is a resistor of 10 .
Fig. 11(a) shows the result when the modulation index is 0.6.
Because Ma is lower than 0.66, the output voltage shows just
five levels. When Ma is 1.0, the output voltage has seven levels,
as shown in Fig. 11(b). In this case, the filtered output voltage is
slightly distorted due to the modified switching scheme. During
the period of the Vdc level, the optimal switching pattern is to
iterate between Vdc and 2Vdc /3, but the modified switching
pattern additionally iterates between 2Vdc /3 and Vdc /3, as
shown in the circle in Fig. 11(b). However, the measured THDv
meets the general requirement of 5% below. In the case of
overmodulation given in Fig. 11(c), both flat tops of the output
voltage reduce the PWM waves; thus, the filtered output voltage
looks like a square wave. Fig. 12 shows the experimental
waveforms of the output voltages when the proposed inverter
connects to an inductive load. The output voltages according
to the modulation index are the same as the results shown in
Fig. 11. The difference is that the load current lags to the output
voltage due to the intrinsic characteristic of the inductive load.
Fig. 13 shows the experimental waveforms of the output
voltages when the proposed inverter connects to a rectifier
load. The output voltages are the same as the results shown in

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Fig. 14. Experimental results of the voltage across each switching

device at Ma = 1.0. (a) Drain-to-source voltage of S1 , S2 , S3 , and S4 .
(b) Drain-to-source voltage of S5 , S6 , and S7 .

Figs. 11 and 12. However, the filtered output voltage has more
distortion because of the modified switching pattern and the
load current that has a short conduction angle with a somewhat
high current peak due to the intrinsic characteristic of the
rectifier load.
Fig. 14(a) shows the experimental results of the drain-tosource voltage of each switching device located in an H-bridge
cell. Fig. 14(b) shows the drain-to-source voltages of the middle
switches. These experimental results are exactly the same as the
simulation results given in Fig. 8.
Fig. 15(a) shows the experimental results of the seriesconnected capacitors and the output voltage when the modulation index is changed from 0.6 to 0.8. Thus, the number
of the output voltage levels changes from five levels to seven
levels. Fig. 15(b) shows the results when the modulation index
is changed from 0.8 to 0.6. In both cases, we can find that the
output voltage goes fast into the steady state and that there is no
influence on the capacitor voltages.
Fig. 16(a) shows the experimental results of the seriesconnected capacitors and the output voltage at Ma = 0.8 when
the output frequency is decreased from 60 to 50 Hz. Fig. 15(b)
shows the results when the output frequency is increased from
60 to 70 Hz. In both cases, there is no influence on the capacitor
voltages regardless of the variation of the output frequency.
The investigation of THDv is important since the modified
switching pattern slightly departs from the optimal switching
pattern for the best THD, as shown in Fig. 11(b). Fig. 17(a)
shows THDv according to the modulation index. It was measured with a 1-kW resistive load. It sufficiently meets the

Fig. 15. Experimental results of the capacitor voltage and the output
voltage according to the variation of Ma . (a) From Ma = 0.6 to Ma =
0.8. (b) From Ma = 0.8 to Ma = 0.6.

general requirement of 5% below when the modulation index is

set between 0.6 and 1. However, it fails to meet the requirement
when Ma is lower than 0.6 and the overmodulation. Fig. 17(a)
also compares THDv with the work in [18]. When the output
voltage is seven levels, the THDv of the proposed approach
and that in [18] are measured as 5% below. At Ma = 1.0, the
work in [18] is better than the proposed approach because the
proposed approach strays from the optimal switching pattern
because of the capacitor balancing control. On the other hand,
when the output voltage is five levels at Ma = 0.6, the THDv
of the proposed approach is better than that in [18] since the
carrier frequency is much higher than in [18].
Fig. 17(b) shows the efficiency comparison according to
the modulation index when the output power varies from
100 W to 1 kW. It shows that the efficiency at a higher Ma is
better than that in a lower Ma . In the overmodulation, it shows
high efficiency because the switching losses are considerably
reduced. At 800 W and over Ma = 0.6, the proposed inverter
has the best efficiency at 92.3% on average.
In Table IV, we compare the number of circuit components
with its counterparts, i.e., flying capacitors (labeled as FC),
diode clamped (labeled as DC), cascaded H-bridge (labeled as
CH), [12], [13], [16], and [18] when they generate a sevenlevel output voltage. In Table IV, the minimum number of
components is in bold, and the parentheses of the proposed

CHOI AND KANG: PWM INVERTER EMPLOYING CAPACITORS PARALLELED TO SINGLE DC VOLTAGE SOURCE

Fig. 16. Experimental results of the capacitor voltage and the output
voltage according to the variation of the output frequency. (a) From
fout = 60 Hz to fout = 50 Hz. (b) From fout = 60 Hz to fout = 70 Hz.

mean the comparison results with the best case. In this comparison, the best approaches in the viewpoint of saving the
number of switches are the works in [12] and [18]. However,
the work in [12] has a higher conduction loss and voltage
across the capacitor and has big ripples, although it employs
a bulky capacitor of 5000 F . The work in [18] is also good
in reducing the number of switches, but it needs eight diodes.
In the case of the proposed approach, it increases one switch,
two diodes, and three capacitors compared with the best case
of the counterparts. We can say that the most advantage of the
proposed approach is the number of independent dc voltage
sources.
Table V shows the comparison result of the blocking voltage
on the switching devices, particularly the switching devices
located at the output terminal. To compare the blocking voltage
on the switching devices, a known factor, i.e., the maximum
voltage ratio (MVR), is used as the performance index as
follows [25]:
Maximum voltage ratio (MVR) =

Vk(max)
.
Vout(max)

(30)

Here, Vk(max) means the maximum value of the H-bridge

(or the submodule at the output terminal). Vout(max) is the
maximum value of the output voltage. The smaller value of
the MVR means the reduced voltage stress on the switching

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Fig. 17. Comparison of THDv and the efficiency. (a) Comparison of

THDv according to the modulation index. (b) Efficiency according to the
modulation index and the output power.
TABLE IV
C OMPARISON OF THE N UMBER OF C IRCUIT C OMPONENTS

devices. In Table V, the cascaded H-bridge multilevel inverter

is the best in reducing the blocking voltage on the switching
devices. The MVR of the proposed approach is 1, which is
similar to that in [18]; this means that they are unsuitable for a
high-voltage application, although they can reduce the number
of switching devices and independent dc voltage sources.
IV. C ONCLUSION
We proposed a multilevel PWM inverter that can effectively
increase the number of output voltage levels with a single
dc voltage source. In order to synthesize the seven-level output voltage, the proposed multilevel inverter needs a single
dc voltage source with a series connection of three capacitors, two diodes, three active switches for synthesizing the
output voltage levels, and an H-bridge cell. After theoretical

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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 62, NO. 6, JUNE 2015

TABLE V
C OMPARISON OF THE B LOCKING VOLTAGE ON THE S WITCHING D EVICES

analysis, we implemented computer-aided simulations to verify

the validity of the proposed approach. Here, we introduced a
modified switching scheme to solve the voltage unbalancing
that occurred in the series-connected capacitors. Finally, we
carried out experiments using a 1-kW prototype, and we compared the number of main components, the blocking voltage
on the switching devices, and THDv with previous multilevel
inverters. As a result, we claim that the proposed seven-level
PWM inverter can be a good candidate, which can substitute
for the conventional PWM inverters in the power rating of a
common use.
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Jin-Sung Choi received the B.S. and M.S. degrees from Hanbat National University, Daejeon,
Korea, in 2012 and 2014, respectively.
He is currently an Assistant Manager with the
Research and Development Center, New Power
Plasma Company, Ltd., Pyeongtaek, Korea. His
research interests include the area of power
electronics, including the design and control
of multilevel inverters. He particularly has researched multilevel-inverter design for electric
vehicles.

CHOI AND KANG: PWM INVERTER EMPLOYING CAPACITORS PARALLELED TO SINGLE DC VOLTAGE SOURCE

Feel-soon Kang (S00M03) received the M.S.

and Ph.D. degrees from Pusan National University, Busan, Korea, in 2000 and 2003,
respectively.
From 2003 to 2004, he was with the Department of Electrical Engineering, Graduate School of Engineering, Osaka University,
Osaka, Japan, as a Postdoctoral Fellow. Since
September 2004, he has been with the Department of Electronics and Control Engineering,
College of Information Technology, Hanbat National University, Daejeon, Korea, as a Professor. His research activities
include the area of power electronics, including the design and control of
various power conversion systems for display, renewable energy, electric
vehicles, and submarines.
Dr. Kang is a member of The Korean Institute of Electrical Engineers
(KIEE) and The Korean Institute of Power Electronics (KIPE). He served
as a Vice Chairman of the Organizing Committee for the 2009 International Telecommunications Energy Conference, the 2010 International
Conference on Electrical Machines and Systems (ICEMS), the 2011
International Conference on Magnetically Levitated Systems and Linear Drives (MAGLEV), the 2012 IEEE Vehicle Power and Propulsion
Conference, and ICEMS 2013. He served as an Associate Editor of
the IEEE T RANSACTIONS ON I NDUSTRIAL E LECTRONICS from 2004 to
2011. Since 2012, he has been an Editor of the Journal of International
Conference on Electrical Machines and Systems. He was a recipient of
awards and prizes from the IEEE Industrial Electronics Society, and he
was the recipient of Academic Awards from Pusan National University
and Hanbat National University in 2003 and 2005, respectively. He was
also the recipient of several Best Paper Awards from KIEE and KIPE.

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