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Summer 2014

S P E C I A L

D A C

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IP INTEGRATION: NOT
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By Gabe Moretti, Senior EDA-IP Editor

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tDAC Issue 2014

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By John Blyler, Chief Content Ofcer

EDITOR'S NOTE

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veryone talks about the increasing


consolidation of the EDA tools
market, but few provide quantified
data for accurate predictions.
Mergers wont guarantee the survival of
chipmakers, explained Microchips CEO
Steve Sanghi in a recent EETimes article
by Rick Merritt. Mergers are marking
the chip industrys maturity as companies get bigger to survive
harsher times ahead.
The consolidation of the EDA market is nothing new. The
past three years have been a particularly active period. But
consolidation can not continue forever in a market where
venture-capital funding is declining for semiconductor start-ups.
Is there any way to gauge the level of consolidation in the market
as a whole and in particular the EDA tools segment? Further, is
there a level of consolidation at which IP design and reuse will
be adversely affected? Well start with the first question.
Consolidation is the merger and acquisition of many smaller
companies into much larger ones. This process is a natural part
of market segment growth with well delineated phases.
Both the acquired and the acquiring companies have its own
product life cycle process for the development of chips. EDA
tools automate much of the design process, which is a necessity
for todays extremely complex system-on-chips (SoC). But how
is the product lifecycle changed when one company is acquired
by another?
The Consolidation Curve, purportedly the founding premise
of the QHS group, represents a product life-cycle as it is
influenced by consolidation in a maturing industry. Simply put,
the affect of consolidation is to significantly shorten the duration
of the life-cycle.
If the consolidation occurs from an outside influence such as
investment bankers or activist investors (recall Icahn vs. Mentor),
then the shortening of the curve results from the fees the bankers
or investors collect immediately after the consolidation.

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But what happens if the consolidation occurs amongst the


legitimate players of the industry, e.g. Cadences recent
acquisition of Jasper and Forte? According to a Harvard Business
Review paper, most industries progress predictably through a
clear consolidation life cycle. The researched paper concluded
that, once an industry forms, it will move through four stages
of consolidation: Opening, Scale, Focus and finally BalanceAlliance. Interestingly, the semiconductor industry is missing
from this curve, which was first constructed 12 years ago.
Where would the semiconductor industry be placed on this
curve? I have no objective data to determine this point. But
consider this comment which Pradeep Chakraborty attributes
to Mentors CEO Wally Rhines: Turnover among the
top 10 in the semiconductor industry has been high, with
more than 50 percent disappearing from the top ten over the
last 50 years. This would seem to place the semiconductor
industry solidly in the Stage 3 (Focus) portion of the Harvard
consolidation curve.
Lets conjecture a bit further, separating out the EDA-IP tools
segment from the entire semiconductor market. Again, I have no
concrete data to offer. However, consider this footnote from last
years EDA Consortium (EDAC) panel discussion of leading
CEOs. The question posed to the EDA CEOs was whether
the EDA industry would consolidate from three down to two
major players? A non-scientific poll of EDAC members revealed
that 48% agreed while 52% disagreed. Remember, this question
speculated about a major player consolidation. Such a move
could further hasten the consolidation of the few remaining
startups in the EDA industry.
With roughly half of the EDAC members agreeing that the
EDA market will shrink from 3 to 2 major players, this would
place the tools industry quickly approaching Stage 4 Balance
and Alliance. Semiconductor IP (SIP) suppliers are not immune
to the flattening of the EDA market. Consolidation of the
tools industry may affect the third-party IP supply market.
Quantifying that affect will be the topic of a future blog.
John Blyler can be reached at: jblyler@extensionmedia.com

DAC Issue 2014t

IN THE NEWS
#Z$BSPMJOF)BZFT 4FOJPS&EJUPS4ZTUFNT

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For anyone worried about the next generation of engineers,
can be reassured as 15-year old Nathan Han (pictured)
receives the Gordon E Moore Award from Intel. The Boston
teenager won the $75,000 prize for devveloping a machine
learning software tool to study mutations of a gene linked to
breast cancer. Also honored at this years Intel International
Science and Engineering Fair, were Lennart Kleinwort of
Germany and Shannon Lee of Singapore who each received
$50,000 prizes as Intel Foundation Young Scientist Awards.
winners Lennart Kleinwort (15) of Germany and Shannon
Lee (17) of Singapore each received prizes of US$50,000
from the Intel Foundation.
Scientists at the University of Reading have found a link
between thunderstorm activity and streams of high energy
particles accelerated by the solar wind. The findings provide
evidence that particles from space help trigger lightning
bolts.
The researchers propose that the electrical properties of the
air are altered as the incoming charged particles from the
solar wind collide with the atmosphere.

Feng Wang, a condensed matter physicist with Berkeley


Labs Materials Sciences Division and UC Berkeleys Physics
Department, as well as an investigator for the Kavli Energy
NanoSciences Institute at Berkeley, led a study in which
photo-induced doping of GBN heterostructures was used to
create pn junctions and other useful doping profiles while
preserving the materials remarkably high electron mobility.
Next month is the 70th anniversary of the D-Day landings
in France, a major part of the Allied strategy in World War
II. Dassault Systmes has digitally reconstructed some
of the engineering feats, conducted under duress, of the
Arromanches artificial harbour, landing craft and gliders
using 3D simulation software.

Solar wind streams rotate with the sun, sweeping past


the earth at regular intervals, accelerating particles into
the atmosphere. The solar wind streams can be tracked by
spacecraft, potentially allowing meterologists to predict the
severity of hazardous weather events many weeks in advance.
Researchers at Berkeley Lab and the University of California
Berkeley have demonstrated a technique where the electronic
properties of GBN (graphene boron nitride) heterostructues
can be modified with visible light. Illumination of a GBN
heterostructure even with just an incandescent lamp can
modify electron-transport in the graphene layer by inducing
a positive-charge distribution in the boron nitride layer that
becomes fixed when the illumination is turned off.

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IN THE NEWS
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Students at Rice University have used thermoelectric


generators to transfer heat from cooling pipes for several
functions. They can generate electricity while cooling the
station and its components, or reverse the process and send
hot coolant (at a desired temperature) back into the station.
The project is one of six sponsored by NASAs X-Hab
Academic Innovation Challenge. The team consists of
electrical engineering majors, Mira Chen and Lee Xiong;
mechanical engineers, Sophie Xu and Yixuan Wang;
double majors, Shota Makino (electrical engineering
and computational and applied math) and Justin Dong
(mechanical engineering and computational and applied
math). They were advised by Gary Woods, a professor in the
practice of computer technology and electrical and computer
engineering at Rice.
The teams approach is not directly
applicable to spacecraft, but the
concept is. We plan to include the
findings of the research in our next
opportunity for power systems
design, said Patrick George, a
project manager at NASAs Glenn
Research Center in Cleveland. He
said such a system applied to the ISS
(International Space Station) would provide more energy for
experiments and other operations and would increase the life
of key components.
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IDC reports smartphone shipments increased by 28.6%


in the first quarter of 2014, with year on year growth that
belies a mixed market. Although impressive, the increase is

less than Q4 2013s year on year increase with shipments


of 289.6million. The analyst company remains positive, as
China bucked the trend of global decline in shipments, and
there is more to come, as the region prepares for 4G.
$*3$6*5#0"3%.*.*$45)&#3"*/

With potential to drive prosthetic limbs or robotics, a circuit


board developed by bioengineers at Stanford University
can simulate one million neurons and billions of synaptic
connections.
Writing in the journal Proceedings of the IEEE, Kwabena
Boahen explains how the Neurogrid circuit board, mimics
the human brain.
He and his team developed the board, with 16 customdesigned Neurocore chips which can simulate neurons and
synaptic connections. It was designed to allow some synapses
to share hardware circuits for power efficiency. The iPadsized device simulates brain activity using the same power
budget as it takes to run a tablet computer.
*4*5"#*3% *4*5"1-"/&

A new meaning for a fly-drive holiday is on the cards if


MITs project for a flying car err, takes off.
CNBC reports on a team of graduates that have formed
Terrafugi and which is prototyping a plane that drives
which is the preferred description, rather than a flying car.
The 1600 horsepower TF-X is powered by a plug-in hybrid
Powertrain and is fitted with a parachute.

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DAC Issue 2014t

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lthough the IP industry is about 25 years old, it still presents


problems typical of immature industries. Yet, the use of IP
in systems design is now so popular one is hard press to find even
one system design that does not use IP. My first reaction to the
use of IP is back to the future.

ENTERS COMPLEXITY

As semiconductors fabrication progressed, the board became the


chip, and the components are now IP modules. One would think
that integration would also remain reasonably straight forward.
But this is not the case. Concerns about safeguarding intellectual
property rights took over and IP developers were reluctant to
provide much information about the functioning of the module,
afraid that its functionality would be duplicated and thus they
would loose sales.
As the number of transistors on a chip increases, the complexity
of porting a design from one process to the next also increases
(See Figure 1).
Developers found that by providing a hard macro, that is a module
already placed and routed and ready for fabrication by the chosen
foundry, was the best way to protect their intellectual rights. But
such strategy is costly because foundries cannot just validate
every macro for free. The IP provider must be in the position to
guarantee volume use by the foundrys customers. Thus many IP
modules must be synthesized. This means they must be verified.
Karthik Srinivasan Corporate Application Engineer Manager
Analog Mixed Signal at Apache Design Solutions, an Ansys
company, wrote that SoC designs today integrate significant
number of IPs to accelerate their design times and to reduce the
risks to their design closure. But the gap in the expectations of

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IP

For many years of my professional career I dealt with board level


design as well as chip design. Between 1970 and 1990 IP was sold
as discrete components by companies such as Texas Instruments,
National, and Fairchild among many others. Their databooks
described precisely how to integrate the part in a design.
Although a defined standard for the contents did not exist, a defacto standard was followed by all providers. Engineers, using the
databooks information would choose the correct part for their
needs and the integration was reasonably straight forward. All
signals could be analyzed in the lab since pins and traces were
available on the board.

DESIGN AND INTEGRATION

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Figure 1. Projected number of transistors on a chip

where and how the sign-off happens between the IP and SoC
designers create design issues that affect the final products
performance and release. IP designers often validate their IPs
in isolation with expectations of near ideal operating conditions.
SoCs are verified and signed off with mostly abstracted or in many
cases black-box views of IPs. But as more and more high speed
and noise sensitive IPs get placed next to each other or next to
the core digital logic failure conditions that were not considered
emerge. This worsens when these IPs share one or more power and
ground supply domains. For example, when a bank of high speed
DDR IPs are placed next to a bank of memories, the switching
of the DDR can generate sufficient noise on the shared ground
network that can adversely affect the operation of the memory.
As designs migrate to smaller technology nodes, especially those
using FinFET based technologies this gap in the design closure
process is going to worsen the power noise and reliability closure
process.
DDR memory blocks are becoming a greater and greater portion
of a chip as the portion of functionality implemented in firmware
increases. Bob Smith, Senior VP of Marketing and Business
Development at Uniquify makes the case for a system view of
memories.
DDR IP is used in a wide variety of ASIC and SoC devices
found in many different applications and market segments. If the
device has an embedded processor, then it is highly likely that
the processor requires access to external DDR memory. This
access requires a DDR subsystem (DDR controller, PHY and

DAC Issue 2014t

Whether it is procured from an external source or developed by


an internal IP group, almost all chip design projects rely on DDR
IP to implement the on-chip DDR subsystem. The integration
techniques used to implement the DDR IP in the chip design
can have far reaching effects on DDR performance, chip area,
power consumption and even reliability.

IP

DESIGN AND INTEGRATION

IO) to manage the data traffic flowing to and from the embedded
processor and external DDR memory.

chip decreases. Thus we are rapidly reaching the point where


only hardened hard modules will be viable. The number of
viable providers in the IP industry is shrinking rapidly and many
significant companies have been acquired in the last three or four
years by EDA companies that becoming major providers of IP
products.
Synopsys started selling IP around 1990 and has now a wide
variety of IP in its portfolio, mostly developed internally. Cadence,
on the other hand, has built its extensive inventory of IP products
mostly through acquisition.
Michael Munsey, Director of ENOVIA Semiconductor Strategy
at Dassault Systemes points out that there are a number of issues
to deal with regarding IP.
1. IP Sourcing: Companies are going to need a way to source
IP. They will need access to a cataloging system that allows for
searching of both internally developed or under development
IP as well as externally available third party IP.

Figure 2. A non-optimized DDR implementation

The above figure illustrates a typical on-chip DDR


implementation. Note that while the DDR I/Os span the
perimeter of the chip, the DDR PHYs are configured as blocks
and are placed in such a way that they are centered with the I/Os.
As shown in the diagram, this not only wastes valuable chip area,
but also creates other problems.
A much more efficient way to implement the DDR subsystem
IP is to deliver a DDR PHY that is exactly matched to the
DDR I/O layout. By matching the PHY exactly to the I/Os, a
tremendous amount of area is saved and power is reduced. Even
better, the performance of the DDR can be improved since the
PHY-I/O layout minimizes skew.
As process technology progresses and moves from 32 nm to
22nm and then 14 nm and so on, the role of the foundry in the
place and route of an entire chip increases. In direct proportion
the freedom of designers to determine the final topology of a

2. IP Governance: For internally developed IP, there needs to


be systems and methodologies for handling the promotion of
work in progress to company certified IP. For both internal
and externally acquired IP, there needs to be a process to
validate that IP, and then a system to rate the IP internally
based on previous use, documentation available, and other
design artifacts.
3. IP Issue Defect and Tracking: Since IP will be in use in
multiple projects, a formal system is required to handle issue
and defect tracking across multiple projects against all IP. If
one group finds and issue with a piece of IP, all other project
groups that are using that IP need to be alerted of any issues
found and the plan on resolving the issue. Ideally this should
be integrated into design tools that are used to assemble IP
as well. If a product has already gone out the door with the
defective IP, these issues need to managed and corrective
actions need to ensue based on any defects found.

Figure 3. Optimized DDR block

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$IJQ%FTJHOtXXXDIJQEFTJHONBHDPN

INTEGRATING THE PIECES

Farzad Zarrinfar, Managing Director of the Novelics Business


Unit at Mentor Graphics, provided a synthesis of the problems
facing designers.
For IP Integration, multiple IP like Hard IP, Synthesizable
Soft Peripheral IP, and Synthesizable Soft processor IP with
different set of deliverables, use EDA tools for efficient ASIC/
SOC designs. Selecting the optimal IP size (such as smallest
embedded memory IP) is a critical design decision. While free
IP is readily available, it does not always provide the best solution
when compared to fee-based IP that provides much better
characteristics for the specific applications.
IP integration to achieve smaller die size, lower leakage, lower
dynamic power, or faster speed can provide designers with a more
optimized solution that can potentially save millions of dollars
over the life of the product, and better differentiate their chips in
a highly competitive ASIC/SoC marketplace.
Bill Neifert, Chief Technology Officer at Carbon Design
Systems observes. Certainly, some designers at the bleeding
edge differentiate every aspect of the subsystem and their own
IP, but were increasingly seeing others adopt whole subsystem
designs and then making configuration tweaks. Think black box
design and ARMs big.LITTLE offerings are prime examples of
this trend.

$IJQ%FTJHOtXXXDIJQEFTJHONBHDPN

IP

5. Variant driven platform based design: Ultimately, for


companies to keep up with the shortening market windows
and application driven platform design, companies will
need to adopt a system where there are base platforms with
pre-qualified IP that can be configured on the fly and used
a s a starting point for new designs. These systems would
automatically populate a design workspace with the required
IP from a company approved catalog as the basis of a new
design moving forward.

Of course, in order to make these configuration changes,


designers need to know the exact impact of the changes that
theyre making. We see users doing this a lot on our IP Exchange
web portal. They will download a CPAK (Carbon Performance
Analysis Kit), a pre-built system or subsystem complete with
software at the bare metal or O/S level. This gets them up and
running quickly but not with their exact configuration. Theyll
then iterate various configuration options in order to meet their
exact design goals. Its not unusual for a design team to compile
20 different configurations for the same IP block on our portal
and then compare the impact of each of these different models
on system performance.

DESIGN AND INTEGRATION

4. IP Security: There are different levels of protection needed for


different types of IP and robust methods must be put in place
to ensure the security of IP. First, company critical IP must be
secure, and systems need to be put in place to make sure that
the IP does not leave the company premises. If collaborating
with partners, any acquired IP must also be handled so that
it is only used in the designs that are being collaboratively
designed. There need to be restrictions on using partner IP in
design blocks which in turn can become IP in other designs.
There needs to be a way to track the pedigree of IP.

Naturally, all of this impacts the firmware team quite a bit.


The software developers dont need to know exactly what the
underlying hardware is doing but the firmware team needs the
exact IP configuration. The sooner these decisions can be made,
the sooner they can start being productive. Integrating this level of
software on to the hardware typically exposes a new round of IP
optimizations that can be made as well. Therefore, its not unusual
for IP configuration changes to happen in waves as additional
pieces of IP and software are added to the system.
Drew Wingard, CTO at Sonics points out that standards matter.
Because there are many sources for IP, the industry had to
create and adhere to standards for integration. From a silicon
vendors perspective, IP sources include third-party commercial
components, internally designed blocks and cores, and customerdesigned components. To meet the challenge of integrating IP
components from many different places, SoC designers needed
communication protocol standards. Communication protocol
standards efforts began with the Virtual Socket Interface Alliance
(VSIA), continued with the Open Core Protocol International
Partnership (OCP-IP), and today reside with Accellera. Of
course, our customers need to leverage de-facto standards such as
ARMs AMBA as well. We owe our ability to integrate IP to the
fundamental communication protocol standards work that these
organizations performed.
THE CHALLENGE OF VERIFICATION

Sunrises Prithi Ramakrishnan is concerned about system


verification. At a very high level, the main issue with IP is that
the simulated environment is different from the final design
environment. Analog and RF IP is dependent on process/node,
foundry, layout, extraction, model fidelity, and placement. So you
are either tied to just dropping it in as is and treating it like a
black box (nobody knows how it works and whether it meets
the required specifications) or completely changing it (with the
caveat that you can no longer expect the same results). Digital
IP needs to be resynthesized followed by placement and routing,

DAC Issue 2014t

DESIGN AND INTEGRATION


IP

and it takes several iterations to make the IP you got work the
way you want it to work. In addition, this process is extremely
tool-dependent.
Finally, there are system level issues like interoperability, interface
and controls (how does the IP talk to the rest of the SoC). A
very important, often overlooked factor is the communication
between the IP providers and the SoC implementation houses
there are documents outlining integration guidelines, but without
an automated process that takes in all that information, a lot
could be lost in translation.
The issue of how well a third party IP has been verified will
always hunt designers unless the industry finds a way to make
IP as trustworthy as the TI 7400 and equivalent parts of the
early days. Bernard Murphy, CTO at Atrenta observed: One
area that doesnt get a lot of air-time is how a SoC verification
team goes about debugging a problem around an IP. You have the
old challenge is this our bug or the IP developers bug? If the
developer is down the hall, you can probably resolve the problem
quickly. If they are now working for your biggest competitor, good
luck with that. If this is a commercial IP, you work with an apps
guy to circle around possibilities: maybe you are using it wrong,
maybe you misunderstood the manual or the protocol, may be
they didnt test that particular configuration for that particular
use-case Then they bring in their expert and go back through
the cycle until you converge on an answer. Problem is, all this
burns a lot of time and youre on a schedule. Is there a way to
compress this debug cycle?
He offers the following suggestion. One important class of
things to check for is the above didnt test that configuration for
that use-case. This is where synthesized assertions come in. These
are derived automatically by the IP developer in the course of
verifying the IP. They dont look like traditional assertions (long,
complex sequences of dependencies). They tend to be simpler,
often non-obvious, and describe relationships not just at the
boundary of the IP but also internal to the IP. Most importantly,
they encode not just functionality but also the bounds of the usecases in which the IP was tested. Think of it as a signature for the
function plus the verification of that function.
Thomas L. Anderson, VP of Marketing at Breker Verification
Systems pleads: integrate, but verify. He argues that The truth
is that most SoC teams trust integration too much and verify too
little. Many SoC products hit the market only after two or three
iterations through the foundry. This costs a lot of money and risks
losing market windows to competitors. Most SoC teams follow a
five-step verification process:

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1. Ensure that each block, whether locally designed or licensed


as IP, is well verified
2. Use formal methods to verify that each block has been
integrated into the SoC properly
3. Assemble a minimal chip-level simulation testbench and
run a few sanity verification tests
4. Hand-write some simple C tests and run on the embedded
processors in simulation or emulation
5. Run the production software on the processors in simulation,
emulation, or prototyping
The problem with this process is that the tests in steps 3 and
4 are too simple since they are hand-written. They typically
verify only one block at a time, ignoring interaction between
blocks. They also perform only one operation at a time, so
they dont stress cache coherency or any inherent concurrency
within the design. Humans arent good at thinking and coding
in parallel. Thorough SoC pre-silicon verification can occur
only with multi-threaded, multi-processor test cases that string
blocks together into realistic scenarios representing end-user
applications of the chip.
AN EXAMPLE OF COMPLEXITY

Charlie Cheng, CEO of Kilopass gave me an example of


complexity in choosing the correct IP for a design by using
sparse matrix math.
With semiconductor IP comprising 90 percent of todays
semiconductor devices and memory IP accounting for over 50
percent of these complex SoCs, its no wonder that IP is the
fastest growing sector of the overall semiconductor industry.
As a result, managing third-party IP is a growing responsibility
within todays semiconductor companies. How to make
the right choice from a growing quantity of IP is the major
challenge facing engineering teams, purchasing departments,
and executive management. The process of these groups buying
IP can be viewed as a sparse matrix mathematical exercise but
without the actual math formulas and data manipulation.
1.8V
TSMC
UMC
SMIC
GLOBALFOUNDRIES

Vendor A OTP
28HP
28HP
28HP
28HP

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If the mathematical exercise was actually performed and all the


cells in the matrix had assigned values, then a definitive solution
is easily achieved. However, if the cells throughout the matrix are
sparsely populated, then the solution ends up with a probable
outcome.

IP

For example, Vendor As OTP at 1.8v has JEDEC three-lot


at 28HP at TSMC, UMC and GLOBALFOUNDRIES,
similarly for 28HPM and 28HP but has only working silicon
at 28LP. Vendor Bs OTP may not have received three lot
qualification at any of the vendors on any of the processes, but
may have first silicon or one or two lot qualification on one or
more of the vendors. In the mathematical exercise, a figure of
merit would be assigned to the being fully qualified, one or two
lot qualified, first silicon or not taped out. Using matrix algebra,
the formal mathematical exercise would return a result but an
intuitive evaluation of the process would suggest vendor A with
more three-lot qualifications at multiple foundries would have
an edge over vendor B which did not.

The above exercise would be typical of the evaluation occurring


in the engineering team. A similar exercise would be occurring
in the purchasing department with terms and conditions
presented in the licensing agreement and royalty schedule each
vendor submits. Corporate and legal would perform a similar
exercise.

DESIGN AND INTEGRATION

The table shows two dimensions of a multi-dimensional matrix


representing the variables confronting the purchasing company
teams. In this two-dimensional matrix, imagine three additional
tables for 1.8v operations with the four foundries at 28HPL,
28HPM, and 28HP. Now, replicate this in a fourth dimension for
the variable of 2.5v. Add a fifth and sixth dimension to the matrix
for Vendor Bs OTP. If this were a mathematical evaluation, a
figure of merit would be assigned to each cell in each plane of the
multidimensional matrix.

Gabe Moretti has been in EDA for 45 years. First


as an individual contributor with TRW Systems
and Compucorp. Then as a manager with Intel and
Signetics. He has been a member of the executive
management team with EIS Modeling (a company
he founded), HDL Systems, and Intergraph/
Veribest. From 2000 to 2005 he was technical editor for EDA at EDN.
Since then Gabe has run his own consulting company, GABEonEDA.
He has a B.A. in Business Administration and a Master in Computer
Sciences.

Far more than just Standards....


Silicon Integration Initiative
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VWDQGDUGVIRUVHPLFRQGXFWRUGHVLJQRZV
%RDUGRI'LUHFWRUVAMD, ARM, Cadence,
Globalfoundries, IBM, Intel, Mentor Graphics,
Qualcomm, Samsung, STMicroelectronics,
Synposys

......Its about Adoption and ROI


Featured Downloads
At: www.si2.org/?page=1038

$IJQ%FTJHOtXXXDIJQEFTJHONBHDPN

www.si2.org
DAC Issue 2014t

CLOCK DOMAIN CROSSINGS


IP ISSUES

ADVERTORIAL

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BOBMZTJT

s design complexity escalates, designers increasingly rely


on commercial or existing IPs to meet project deadlines
rather than designing everything from scratch. According to
Semico Research, over the next couple of years, the number
of IPs per design will increase from an average of 50 to a
staggering 180.

design as erroneous states causing functional failures. Hence


it is important for designers to find portions of their designs
where CDC can occur. Designers then insert logic to greatly
reduce the likelihood of propagating erroneous data due to
metastable signals.
FAILURE OF THE BLACK BOX METHODOLOGY

The difficulty of IP integration and design verification will


undoubtedly grow exponentially. Even today, many design
teams complain that it takes too long for integration and
verification using existing methodologies. Just imagine the
resulting dreadful situations as the number of IP per design
goes up. To alleviate these types of issues, EDA vendors need
to provide breakthrough methodologies. Previously, Blue Pearl
Software introduced the Grey Cell methodology, which was
discussed at DAC 2012 and elaborated within EETimes.
With the recently introduced User Grey Cell methodology,
Blue Pearl enables IP providers and FPGA designers to reduce
the risk of missing CDC issues. We illustrate how this reduces
metastability.
LEADING CAUSE OF METASTABILITY

Designs today integrate components/IPs from many sources


that operate with independent clocks with different frequency
and phase relationship. This is done to bring data into the
design from different sources or to change frequency in order to
optimize power. The added complexity of disabling many logic
cones means verification engineers need to be more vigilant.
Whenever there are setup or hold time violations in any flipflop, it can enter a state where its output is unpredictable. This
state is known as metastable state. It could well be that the flipflop will settle in a known state, but due to dependencies on
thermal and induced noise, one cannot be certain on the time
it takes to settle. The likelihood of a functional failure due to
metastability increases with clock frequency.
When components or IPs with different clock phase/frequency
interface, the receiving logic flip-flop may violate setup or
hold time causing the output to not settle to a stable 1 or 0
state. This metastable state can get propagated through the
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As discussed earlier, the required components/IPs can come


from varied sources. They could be acquired in synthesizable
RTL format, protected IP format, simulation models, or nonsynthesizable formats. If the IP is in the form of a synthesizable
RTL, then it is relatively straightforward to perform CDC
analysis through it. However, for the other formats, the IPs have
traditionally been treated as black boxes i.e. the analysis will not
use any knowledge of the internals of the IP. In a black box
methodology, the CDC analysis will stop at each IP boundary
and treat it as an end point with no relationship whatsoever
with whats inside the IP.
As designers rely more and more on IPs, the number of black
boxes included in the analysis is increasing. Thus, the risk of
missing critical CDC issues grows. Moreover, since the IPs
are instantiated in hierarchical designs, it quickly becomes
impossible to manually trace and decide whether a particular
black box can cause a CDC issue.
WONT IEEE P1735 SOLVE THE BLACK BOX ISSUE?

The IEEE project P1735 intends to describe IP encryption


markup for design information formats, and thus enable design
flows that provide interoperability between IP sources, tools,
integrators and users of the IP. This is driven primarily by
IP providers who want to protect their know-how and thus
encrypt their IP. P1735 provide guidelines for key management,
together with encryption and decryption algorithms. This
enables inter-operable IP encryption and thus allows specific
EDA tools to see the inside of the IP.
Once P1735 is finalized, it will solve the CDC analysis for a
synthesizable RTL IP assuming that once decrypted, the tool
has enough information to perform the analysis through the
IP. However, this does not completely address all the reasons
why designers settle for a Black Box methodology. Designers
$IJQ%FTJHOtXXXDIJQEFTJHONBHDPN

still need to handle the non-synthesizable models, simulation


models, behavioral models and/or still incomplete models. For
these components, encryption/decryption still does not help in
enabling a complete CDC analysis. Thus, P1735 still does not
solve all the issues of using a Black Box methodology.

WHAT IS A USER GREY CELL?

A User Grey Cell, as depicted in Figure 1 below, contains more


information than a black box. The User Grey Cell reduces
the amount of information in the complete proprietary RTL
design to what is sufficient for CDC analysis.
The User Grey Cell provides clocking and register information
that allows for an accurate CDC analysis. When creating a
User Grey Cell, the user needs to specify only those ports that
are relevant to the current design, rather than specifying all
the ports.

IP ISSUES

Even though the IPs can be encrypted and decrypted with


proper key management, some IP developers are still not
convinced that the IP will not end up in the wrong hands.
Consequently, Blue Pearl Software developed the User Grey
Cell methodology that works on all types of IP without the
need to ever ship the proprietary information. In fact, designers
can perform CDC analysis through the FPGA vendor
protected/generated IPs.

However, if an FPGA vendor generated IP, such as CoreGen


or MegaFunction, is included in the design this is typically
treated as a black box. Any information regarding the IP ports
with clock interactions is lost, and therefore the CDC analysis
is not as thorough as it could be. This is solved via our User
Grey Cell Methodology.

CLOCK DOMAIN CROSSINGS

ADVERTORIAL

A User Grey Cell is specified in xml format. A default set is


supplied in the Blue Pearl Software distribution package, and a
designer can create new User Grey Cells that will be recognized
by the software. Some key elements of the xml content include:
Figure 1: User Grey Cell representation

BASIC CDC ANALYSIS

Before we get into the details of User Grey Cell, let us do a


quick refresher on basic CDC analysis.
A clock domain crossing occurs whenever data is transferred
from a flip-flop driven by one clock to a flip-flop driven by
another clock. Traditional simulation and/or static timing
analysis methods are not sufficient to verify that the data is
transferred consistently and dependably across clock domains.
Thus, CDC analysis tools emerged to assist designers in
checking for these potential issues. Lets point out that some
FPGA designers tend to wait to debug in the lab. However,
it is better to use verification tools on the RTL rather than
waiting for the lab.
A basic CDC analysis tool should check and report on some
simple issues, e.g. existence of unsynchronized and synchronized
schemes, report even if one bit of a bus can cause CDC, check if
data is being clocked using both rising and falling edges, check
if a fast clock transfers data to a slow clock (potential data loss),
and check if level sensitive latch data is combined with edge
triggered data.

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and architecture. Specify the name of the module and
some of its properties, such as whether you are creating a
synchronization cell.
R555 (*/.5(5/.*/.5*#(-95*#.#)(5) 55,!/&,5#(*/.5),5
output pin requires either notation of a clock pin, in which
case a DFF is inferred, or that the pin is asynchronous. You
also have the option of specifying a reset pin along with a
clock.
R555&)%5*#(-95(5#( ,,55 ),5(5#(*/.5),5)/.*/.5'/-.55
matched with a specified clock input pin. A clock output
pin represents a new clock domain.
R555-.5*#(-95(5#( ,,55 ),5(5#(*/.5),5)/.*/.5(55
matched with a specified reset pin, as noted above.
R55552'&5-3(.25#-5&-)52#&5()/!"5.)5&&)15 ),5+/.#)(5
definition and parameterization of the pins.
Read the complete article on Chip Design: http://eecatalog.com/
chipdesign/2014/05/21/metastability-challenges-ip-and-fpgaclock-domain-crossing-analysis

DAC Issue 2014t

The Global Semiconductor Alliance (GSA) mission is to accelerate the growth


and increase the return on invested capital of the global semiconductor industry
by fostering a more effective ecosystem through collaboration, integration and
innovation. It addresses the challenges within the supply chain including IP,
EDA/design, wafer manufacturing, test and packaging to enable industry-wide
solutions. Providing a platform for meaningful global collaboration, the Alliance
identifies and articulates market opportunities, encourages and supports
entrepreneurship, and provides members with comprehensive and unique
market intelligence. Members include companies throughout the supply chain
representing 25 countries across the globe.

GSA Member Benefits Include:

Access to Profile Directories


Ecosystem Portals
IP ROI Calculator
IP Ecosystem Tool Suite
Global Semiconductor Funding, IPO and
M&A Update

Global Semiconductor Financial Tracker


End Markets Tool
MS/RF PDK Checklist
AMS/RF Process Checklist
MS/RF SPICE Model Checklist
Collaborative Innovation Study with the

Discounts on various reports and


publications including:

Wafer Fabrication & Back-End Pricing Reports


Understanding Fabless IC Technology Book
IC Foundry Almanac, 2011 Edition
Global Exposure Opportunities:

Advertising
Sponsorships
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Wharton School

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#Z+PIO#MZMFS $IJFG$POUFOU0GmDFS

FOCUS REPORT ON IOT

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earable devices will add a new twist to traditional embedded


designs according to experts from ARM, Freescale, HillCrest
Labs, STMicr, Imec and Koinix.

be replacing QFN and LGA for many applications. This requires


close cooperation across all disciplines as the traditional package
disappears.

Wearable technology design presents challenges different from other


embedded markets. To understand these challenges, System Design
Engineering talked with James Bruce, Director Mobile Solutions for
ARM; Mike Stanley, Systems Engineer at Freescale; Daniel Chaitow,
Marketing Communications Manager at Hillcrest Labs; Jay Esfandyari,
Director of Global Product Marketing at STMicroelectronics; Siebren
Schaafsma, Team Leader at Holst Centre and Imec, and; Thea Rejman,
Financial Analyst at Kionix, Inc. What follows is a portion of that
conversation. JB

Low power, wireless communications and small form factor are keys
to driving IoT applications. In many ways, these are closely related
to some wearable applications in that they use similar sensors and
common software libraries for communication, data abstraction and
signature recognition.

System Design Engineering: What unique technical challenges


are designers facing in the wearable smart connected market as
opposed to other markets?
Bruce: The big challenge for wearable designers is that the use
cases are still very new. There is a lot of innovation and diversity
taking place. People are trying out many different operational
scenarios. Designers need low power processors that are right
for these evolving workloads. One of the benefits is that there is
a strong ecosystem with a large number of system-on-chip (SoC)
available to developers to create initial wearable solutions. Once they
have taken the initial designs to market, they can stay with it, use a
different SOC, or even customize it.
Another key consideration for designers is improving quality of
sensor data integrated into the device, which have traditionally
been not in the domain of digital designers. Traditional digital
designers need to worry about the analog portions of a wearable
device, i.e., accelerometers, gyros, humidity sensors, etc as there are
several choices of sensor fusion solutions for low power application
processors available off-the-shelf.
Stanley: Managing power consumption and communications are
currently the two largest hurdles for wearable hardware. Looking
ahead to truly wearable sensors that can be embedded into clothing,
athletic equipments, name badges, etc., means that every component
in the system must become even smaller and thinner. This drives the
trend of consolidating multiple sensors into one package, and then
shrinking that combo sensor even more. Chip scale packaging will

$IJQ%FTJHOtXXXDIJQEFTJHONBHDPN

Chaitow: The challenges of timing, power, availability, and security


are similar to but different from the typical embedded design
problem. Perhaps the main difference is that, instead of a single
circuit board or chip to worry about, the designer must consider
the whole system. This adds network and systems engineering
problems to the job of a typical embedded design engineer. Its
one thing to optimize the power and security of a single device; its
totally different to do that across a various set of devices in a variable
network. Then add in the fact that the number of devices or versions
of the devices might change in a given network over time and the
design problem gets even bigger.
An additional unique challenge is the need for calibration of
sensors. MEMS sensors used in commercial products have variable
performance. This variable performance is true both at the point of
manufacture and over the lifetime of the product, as each sensor
reacts differently to changes in environmental factors such as
temperature, voltage, interference, and sensor aging, to name just
a few. These variations make calibration essential for sensor-based
products.
Esfandyari: Wearable-device requirements are currently driving
significant changes in the MEMS industry. They are driving
the development of even smaller components with even lower
power consumption but with more embedded features. To satisfy
these needs, sensor manufacturers are creating highly integrated
devices with multiple sensors (e.g., accelerometer, gyroscope and
magnetometer) embedded in a single package.
Finally, from a design perspective, wearable-device manufacturers
must be very careful with the appearance of their product because
many people are conscious of their appearance and would prefer
not to wear accessories that make them look strange. The challenge

DAC Issue 2014t

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FOCUS REPORT ON IOT


is to make wearable technology invisible to the final user and the
external world.
Siebren: An important part of wearable technology will be in the
design of body area networks (BANs) a collection of miniature
sensor and actuator nodes. Such devices will require innovative
solutions to remove the critical technological obstacles such as
shrinking form factors that require new integration and packaging
technology. Battery capacities will need to be extended. Indeed, the
energy consumption of all building blocks will need to be drastically
reduced to allow energy autonomy. System design will have to focus
on overall system power consumption where trade-offs have to be
made between security, privacy, precision, availability and storage of
the data. For example a high power streaming mode over radio of
high resolution, medical grade ECG data in case of an emergency
compared to average heart rate monitoring once a minute in the low
power mode.

TRADITIONAL DIGITAL DESIGNERS NEED TO


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Rejman: Stringent power requirements drive the majority of
sensor applications in the wearables market. Therefore, it is essential
that both the sensors and the software are low power. Designers
should look for a sensor fusion solution that offers embedded power
management functionality to help manage sensor interaction and
data processing with minimal overhead, resulting in lower power
and better performance.
System Design Engineering: Thank you.
John Blyler covers todays latest high-tech, R&D and
even science fiction in blogs, magazine articles, books
and videos. He is an experienced physicist, engineer,
journalist, author and professor who continues to speak
at major conferences and before the camera. John is the
Chief Content Officer for Extensionmedia, which includes the brands Chip Design, Solid State Technology, Embedded Intel and
others. He holds a BS in Engineering Physics and a MSEE. John plays the
piano and holds a black belt in TKD.

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Several recent interviews with technical experts about trends in


wearable technology made me wonder how sci-fi writers might
envision the future.
Just for fun, I asked the Sci-Fi community for their thoughts
on the future of wearable technology. The responses ranged
from the far-out to the retro and from the quirky to the deeply
insightful. The only problem was that I couldnt resist adding
to their comments. Perhaps youll find it equally difficult to
withhold your own opinions? JB
Walter Knight, Americas Galactic Foreign Legion series:
The most obvious wearable technology Ive explored in my
Americas Galactic Foreign Legion science fiction series is the
helmet camera, a reality now. Soldiers, police officers, security
guards, etc wear the cameras at work. Soon, everyone will be
wearing these cameras on errands and vacations. Weve already
seen many news reports showing biker helmet cameras and
dash camera.
Privacy concerns are now focused on those the cameras encounter
and government intrusion. But Im more concerned with the
privacy of the wearer of the camera. What if an employer insists
all employees wear the cameras? Will your union go along
with that? What about bathroom breaks? Cheating at work?
Picking your nose and flatulence? Political correctness? It all
gets recorded. Fortunately, there is a low-tech solution if this
scenario becomes reality. Duct tape over the camera lens. Ha!
Another use for duct tape!
Response from JB: Dont forget your sentient ATM! Thats
sort-of wearable from the perspective of the robot.
Jonathan Howard, Author of the Johannes Cabal, Russalka
Chronicles, & Goon Squad series: I cant honestly say its
(wearable technology) anything Ive ever given much thought to,
although whoever invents heat-sensitive cloth that moderates
its insulating qualities depending on the temperature of the
wearer will do very well.
Read the complete story at: http://www.chipdesignmag.com/
blyler/2014/04/28/insights-from-the-sci-fi-community-onwearables/

DAC Issue 2014t

DEEPER DIVE
#Z$BSPMJOF)BZFT 4FOJPS&EJUPS4ZTUFNT

%FFQFS%JWF5)[4J(F
TeraHz (THz) technology holds a great deal of promise for imaging and
sensing, wireless Gbit/s communications and millimeter-wave radar.
There have been several breakthroughs already this year that have added
to the anticipation, writes Caroline Hayes, Senior Editor.

erman company, IHP Microelectronics, and the Georgia


Institute of Technology have demonstrated the worlds
fastest silicon-based device, a SiGe (silicon-germanium) transistor
operating at 798GHz fMAX, surpassing the previous record by
around 200GHz.
IHP (Innovation for High Performance) Microelectronics is a
research center funded by the German government. It designed
and fabricated the HBT (Heterojunction Bipolar Transistor) made
from a nanoscale SiGe alloy embedded within a silicon transistor.
Professor John Cressler, Georgia Tech School of Electrical
and Computer Engineering and his team analyzed, tested and
evaluated the transistors, recording the record speeds in February,
at extremely cold temperatures.
Operation at room temperature will open up possibilities,
announced Cressler at the time, for what he described as potentially
world-changing progress in high-data-rate wireless and wired
communications, as well as signal-processing, imaging, sensing and
radar applications. He also believed that THz speeds in a robust
and manufacturable silicon-germanium transistor is within reach.
In the project, the team demonstrated IHPs 130nm BiCMOS
process 800GHz transistor at 4.3 Kelvins (452 F below zero) with
a breakdown voltage of 1.7V deemed adequate for most intended
applications. Liquid helium was used to achieve the low cryogenic
temperatures.
I asked IHP Microelectronics Bernd Heinemann about breaking
the THz barrier and how realistic it is to apply it to silicon devices.
III-V transistors have already surpassed the THz barrier at room
temperature, he confirmed. If device simulations are reliable
enough and best manufacturing capabilities are applied, then is a
realistic chance also for Si devices too.
Currently, the European research project DOTSEVEN is
targeting the realization of SiGe HBTs with maximum oscillation
frequencies fmax of 0.7THz.

t%"$*TTVF

What everyone wants to know is how was it done? Did 0.13m


BiCMOS process play in achieving the increased speed, I asked.
Not too much, replied Heinemann. This performance level
could be demonstrated also in 0.25m BiCMOS. The shrunken
design rules of the 0.13m CMOS helped for some points, he
conceded, to reduce parasitics, such as the resistance of the base of
the transistor.
Operating at room temperature, Heinemann says that the possible
applications are imaging, radar, high-data-rate communication
systems, and spectroscopy in science or medicine.
Imaging systems operating at frequencies up to 0.8THz have
already been demonstrated with currently available high-speed
SiGe HBT technologies, he confirms. A recent example is
the realization of a powerful radiation source at 0.5THz by the
group of U. Pfeiffer of University of Wuppertal presented at the
IEEE ISSCC conference this year. These chips were fabricated
in the 0.13m BiCMOS process with fmax of about 450GHz
at room temperature. The fmax values of 800GHz at cryogenic
temperatures were measured for HBTs of the same technology
generation.
Combining silicon-germanium with the cost, yield, size,
integration and manufacturing advantages of silicon makes the
device competitive in the marketplace.
Trans-Atlantic collaboration however, belies the race that is on
THz technology, as both North America and Europe are keenly
pursing the technology and looking to exploit it for cost-efficient,
manufacturable, high performance devices.
Caroline Hayes has been a journalist, covering the
electronics sector for over 20 years. She has worked
on many titles, most recently the pan-European
magazine, EPN. Now a freelance journalist, she
contributes news, features, interviews and profiles for electronics journals in Europe and the US.
In a previous role, as editor of EPD, she created the e-Legacy Awards
and also managed and chaired EPNs 40 th Anniversary Forum at
electronica 2012.

$IJQ%FTJHOtXXXDIJQEFTJHONBHDPN

DEEPER DIVE
#Z$BSPMJOF)BZFT 4FOJPS&EJUPS4ZTUFNT

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he gang of three, or the Grand Alliance, refers to the cooperation of foundry, IP and EDA companies to make
14nm FinFET a reality. Caroline Hayes, Senior Editor, asked
Steve Carlson, Director, office of Chief Strategy Officer, Cadence
Design, what was required to bring about FinFET harmony.

partners in a process of early collaborative co-optimization. This


co-optimization process gets the new process to production
readiness sooner, with known characteristics for key industry
favored IP and ensure that the tool flows will deliver on the
performance, power, and area promise of the new node.

What foundry support is needed for any chip maker looking to


develop 14/16nm finFET?

EDA (Cadence) has made some critical contributions in the rollout of enablement for FinFET:

SC: The foundry needs to supply a complete


enablement kit. This includes traditional PDKs
(physical design kits), along with the libraries,
technology/rule files for the synthesis, designfor-test, extraction, place and route, EM, IR,
Self-heat, ESD, power and timing sign-off,
DFM and physical rule checking.

We have solved technology challenges such as sign-off accuracy


demanded by 14/16nm to within 2 to 3% of Spice on all sign-off
tools (Tempus, Voltus, QRC, etc.) We have also brought about
low Vdd, which 14/16nm allows, with its challenges in terms of
optimization and sign-off.
Other challenges, met and solved are to improve routability for
small standard cell size (7.5 tracks).

Put another way, enablement


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meeting today. One is Hold. This is
level support, up through complex
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critical, especially with low Vdd and
SoC design. To get to the
IP AND EDA PARTNERS IN A PROCESS OF
it is supported at different stages in
production phase of enablement
the design and sign-off flow.
roll-out there have been several
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tape-outs and test chips of complex
There is also signal EM optimization
SoCs specifically architected to
and technology challenges to meet 14/16 nm requirements in
mimic the needs of the early adopters.
terms of placement rules and also routing rules
What IP technology is needed?
Assuming that 14/16nm finFET will be used to exploit its
dielectric isolation, where do you envisage it will be used?
SC: There are many IPs that would be useful in accelerating the
development of a new 14/16nm SoC. First and foremost, getting
SC: SOI will continue to fill niche applications and is very
the cell libraries (at least for use as a starting point) is critical.
unlikely to unseat bulk CMOS. FinFET on SOI may have
Along with that, many complex high speed interface IPs, such as
some advantage over FinFet on bulk for both leakage power and
SERDES are very useful.
radiation hardness. So military and possibly certain applications
(for safety concerns, maybe automotive) may choose FinFET on
If called for architecturally, processor IP, and standard interface IP
SOI.
make a lot of sense to buy, versus make.
What is needed to develop an efficient ecosystem for 14/16nm
finFET?
SC: TSMCs chairman [Morris Chang] has talked about the
grand alliance with the inclusion of the foundry, IP and EDA

$IJQ%FTJHOtXXXDIJQEFTJHONBHDPN

Caroline Hayes has been a journalist, covering the electronics


sector for over 20 years. Now a freelance journalist, she
contributes news, features, interviews and profiles for electronics
journals in Europe and the US.

DAC Issue 2014t

WAFER-LEVEL PACKAGING
RF-WIRELESS

#Z&E,PSD[ZOTLJ 4FOJPS5FDIOJDBM&EJUPS 4PMJE4UBUF5FDIOPMPHZ

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he most functionality at the least cost is the promise of


wafer-level packaging (WLP) when dealing with complex
integrated circuits (IC) with a high number of input/output
connections to the outside world. Integration of heterogeneous
circuit functionssuch as micro- and graphics-processing, fieldprogrammable gate array (FPGA) logic, dynamic and static
memory, radio-frequency (RF) and analog, and sensing and
actuatingmay also be needed at the package-level to be able to
deliver complete systems (Figure 1).

parts can often justify the additional design and test expenses
of delivering the same functionality as a single SOC.
The other major reason to go with an SIP is to improve the yield
of large area chips at the leading edge of fab processing. Since
defects/area tend to be relatively high with a new fab process,
very large chip designs will have relatively low yield at first but
then will improve as the fab learns how to reduce both random
and systematic yield limiters. The recent excellent example of
this trend is the Xilinx Vertex-7 FPGA which splits the chip
into four sub-chips and then uses a silicon interposer for SIP
re-integration. We may expect that a next-generation of the
product would be build in a single SOC after the yield improves,
at which point Xilinx would be expected to extend the product
line with additional functionality added in using multi-chip SIP.
FAN-OUT WLP

FIGURE 1: Heterogeneous System-in-Package (SiP) as an extension of proven


flip-chip (FC) packaging technology. (Source: Amkor)

In particular, electronic systems for high-growth mobile


applications require low-power and low-volume per element
which dis-allows circuit integration at the printed-circuit board
(PCB) level. Instead, heterogeneous integration must occur as
either a system-in-package (SIP) or a system on-chip (SOC).
Dr. Eric Mounier of Yole Dveloppement, presented at the
recent European 3D TSV Summit 2014 held in Grenoble, and
showed Yole forecasts that total world-wide semiconductor IC
wafers packaged at the wafer-scale will be 19% this year, raising
to 20% in 2015.
One way of looking at the history of the IC industry is to
examine the dynamic between SIP and SOC approaches.
New functionalities tend to be first integrated into hardware
as dedicated additional chips, to be connected in to the
rest of the system as part of a PCB or SIP. Since different
functionalities often require different fab processes, it
is generally less expensive at the chip-level to divide
functionalities into different chips, but then the packaging
costs tend to be higher. Relatively low-volume parts may be
most economically delivered as SIP, while higher-volume

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Steffen Kroehnert, director of technology for Nanium S.A., gave


a recent presentation at SEMICON/Singapore 2014 entitled
Wafer Level Fan-Out as Fine-Pitch Interposer. Fan-In WLP
uses layout package connections within the chip area, and when
the scale and count of on-chip bond pads does not match with
standard packaging scales, a Re-Distribution Layer (RDL) of
metal interconnect can be used to Fan-In to ball-grid or pillargrid arrays (BGA/PGA) within the chip-area. However, when
the needed number of connections cannot be made within
the chip area, packaging filler materials can be used to provide
physical area adjacent to an original chip such that package
connections can be arranged to Fan-Out WLP solutions use
Fan-Out out from the chip center when seen from above.
Chip-Package-Board simultaneous co-design and codevelopment are becoming import instead of serial work
according to Kroehnert. The penalty for re-design costs and
losing strategic time-to-market for a new SiP is too high for
allow for iterative R&D, such that products must be co-designed
properly the first time.
FO-WLP LEVERAGING PV FAB TRICKS

Deca Technologies, the electronic interconnect solutions


provider to the semiconductor industry owned by Cypress
Semiconductor, recently announced that it has shipped its
100-millionth component.The company attributes this milestone

$IJQ%FTJHOtXXXDIJQEFTJHONBHDPN

As thoroughly covered in our sister blog Insights From The


Leading Edge, STATSChipPAC (SCP) recently announced
FlexLine FO-WLP. The FlexLine flow dices and reconstitutes
incoming wafers of various sizes to a standard size, which results
in wafer level packaging equipment becoming independent of
incoming silicon wafer size. The SCP FlexLine process flow
is based on the SCP commercial eWLB FO-WLP process
(Figure 3). Single and multi die fan-out package solutions have
been in high-volume manufacturing since 2009 with more than
a half-billion units shipped.

RF-WIRELESS

Leveraging volume production technologies from leading


silicon PV manufacturer SunPower Corp., Deca quickly
achieved this milestone by addressing cycle time and capital
cost challenges that semiconductor device manufacturers have
struggled with using conventional approaches to WLCSP
manufacturing. Deca claims that other FO-WLP technologies
suffer from inherent manufacturing and reliability issues due
to discontinuity at the silicon:mold-compound interface, which
are avoided by the companys use of copper-pillars and an overmold approach (Figure 2).

FO-WLP FOR THE FUTURE

WAFER-LEVEL PACKAGING

to strong demand from portable electronics manufacturers for


wafer-level chip scale packages (WLCSP) manufactured using
Decas unique, integrated Autoline production platform, which
is designed to achieve faster time-to-market at lower cost.

FIGURE 3: Schematic cross-sections of various Fan-Out WLP packages.


(Source: STATSChipPAC)

FIGURE 2: Cross-section of edge of FO-WLP using Cu-pillars and over-mold


approach. (Source: Deca Technologies)

Demand for WLCSP is being driven by manufacturers


of wireless connectivity, audio, and power management
components for mobile markets. Demand fluctuations in
these markets can lead to challenges in managing inventories.
Congratulations to the Deca team on achieving this significant
milestone, said Brent Wilson, senior vice president of the
Global Supply Chain Organization at ON Semiconductor.
Decas innovative technologies and focus on customer service
have made the company a valuable part of our supply chain.
Reaching 100 million units is an important milestone for
Deca because it validates our unique approach to WLCSP
manufacturing, said Chris Seams, CEO of Deca Technologies.
Based on the demand forecasted by our customers, we
anticipate passing the half-billion mark in unit shipments this
year.

$IJQ%FTJHOtXXXDIJQEFTJHONBHDPN

Earlier this month, Digitimes provided a brief English


translation of some Chinese-language Economic Daily News
(EDN) saying that Taiwan Semiconductor Manufacturing
Company (TSMC) plans to increase IC packaging revenues
to US$1 billion in 2015 and to US$2 billion in 2016. TSMC
co-CEO CC Wei reportedly acknowledged that the production
cost for silicon-substrate SIP (TSMCs variant termed chipon-wafer-on-substrate or CoWoS) packages is relatively high,
and so the worlds leading IC foundry intends to invest in FOWLP technologies to be able to offer advanced packaging at a
reduced price.
Wafer-level packaging continues to gain slow IC market
share, and novel fan-out redistribution drives the need for
improvements in existing packaging materials within tight cost
and reliability constraints. With silicon-interposers and copperinterconnects part of WLP technology, the lines between chip
and package have never been less clear. Managing all of this
complexity is business as usual when designing mobile systems
of the future.
Ed Korczynski is the Senior Technical Editor for
Solid State Technology.

DAC Issue 2014t

DOT.ORG
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8IBUTOFXJOUIFMBUFTU*534
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he newly revamped International Technology


Roadmap for Semiconductors was released in early
April. Its actually called the 2013 ITRS, which makes it
seem already out of date, but thats the way the numbering
has always been.

completely new devices operating on completely new


principles and amenable to support completely new
architectures. For instance, spin wave device (SWD) is a
type of magnetic logic device exploiting collective spin
oscillation (spin waves) for information transmission
and processing. No surprise, the
manufacturing of integrated
THE 2013 ITRS REPORTS ON
circuits, driven by dimensional
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scaling, will reach the few
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nanometers range well within
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the 15-year horizon of the 2013
ITRS.
/&8"3$)*5&$563&4

Its a big undertaking, with input


from the U.S., Europe, Japan,
Korea and Taiwan. Through
the cooperative efforts of the
global chip manufacturers and
equipment suppliers, research
communities and consortia,
the ITRS identifies critical
gaps, technical needs, and potential solutions related
to semiconductor technology. Some key findings and
predictions of the 2013 ITRS include the following:

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power devices will usher in a new era of scaling identified
in short as 3D Power Scaling. The increase in the number
of transistors per unit area will eventually be accomplished
by stacking multiple layers of transistors.
R5,)!,--5#(5'(#*/&.#)(5) 5!&--51,**5'.,#&-5
(e.g., carbon nanotubes, graphene combinations, etc.)
offer the promise of ballistic conductors (as shown on this
months cover), which may emerge in the next decade.

An addition to the 2013 ITRS


edition is a new sub-chapter on big data (BD). The fab is
continually becoming more data driven and requirements
for data volumes, communication speeds, quality, merging,
and usability need to be understood and quantified.
Pete Singer has been involved in technical
journalism for more than 30 years and has
written well over 150 articles on all aspects
of semiconductor manufacturing and related
industries, Pete holds a degree in Electrical
Engineering from the University of Illinois and
is a member of IEEE, Electrochemical Society, American Vacuum
Society and Materials Research Society

R5 ,5 1#&&5 5 .1)5 #.#)(&5 13-5 ) 5 *,)0##(!5 ()0&5


opportunities for future semiconductor products. The
first consists of extending the functionality of the
CMOS platform via heterogeneous integration of new
technologies, and the second consists of stimulating
invention of devices that support new informationprocessing paradigms.
The ITRS also covers system level integration, including
the integration of multiple technologies in a limited space
(e.g., GPS, phone, tablet, mobile phones, etc.).
Looking at Long Term Devices and Systems (7-15
years horizon, beyond 2020) the 2013 ITRS reports on

t%"$*TTVF

$IJQ%FTJHOtXXXDIJQEFTJHONBHDPN

Agnisys, Inc.

IDesignSpec is an award winning Electronic Design


Automation tool that allows an IP, SoC, or System
Designer to create the register map specication once
and automatically generate all possible views and code
from it for Design, Design Verication, Software and
Documentation. An extensive list of outputs is possible
including UVM, OVM, RALF, SystemRDL, IP-XACT and
more. Other user-dened outputs can be created using
Tcl or XSLT scripts adding to the solutions extensibility.
IDesignSpec is patented technology that improves engineers productivity and design quality while enabling
the many SOC or FPGA project specication changes to
be quickly and accurately migrate to each project team
stakeholders code and documentation.

Create synthesizable code for registers for the design

ensuring correct by construction implementation of


the SoC or FPGA
Accelerate Device Driver, Firmware and Application
Software by automating header le generation MISRA-C compatible
Ensure documentation for customers and Tech-Pubs
is accurate and kept synchronized with SoC design
and verication
Built-in support all major (parallel) register busses:
AMBA AHB, APB, AXI, OCP-IP, Avalon, with simple
custom register support

CONTACT INFORMATION

FEATURES & BENEFITS

Agnisys, Inc.
1255 Middlesex St. Unit I
Lowell, MA - 01851
Tel: 1855-VERIFYY
Fax: 1-978-349-6949
www.agnisys.com

Automatically verify all addressable registers in the

design to eliminate errors before they can impact


project schedules

Verication

Verication

IDesignSpec

CONTACT INFORMATION

XXXDIJQEFTJHONBHDPN

.FUIPET&%"5PPMTt

Source III, Inc.

With nearly 25 years of eld-proven success, VTRAN


offers the most cost-effective, full-feature solution to creating EDA and ATE test programs from simulation and ATPG
vectors. Whether you need to translate VCD or EVCD simulation dump les into a test program for one of the popular
device testers, or you are taking ATPG-generated vectors
in WGL or STIL format to a tester, VTRAN provides the
most reliable and lowest-cost option available today. If you
are using an in-house tool for this, VTRAN can save your
valuable in-house resources, time and money while at the
same time bringing many powerful vector processing features to bear on solving your vector translation problems.
Source IIIs technical support staff becomes an extension
to your design and test groups to ensure your success. You
get a proven, reliable product with a full-time technical staff
to support it at a fraction of the cost of just one in-house
engineer. No other tool on the market can offer the level
of scope, features, performance, support and low-cost that
VTRAN is able to offer. Recently released supporting
tools, such as the Vtran User Interface which guides you
thru the translation process, and DFTView our visualization
and validation tool, further simplify the translation process.

FEATURES & BENEFITS


Blazing Speed - VTRAN can translate GigaByte les

in minutes. Text/Script batch compiler gives the user


full control over the process, or optionally Vtran User
Interface provides a simple guided method for performing translations.
For most tester interfaces, VTRAN also includes a
ReadBack module which provides a re-simulation
verication path from VTRAN-generated test programs
to a Verilog or VHDL testbench.
Short learning curve and Excellent Documentation VTRAN learning time as low as 2-6 hours for many
translation applications. Vtran Users Guide, example
translations and Application Notes all available online,
in addition to the graphical user interface.
Outstanding Technical Support - Source III is highly
responsive to all customer needs. New features are
often added within days to meet customer needs. We
provide you with personalized technical support.
Low Cost!! - VTRAN is the lowest cost, full-feature,
validated vector translation program on the market.

TECHNICAL SPECS
Cyclizing of print-on-change simulation vector les,

such as VCD/EVCD and translation of popular ATPG


vector formats such as WGL and STIL including support
for scan data sets and multiple timesets.

t.FUIPET&%"5PPMT

Design - for - Test (DFT)

Design - for - Test (DFT)

VTRAN Vector Translation Tool

Powerful Vector Processing Features Multiple time-

sets, Repeat count and vector compression, cumulative


timing and pin-maps for multiple vector les, le Merging, adding/deleting/masking signals, Data Shifting...
Tester support includes Advantest V93000, Pinscale,
T66xx, T33xx, T2000, Credence (SWAV), Teradyne
Catalyst,J750,J971/J973,FLEX, LTX, Schlumberger
ITS9000, Nextest Magnum, SVF.
Supporting tools available for timing analysis of vcd/
evcd les using VCAP, visualization and validation of
ATE programs using DFTView.
Available on Solaris SPARC and Linux 32/64 bit platforms.

INDUSTRIES SERVED
Audio, Automotive, Consumer Products, Defense,
Industrial, Entertainment, Networking, Telephony, Telecommunications, Wireless

CONTACT INFORMATION
Source III, Inc.
3941 Park Drive
Suite #20-342
El Dorado Hills, CA
95762
USA
tel: 916-941-9403
fax: 916-941-9404
corp@sourceiii.com
www.sourceiii.com

$IJQ%FTJHO3FTPVSDF(VJEF

Real Intent
Meridian CDC

Meridian CDC is the only integrated solution in the


industry that combines automatic CDC intent analysis
and metastability-aware formal analysis. Its superior
technology allows designers to use all of these strategies to guarantee complete CDC correctness. Its exible
top-down and bottom-up hierarchical analysis accommodates the different methodologies used by design
teams.
Meridian CDC automatically infers clock domain crossing
intent from the design and comprehensively analyzes
clock/reset issues, incorrect or missing synchronization,
glitch potentials, reconvergence, structurally unsafe
crossings and potential data/control crossings that need
functional verication. Its comprehensive support of
crossing styles and advanced correlation algorithms
delivers the fastest and most accurate analysis available.

Verication

Verication

Meridian CDC is the fastest, highest capacity and most


precise clock domain crossing (CDC) solution in the
market. It performs comprehensive structural and
functional analysis to ensure that signals crossing asynchronous clock domains on ASIC, or FPGA devices are
received reliably. It is the only solution that enables all
aspects of CDC sign-off for 500M+ gate SoC designs.

BENEFITS
Highest capacity to enable CDC verication on

Meridian CDCs integrated formal analysis exhaustively


veries control and data stability for all data transfer protocols and gray-coding using our metastability-aware
formal engine. It ensures safe data transfer by verifying
the underlying design principle that the CDC data path
must be a multi-cycle-path. Meridian CDCs integrated
formal solution leverages the automatic CDC intent analysis results to produce a composite report, saving users
time and effort.

500+M gate SoC designs


Fastest performance for quick verication turnaround
Most precise CDC reporting using integrated analysis
Easiest-to-use CDC solution in the industry, and is
template free
Multiple technologies to enable complete CDC signoff from RTL to netlist

PLATFORMS SUPPORTED
Meridian CDC is supported on RedHat Enterprise Linux
5.0 (64-bit) and later operating systems.

FEATURES
Automatic design environment capture from designs

or SDC constraints
Comprehensive clock intent inference and analysis
catches clock and reset issues
Metastability aware formal analysis veries control
and data stability
Flexible top-down and bottom-up analysis to accommodate different design methodologies

XXXDIJQEFTJHONBHDPN

CONTACT INFORMATION
Real Intent
990 Almanor Ave. Suite 220
Sunnyvale, CA 94070
USA
Tel: 408-830-0700
Fax: 408-737-1962
info@realintent.com
www.realintent.com

.FUIPET&%"5PPMTt

Sutherland HDL, Inc.


Expert SystemVerilog and
UVM Training Services
Founded in 1992, Sutherland HDL has trained thousands
of engineers throughout the world on Verilog, SystemVerilog, SVA and UVM.

WORKSHOP HIGHLIGHTS
Verilog and SystemVerilog for Design and Synthesis:

SystemVerilog Object Oriented Verication: Detailed

Verication

Verication

Comprehensive training on the synthesizable portions of Verilog and SystemVerilog, with emphasis
on proper coding styles for optimal simulation and
synthesis results.
training on the SystemVerilog constructs used by
advanced verication methodologies, including OOP,
constrained random stimulus, and coverage.
Mastering SystemVerilog UVM: Enables engineers

to write reusable testbenches using UVM, including


transactions, constrained random tests, coverage
and scoreboarding.
SystemVerilog Assertions for Design and

Verication Engineers: Advanced training enabling


engineers to verify complex logic using assertions.
SVA operators and properties are covered in detail.

WORKSHOP TYPES
On-site Workshops: Held at your facility, at a time

and location that is best for your engineering team.


Course topics can be customized to meet the needs
of the team. All that is required is a conference room.
Sutherland HDL can provide a portable lab environment.

DAC-2014 ANNOUNCEMENTS
Sutherland HDLs acclaimed SystemVerilog train-

ing materials are now available for licensed use in


internal corporate training! Benet from up-to-date,
best-in-class training courses without the time and
expense of developing and maintaining internal
materials. Train-the-trainer service is also available.
Sutherland HDLs eTutored self-paced Verilog and

SystemVerilog Language Foundations for Design and


Verication workshop is being demonstrated at the
Avery Design Systems Booth (1225). Stop by to try
out this fantastic way to become a SystemVerilog
wizard!

eTutored live Online Workshops: Instructor-led,

webinar-style workshops that provide all the benets


of on-site training, but with greater exibility to
mix training and work responsibilities. The same
materials, lecture and labs are used as with on-site
workshops. eTutored live workshops can be held
just for your company. Sutherland HDL also holds
periodic open-enrollment eTutored live workshops.
eTutored self-paced Online Workshops: Study

anytime and anywhere for the utmost in schedule


exibility, while still beneting from instructorassisted tutoring and lab reviews by SystemVerilog
experts. eTutored self-paced online workshops use
eBooks and custom eLearning courses developed
specically for effective online learning.

t.FUIPET&%"5PPMT

INDUSTRIES SERVED
Automotive, Consumer Products, Defense, Industrial,
Healthcare, Networking, Security, Telecommunications

CONTACT INFORMATION
Sutherland HDL, Inc.
22805 SW 92nd Place
Tualatin, Oregon 97062
United States
Tel: +1-503-692-0898
info@sutherland-hdl.com
www.sutherland-hdl.com

$IJQ%FTJHO3FTPVSDF(VJEF

Mixel, Inc.
Mixels MIPI M-PHY
Organizations: GSA, MIPI Alliance

The MXL-M-PHY-MIPI is a high-frequency low-power,


low-cost, Physical Layer IP compliant with the MIPI
Alliance Specication for M-PHY. The IP can be used
as a physical layer for many use cases. It supports DigRF
v4, CSI-3, DSI-2, Uniport-M (UniPro) LLI, JC-64.1 UFS,
SSIC, and M-PCIe protocols. By using efcient BURST
mode operation with scalable speeds, signicant power
savings can be obtained. Selection of signal slew rate
and amplitude allows reduction of EMI/RFI, while maintaining low bit error rates.
The Mixel M-PHY is characterized by:
t -PX QJO DPVOU BMM DPOUSPM TJHOBMJOH IBOEMFE JOCBOE
across the interface

Low-Power, optimized for mobile applications


Physical layer for many applications, including

DigRF v4, CSI-3, DSI-2, Uniport-M (UniPro1.6) LLI and


JC-64.1 UFS, SSIC, and M-PCIe

t0QUJNJ[FEGPSTIPSUEJTUBODF 
CVUTVJUBCMFGPSMPOH
distance (m)

TECHNICAL SPECS
Supports HS modes GEAR 1-3, series A and B with

t)VHFSBOHFPGTQFFESFRVJSFNFOUTTVCLCQTUP_(CQT

t1PXFSFGmDJFOUUISPVHIPVUBEBQUJPOVTJOHCVSTUNPEF
t$MPDLJOHTIBSFEPSOPOTIBSFESFGFSFODFDMPDLT
t*OEFQFOEFOUPGGPVOESZQSPDFTT

data rate range from 1-6 Gbps


Supports all Type-I LS modes GEAR 0-7 with data
rate range from sub-kbps-576Mbps
Supports Type-II LS mode
Slew-rate control for EMI reduction
Supports all Reference Clock frequencies used for
mobile applications, ranges from 19.2 MHz to 52 MHz

t&.*GSJFOEMZ

INDUSTRIES SERVED

t.VMUJQMFUSBOTNJTTJPONPEFTGPSCFUUFSQPXFSFGmDJFODZ

Audio, Automotive, Biometric, Computer Services,


Consumer Products, Defense, Industrial, Entertainment,
Healthcare, Networking, Security, Telephony,
Telecommunications, Wireless

t.VMUJQMFUSBOTNJTTJPOTQFFESBOHFTSBUFTGPSWBSJFEBQQMJcation needs and for mitigation of interference problems

IP - Core

IP - Core

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exibility, DC balanced coding scheme, etc)

t.VMUJQMFQPXFSTBWJOHNPEFT XIFSFQPXFSDPOTVNQUJPO
can be traded-off against recovery time

FEATURES & BENEFITS


Complies with MIPI Specication for M-PHY
Wide data range from sub kbps range up to 6Gbps,

with low jitter performance


Dual-simplex point-to-point interface with ultra low
voltage differential signaling

$IJQ%FTJHOtXXXDIJQEFTJHONBHDPN

CONTACT INFORMATION
Mixel, Inc.
97 East Brokaw Road, Suite 250
San Jose, CA 95112
United States
Tel: 408-436-8500
marketing@mixel.com
www.mixel.com

4FNJDPOEVDUPS5FDIOPMPHJFTt

True Circuits, Inc.


DDR 4/3 PHY

Byte Slice N
Byte Slice 1

Organizations: GSA
The TCI DDR 4/3 PHY is a high-performance, scalable
system using a radically new architecture that
continuously and automatically adjusts each pin
individually, correcting skew within byte lanes. This
state-of-the-art tuning acts independently on each
pin, data phase and chip select value. Read data
eye and gate timing are also continuously adjusted.
Automatic training is included for multi-cycle read
gate timing and write leveling, write data eye timing,
and internal and external (on DRAM) Vref setting.

DQS

Gate
Training
Gating/
Slave DLL

Multi-cycle
DLL
Write
Leveling

Read
Data Eye
Per Rank

Write
Data Eye
Per Rank

DQ
Jitter & Measurement

Master Timing Functions

The PHY is DFI 3.1 compliant, and when


combined with the Northwest Logic DDR 4/3
memory controller, a complete and fullyautomatic DDR 4/3 system is realized.

Clock
Deskew

Clock
Deskew

Training Interface

MEMORY CONTROLLER

Remarkable physical exibility allows the


PHY to adapt to each customers die oorplan
and package constraints, yet is delivered
and veried as a single hard macro for easy
timing closure with no assembly required.

Read FIFO

PLL

CUSTOMIZED I/O RING

REGULATED CLOCK TREE AND ROUTING

Byte Slice 0

Write FIFO
Command Address FIFO

Loop Back/
PRBS

Read/Write Training
Vref Training

Eye Diagram
TDR

SDR Tuning

FEATURES

Multi-cycle
DLL

Supports DDR4-2400, DDR3-2133 and LPDDR3-1066,


simultaneously with one hard macro

DDR Tuning (LPDDR)

DFI 3.1 compliant

%%31):

Supports x4, x8 and x16 DRAMs


Up to 144 bits wide
Up to 4 chip selects, each with unique tuning
Includes PLL, with frequency multiplication from
low frequency reference
Per-pin architecture, similar to a SerDes, automati
cally corrects skew, increases data eye and elimi
nates most parallel interface problems

Key Features | Benets


Automatic
Deskew

Skew among pins is automatically corrected; intentional


skew can reduce SSO

Tuning

State-of-the-art tuning is the key to a high performance


DDR system

$PNQMFUF1):

Completely assembled and validated hard PHY and


I/O ring means no assembly is required and performance
is guaranteed

Continuous adjustment of read data eye and gate timing


Automatic Training includes:
t Multi-cycle read gate training and write leveling
t Write data eye centering
t Internal Vref adjustment
t External Vref adjustment in each DRAM
Localized, clock-deskewed PHY-to-memory controller
interface to ease timing closure
Full speed read/write BIST with pseudo-random data,
mux-scan ATPG and 1149.1 Boundary Scan
Circuitry in each pin able to measure the data eye and
jitter, and calculate ight delays

t4FNJDPOEVDUPS5FDIOPMPHJFT

Flexibility

Proprietary tools generate and validate a PHY fitted


to the customers die floorplan and package
CONTACT INFORMATION

Timing Closure

Instrumentation

Memory controller to Mixel,


PHY timing
Inc. closure is eased by a
localized interface and97clock
Eastdeskew
Brokaw circuitry
Road, Suite 250
San Jose, CA 95112
Uniteddata
States
PHY resources can measure
eye and jitter per pin,
408-436-8500 Telephone
speeding up board bring-up
sales@mixel.com
www.mixel.com

$IJQ%FTJHOtXXXDIJQEFTJHONBHDPN

IP - Core

IP - Core

Command/Address

True Circuits, Inc.


HIGH PERFORMANCE

EASY INTEGRATION

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The PHY has been designed from the ground up to
provide extensive, automatic and continuous tuning.
Each pin constantly adjusts separate read data eyes for
even and odd data phases, taking jitter into account.
Tuning is also done separately for each chip select
value. Pervasive tuning is the key to performance.

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The IP is delivered as a completely assembled hard
macro. It is fully tested and veried with state-of-theart timing analysis. Through a careful, joint process,
the I/O ring and package are co-designed prior to
PHY delivery, so that the PHY can be fully described,
veried and delivered as a whole. Tremendous
exibility is allowed and no assembly is required.

AUTOMATIC TRAINING
DDR4 systems require a great deal of training to
function properly. The TCI PHY, combined with
an appropriate controller, does all of the required
training with almost no user interaction. Low
overhead, incremental training can be done at the
users discretion to achieve even higher data rates.
Automatic training includes multi-cycle read gate
training and write leveling, and read and write
data eye centering. DDR4 systems require internal
Vref and external Vref (on DRAM) adjustment,
which the TCI PHY performs automatically
using very sophisticated algorithms.
TOOLS
TCI uses many proprietary tools to achieve
a level of quality, exibility and automation
unseen in mixed-signal design, and not
currently available in this type of hard IP.

-08&3*/(1"$,"(&"/%#0"3%$0454
Simpler and cheaper (fewer layer) chip packages and
boards can be designed by eliminating the need for
matched trace lengths, and by allowing for tremendous
exibility in the I/O ring/package co-development.
By intentionally skewing adjacent pins, lower cost
power delivery systems can be used, and wire
bond packages can be used at a higher speed.
MEASUREMENT RESOURCES FOR
$)"3"$5&3*;"5*0/
The PHY contains many resources that can be set
up to quickly characterize a new chip, a package or a
customers PCB board. Per pin measurements include:
DQ switching jitter, read DQS jitter, read data eye,
write data eye, Vref sensitivity and ight times. Pin
and pattern weaknesses can be found quickly, without
expensive lab equipment. Using an appropriate
controller, the DDR interface can be fully characterized
without CPU interaction.

IP - Core

IP - Core

TIMING CLOSURE
To make timing closure of the DDR 4/3 PHY to
the memory controller faster, two elements are
employed: 1) the interface from PHY to memory
controller is localized and optimized for easy
timing, and 2) the clock to the memory controller
is driven by the PHY and is internally deskewed,
minimizing clock-to-clock uncertainty.

TEST
The PHY includes a full speed read/write BIST, which
tests the complete read and write paths of every
pin simultaneously with pseudo-random data. The
PHY design kits include industry-standard boundary
scan chains and all the appropriate views for DFT.

CONTACT INFORMATION

Come see us at DAC!


Booth 1707

$IJQ%FTJHOtXXXDIJQEFTJHONBHDPN

True Circuits, Inc.


4300 El Camino Real, Suite 200
Los Altos, CA 94022
Tel: 650-949-3400
Fax: 650-949-3434
sales@truecircuits.com

4FNJDPOEVDUPS5FDIOPMPHJFTt

VIEWPOINT
#Z+PIO#MZMFS $IJFG$POUFOU0GmDFS

$BO*OOPWBUJPO4BWFUIF1MBOFU
N

atural resource depletion and environmental challenges threaten all life. Can technologies like the
IoT help to reduce the human footprint on Planet Earth?
Technology is often seen as both a blessing and a curse. Many
people believe that technological advances only accelerate our
dwindling natural resources. How can science and technology
be used to reduce consumption on a global scale? To answer
these questions, John Blyler talked with Ramez Naam, a fellow at the Institute for Ethics and Emerging Technologies.
Naam is a computer scientist, former CEO of Apex nanotechnoloiges and Microsoft team leader. His latest book is titled;
The Infinite Resource The Power of Ideas on a Finite
Planet. JB
Blyler: Technology is often seen as a mechanism that
increases the depletion of resources, e.g., consumers
consume more not less with technology. Can technology
really be used to drive innovation and conserve resources?
Naam: Tech absolutely can increase
our resource use and our rate of pollution. But used intelligently it can
turn things around. In the 70s we
had massive smog. We were punching a hole in the ozone layer. We
had rivers literally catching on fire.
We had acid rain. Now the air and
water in the US are the cleanest theyve been in decades.
We invented new ways to run air conditioners and refrigerators that are allowing the ozone layer to recover.
And the average American uses less oil and less water
each year than at any time since the 1960s.
Look ahead and we can see more opportunities. We have
to beat climate change, and technology has to play a huge
role in that. People want energy. Civilization needs energy. So were going to need to keep innovating in things
like solar and wind and batteries and more ways to be
efficient in energy use so we can phase out coal and oil
and natural gas while keeping civilization moving.
All of that depends on progress in science and technology.
Blyler: What are some of the hard policy choices we
need to make in order to win the race between innovation and resource depletion?

$IJQ%FTJHOtXXXDIJQEFTJHONBHDPN

Naam: The technology innovation goes hand in hand


with changes in policy. When we turned things around
on the ozone layer, it wasnt as simple as a sudden breakthrough in cooling technology.
The ozone layer is a commons. Everyone on the planet
benefits from it. But no one owns it. No one was protecting it. No one was saying you cant do this thing that
damages it.
So the first thing we had to do was create a policy that
phased out the chemicals that were damaging the ozone
layer CFCs. Once that agreement the Montreal Protocol was signed, the incentive to create and sell and
deploy new ways to cool food and homes and cars was
huge. Businesses took care of the rest. Once their incentives were right.
Our air, our rivers, our oceans and our climate are all
the same. The biggest policy change we need to make
is to protect those commons. Once create rules that say
you cant deplete this common resource; you cant dump
pollution into this resource we all depend on then the
market tends to find a way to fix the problem.
And very specifically, on climate change, that means
some sort of rules that limit the dumping of carbon into
the atmosphere, either by capping it, or by putting a
price on it. Do that, and youll see a fast switch over to
solar and wind and other forms of clean energy.
Blyler: The Internet of Things (IoT) is a key driver of
innovation in todays electronic semiconductor markets.
Will IoT technologies and the proliferation of a connected sensor world help or hinder the cause of resource
preservation?
Naam: The Internet of Things is a big fuzzy term. It
means a lot of things to a lot of people. But under that
umbrella there are at least two things that will make
a big difference. One is getting more data and more
control over our buildings, homes, cars, appliances,
and all the other objects that fill our lives. A lot of our
energy gets used heating and running all that stuff. A
simple example is the Nest thermostat, which Google
bought. It learns your patterns of how and when you
come home and when you get up, and can heat and cool
your house appropriately and save you money and energy.
That can also reduce the amount of carbon we pump

DAC Issue 2014t

VIEWPOINT

into the atmosphere. Down the road, data from that sort
of device can be used to figure out the cheapest time to
charge an electric car, or even to give energy back from
the car to the grid, or to give the grid data about how and
when to balance load across sites.
The second case I think well see a huge impact of is environmental sensors. Sensors are getting cheaper, smaller, and less
power-hungry all the time. That means we can start to use
them in big ways to look for environmental toxins, to monitor the health of forests, to track endangered species and catch
poachers.
Any way you cut it, the ability to get more data about our world
and the objects in it is going to help us conserve.

5)&*/5&3/&50'5)*/(4*4"#*('6;;:
5&3.*5.&"/4"-050'5)*/(450"-050'
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#*(%*''&3&/$&
Blyler: Lets switch gears to talk about your works of science
fiction. What do you see as the difference between fiction and
non-fiction? Why does Sci-Fi apeal to you and most technical professionals?
Naam: Science fiction fires the imagination. It frees of from
the constraints of the current world we live in, and lets us imagine new ones. And thats tremendously exciting.
The big difference for me is where I focus. In my non-fiction I
tend to zoom out and tell the big picture story of how all the
pieces fit together. In my science fiction, theres a big picture
backdrop, but Im always telling the story through the lens of
people who are being swept along in some way that powerfully
affects them personally. The first rule in fiction is to never let
the reader put the book down.
Blyler: Thank you.
John Blyler covers todays latest high-tech, R&D and even
science fiction in blogs, magazine articles, books and videos. He is an experienced physicist, engineer, journalist,
author and professor who continues to speak at major conferences and before the camera. John is the Chief Content
Officer for Extensionmedia, which includes the brands
Chip Design, Solid State Technology, Embedded Intel and others.

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IoT sensors breed a new future as technology fades into the


background. Old industries are reformed, new applications
light up and take flight while data stalls. Tomorrow begins
today!
With more than 50 billion devices already in the market,
what does the future hold for ARM and the innovation for
the next 100 billion ARM-based chips? To find out, Krisztian Flautner, Vice President of R&D at ARM shared his
insights with John Blyler Chief Content Officer at Extension Media. What follows is a portion of that conversation.
Blyler: Lets jump right into it. What business and technology trends over the next five years will push ARM well
beyond 50 Billion chips?
Flautner: Technology will become less and less visible in
the future. This is a sign of market success and perhaps maturity, i.e., when you stop thinking about a piece of technology as technology. You take it for granted and instead focus
on the experience.
We are at this point today. We have moved beyond the early
phases of technology development, where the initial complexity of the devices required a lot of work and attention.
The new era will see more and more of these technologies
disappear into the background. The Internet of Things (IoT)
is the breeding grounds where some of this will happen,
delivering the much talked about age of ubiquitous and
pervasive computing - we are deploying sensors throughout
our environments. When combined with more computing
power, these sensors will make the environment adapt to
you instead of the other way around. This scenario is starting to happen today and well see continued progress over
the next five years.
Blyler: The future with an adaptive, sensor-rich environment where technology disappears into the background.
What else can we expect?
Flautner: Its kind of an oxymoron, but a lot of the exciting things that will be happening in the next five years are
very mundane. They are exciting precisely because they are
mundane. Computer technology will be used to significantly
reform older industries.
Read the complete article at: community.arm.com

$IJQ%FTJHOtXXXDIJQEFTJHONBHDPN

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UNLEASH THE POWER


Realize the true potential of your products with the functionality and
performance of True Circuits timing IP

PLL and DLL Hard Macros

SPEED

PERFECT TIMING REQUIRES SPEED AND PRECISION,


PARTICULARLY IN THE UNFORGIVING WORLD OF DIGITAL CHIPS

Wide output frequency ranges


Large multiplication factors (1-4096)
GHz frequencies for Gb/s data rates

True Circuits offers a complete family of standardized high performance


and general purpose PLL and DLL hard macros that have been specically
designed to meet the precise timing requirements of the entire line of

PRECISION
Low jitter
Pin programmable
Process independent

ARM processor cores and the latest DDR, SerDes, audio, video and other
interface standards.
These PLLs and DLLs are available for delivery in a range of frequencies,
multiplication factors, sizes and functions in TSMC, GLOBALFOUNDRIES,

PERFECTION
High quality, silicon proven IP
Comprehensive documentation
Easy to integrate

UMC and Common Platform processes from 180nm to 16nm.


With so much on the line and so much complexity to manage, realize the
true potential of your products with the speed, precision and perfection of
True Circuits timing IP.

Come see us at DAC!


Booth 1707

WWW.TRUECIRCUITS.COM/TIMING

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