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FUNDAMENTALS OF CMOS VLSI [10EC56]

UNIT 7
MEMORY, REGISTERS AND CLOCK:
Timing consideration
Memory elements
Memory cell arrays

Recommended reading:
Douglas A. Pucknell 3rd Edition => chapter 9 (page no. 235-261)

System timing considerations:

1. A two-phase non-overlapping clock signal is assumed to be available, and this clock alone will be used
throughout the system.
2. Clock phases are to be identified as 1 and 2 where 1 is assumed to lead 2.
3. Bits (or data) to be stored are written to register, storage elements, and subsystems on 1 of the clock;
that is, write signals WR are Anded with 1.
4. Bits or data written into storage elements may be assumed to have settled before the immediately
following 2 signals, and 2 signals may be used to refresh stored data where appropriate.
5. Delays through data paths, combinational logic, etc. are assumed to be less than the interval between the
leading edge of 1 of the clock and the leading edge of the following 2 signal.
6. Bits or data may read from storage elements on the next 1 of the clock; that is, read signals RD are
Anded with 1.
7. There must be at least one clocked storage element in series with every closed loop signal path.

Storage / Memory Elements:

The elements that we will be studying are:
Dynamic shift register
3T dynamic RAM cell
1T dynamic memory cell
Pseudo static RAM / register cell
4T dynamic & 6T static memory cell
D FF circuit
JK FF circuit

Mr.VISHWANATH M MUDDI M.Tech, Assistant Professor in ECE Dept., PESITM SHIVAMOGGA.

1. The Dynamic shifts register:

Circuit diagram:

Working:
Data bits are shifted in when 1.LD is present, one bit being entered on each 1 signal.
Each bit is stored in Cg1 as it is entered, and then transferred complemented into Cg2 during the next 2
signal. Thus, after a 1 followed by 2 signal, the stored bit is present at the output of inverter 2.
On the next 1, the next input bit is stored in Cg1 and simultaneously the first bit is stored is passed on
to inverter pair 3 and 4 by being stored in Cg3, and so on.
It will be seen that bits are clocked to the right along the shift register on each 1 followed by 2
sequence.
Once four bits are stored, the data is available in serial form from the output of inverter 8 when 1.RD is
high as further clock sequence are received.
Power dissipation:
Static dissipation is very small.
Dynamic power is significant.
Dissipation can be reduced by alternate geometry.
Volatility:
Data storage time is limited to 1msec or less.

Mr.VISHWANATH M MUDDI M.Tech, Assistant Professor in ECE Dept., PESITM SHIVAMOGGA.

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2. A Three-transistor Dynamic RAM Cell
Circuit diagram:

Working:
RD = low, bit read from bus through T1, WR = high, logic level on bus sent to Cg of T2, WR = low
again.
Bit level is stored in Cg of T2, RD=WR=low.
Stored bit is read by RD = high, bus will be pulled to ground if a 1 was stored else 0 if T2 nonconducting, bus will remain high.
Dissipation:
Static dissipation is nil.
Depends on bus pull-up & on duration of RD signal & switching frequency.
Volatility:
Cell is dynamic, data will be there as long as charge remains on Cg of T2.

3. A One- transistor Dynamic Memory Cell:

Circuit diagram:

Mr.VISHWANATH M MUDDI M.Tech, Assistant Professor in ECE Dept., PESITM SHIVAMOGGA.

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Working:
Row select (RS) = high, during write from R/W line Cm is charged.
Data is read from Cm by detecting the charge on Cm with RS = high.
Cell arrangement is bit complex.
Solution: extend the diffusion area comprising source of pass transistor, but Cd<<< Cg channel.
Another solution: create significant capacitor using poly plate over diffusion area.
Cm is formed as a 3-plate structure.
With all this careful design is necessary to achieve consistent readability.
Dissipation
No static power, but there must be an allowance for switching energy during read/write.
4. Pseudo static RAM / register cell:
Circuit diagram:

Working:
Dynamic RAM need to be refreshed periodically and hence not convenient.
Static RAM needs to be designed to hold data indefinitely.
One way is connect 2 inverter stages with a feedback.
Say f2 to refresh the data every clock cycle.
Bit is written on activating the WR line which occurs with f1 of the clock.
Bit on Cg of inverter 1 will produce complemented output at inverter 1 and true at output of inverter 2.
At every 2, stored bit is refreshed through the gated feedback path.
Stored bit is held till 2 of clock occurs at time less than the decay time of stored bit.
To read RD along with f1 is activated.
Mr.VISHWANATH M MUDDI M.Tech, Assistant Professor in ECE Dept., PESITM SHIVAMOGGA.

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Note:
WR and RD must be mutually exclusive.
2 is used for refreshing, hence no data to be read, if so charge sharing effect, leading to destruction of
stored bit.
Cells must be stackable, both side-by-side & top to bottom.
Allow for other bus lines to run through the cell.
5. Four-transistor Dynamic and Six-transistor Static CMOS Memory Cells:
Circuit diagram:

Mr.VISHWANATH M MUDDI M.Tech, Assistant Professor in ECE Dept., PESITM SHIVAMOGGA.

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Working:
Uses 2 buses per bit to store bit and bit.
Both buses are precharged to logic 1 before read or write operation.
Write operation:
Both bit & bit buses are precharged to VDD with clock f1 via transistor T5 & T6 column select line is
activated along with 2.
Bither bit or bit line is discharged along the I/O line when carrying a logic 0.
Row & column select signals are activated at the same time => bit line states are written in via T3 & T4,
stored by T1 & T2 as charge.
Read operation:

Bit and bit lines are again precharged to VDD via T5 & T6 during 1.
If 1 has been stored, T2 ON & T1 OFF.
Bit line will be discharged to VSS via T2.
Each cell of RAM array be of minimum size & hence will be the transistors.
Implies incapable of sinking large charges quickly.
RAM arrays usually employ some form of sense amplifier.
T1, T2, T3 & T4 form as flip-flop circuit.
If sense line to be inactive, state of the bit line reflects the charge present on gate capacitance of T1
&T3.
Current flowing from VDD through an on transistor helps to maintain the state of bit lines.

6. D Flip-flop Circuit:

A D Flip-flop is readily formed from a JK flip-flop by renaming the J input D and then replacing
connections to K by D.
The below figure shows the D Flip-flop which is obtained from a pseudo-static approach.

Working:

When the LD. input is high, the flip-flop is transparent changes at the D input appear at the output Q.
When the LD. goes low ,forming a storage loop.
that holds the last value on D until the enable goes high again. The storage loop will hold its state as
long as power is on; we call this a static latch.
Mr.VISHWANATH M MUDDI M.Tech, Assistant Professor in ECE Dept., PESITM SHIVAMOGGA.

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7. JK Flip-flop Circuit:

JK flip-flop is an example of a static memory element.

It is almost useful in that other common arrangements such as the D flip-flop and T flip-flop are readily
formed from the JK ararngement.

Switch logic and inverter implementation:

The below figure shows the Switch logic implementation of JK flip-flop.

Mr.VISHWANATH M MUDDI M.Tech, Assistant Professor in ECE Dept., PESITM SHIVAMOGGA.