Lovely Professional University,Punjab

Format For Instruction Plan [for Courses with Lectures and Labs

Course No

Cours Title

Course Planner

CSE539

ADVANCED COMPUTER ARCHITECTURE

12735 :: Sumit Mittu

Text Book:

Other Specific Book:

Lectures Tutorial Practical Credits

4

1 Kai Hwang, Faye A Briggs, 'Computer Architecture & Parallel Processing', Mc Graw Hill

2 V. Rajaraman, C. Siva Ram Murthy, 'Parallel Computers Architecture & Programming', PHI
3 K A Partasarthy, A Ramachandran, R Purshotaman, 'Advanced Computer Architecture', Thomson Publication
4 Dezso Sima, 'Advanced Computer Architectures', Pearson Education
5 Michael Quinn, 'Parallel Computing: Theory and Practice' Mc Graw Hill
6 Kai Hwang, 'Advance Computer Architecture - Parallelism, Scalability and Programmability', TMG
7 Hesham El Rewani & Mustafa, 'Advanced Computer Architecture and Parallel Processing', Wiley

Other Reading
Sr No

Jouranls atricles as compulsary readings (specific articles, Complete reference)

Relevant Websites
Sr. No. (Web adress) (only if relevant to the courses)
8 https://computing.llnl.gov/tutorials/parallel_comp/

Gives an abstract of basic terms and concepts of parallel computing

9 http://www.educypedia.be/computer/javacomputer.htm

Animations and images being used in the course

10 http://cs-www.cs.yale.edu/homes/arvind/cs424/notes/l2-6.pdf

Salient Features

PRAM Model of Computation

Approved for Autumn Session 2011-12

11 http://web.ebscohost.com/ehost/viewarticle?
Research on Grid Architecture and Its Application.
data=dGJyMPPp44rp2%2fdV0%2bnjisfk5Ie45PFKr6iuS7Kk63
nn5Kx94Ke
%2bT62osEewpq9JnqewUrKtuE21lr9lpOrweezp33vy3%2b2G
59q7Ra%2bntE6xqK5QtaukhN
%2fk5VXj5KR84LPfUeac8nnls79mpNfsVbSmrkixprdKpNztiuv
X8lXu2uRe8%2bLqbOPu8gAA&hid=15
12 http://web.ebscohost.com/ehost/viewarticle?
Use of a New Moodle Module for Improving the Teaching of a Basic Course on Computer
data=dGJyMPPp44rp2%2fdV0%2bnjisfk5Ie45PFKr6iuS7Kk63 Architecture.
nn5Kx94Ke
%2bT62osEewpq9JnqewUrKtuE21lr9lpOrweezp33vy3%2b2G
59q7Ra%2bntE6xqK5QtaukhN
%2fk5VXj5KR84LPfUeac8nnls79mpNfsVbSmsVC1p7NIpNzti
uvX8lXk6%2bqE8tv2jAAA&hid=15
13 http://web.ebscohost.com/ehost/viewarticle?
An Architectural Framework for the Design, Analysis and Implementation of Interactive Systems.
data=dGJyMPPp44rp2%2fdV0%2bnjisfk5Ie45PFKr6iuS7Kk63
nn5Kx94Ke
%2bT62osEewpq9JnqewUrKtuE21lr9lpOrweezp33vy3%2b2G
59q7Ra%2bntE6xqK5QtaukhN
%2fk5VXj5KR84LPfUeac8nnls79mpNfsVbSorkmvq65LpNztiu
vX8lXk6%2bqE8tv2jAAA&hid=15
14 http://web.ebscohost.com/ehost/viewarticle?
Efficient algorithm and systolic architecture for modular division.
data=dGJyMPPp44rp2%2fdV0%2bnjisfk5Ie45PFKr6iuS7Kk63
nn5Kx94Ke
%2bT62osEewpq9JnqewUrKtuE21lr9lpOrweezp33vy3%2b2G
59q7Ra%2bntE6xqK5QtaukhN
%2fk5VXj5KR84LPfUeac8nnls79mpNfsVbSnsE
%2byrq9PpNztiuvX8lXk6%2bqE8tv2jAAA&hid=15
15 http://web.ebscohost.com/ehost/viewarticle?
An Architecture for Interoperability of Embedded Systems and Virtual Reality.
data=dGJyMPPp44rp2%2fdV0%2bnjisfk5Ie45PFKr6iuS7Kk63
nn5Kx94Ke
%2bT62osEewpq9JnqewUrOnuEu2lr9lpOrweezp33vy3%2b2
G59q7Ra%2bntE6xqK5QtaukhN
%2fk5VXj5KR84LPfUeac8nnls79mpNfsVbKqrky2p7BRpNztiu
vX8lXk6%2bqE8tv2jAAA&hid=126
16 http://web.ebscohost.com/ehost/viewarticle?
Data Structures in the Multicore Age.
data=dGJyMPPp44rp2%2fdV0%2bnjisfk5Ie45PFKr6iuS7Kk63
nn5Kx94Ke
%2bT62osEewpq9JnqewUrOnuEu2lr9lpOrweezp33vy3%2b2
G59q7Ra%2bntE6xqK5QtaukhN
%2fk5VXj5KR84LPfUeac8nnls79mpNfsVbOvskqxr7ZJpNztiuv
X8lXk6%2bqE8tv2jAAA&hid=126

Approved for Autumn Session 2011-12

17 http://web.ebscohost.com/ehost/viewarticle?
Software-oriented approaches for teaching computer architecture to computer science students.
data=dGJyMPPp44rp2%2fdV0%2bnjisfk5Ie45PFKr6iuS7Kk63
nn5Kx94Ke
%2bT62osEewpq9JnqewUrOnuEu2lr9lpOrweezp33vy3%2b2
G59q7Ra%2bntE6xqK5QtaukhN
%2fk5VXj5KR84LPngeac8nnls79mpNfsVbOpskyzrLdOpNztiu
vX8lXk6%2bqE8tv2jAAA&hid=126
18 http://web.ebscohost.com/ehost/viewarticle?
64 bit Computer Architectures for Space Applications -- A study.
data=dGJyMPPp44rp2%2fdV0%2bnjisfk5Ie45PFKr6iuS7Kk63
nn5Kx94Ke
%2bT62osEewpq9JnqewUrOsuE2wlr9lpOrweezp33vy3%2b2
G59q7Ra%2bntE6xqK5QtaukhN
%2fk5VXj5KR84LPfUeac8nnls79mpNfsVbKmrlC0qa9QpNztiu
vX8lXk6%2bqE8tv2jAAA&hid=9
19 http://search.proquest.com/docview/195181488/130B5BB330 Strategic directions in computer architecture
E3796FF58/3?accountid=80692
20 http://search.proquest.com/docview/225800170/fulltextPDF/13 Advanced computer architecture and parallel processing
0B5BB330E3796FF58/9?accountid=80692
21 http://search.proquest.com/docview/237037670/130B5BB330 Advances in computer architecture
E3796FF58/12?accountid=80692
22 http://search.proquest.com/pqcentral/docview/203733654/fullt Applications on Advanced Architecture Computers
extPDF/130B5D7C51B5B43AB83/10?accountid=80692
23 http://search.proquest.com/pqcentral/docview/397957796/130 Architecture: Computers Do It Faster
B5D7C51B5B43AB83/23?accountid=80692
24 http://search.proquest.com/pqcentral/docview/245687520/fullt The last word on: Architecture
ext/130B5D7C51B5B43AB83/40?accountid=80692

Detailed Plan For Lectures

Week Number Lecture Number Lecture Topic

Chapters/Sections of Pedagogical tool

Textbook/other
Demonstration/case
reference
study/images/anmatio
n ctc. planned

Part 1
Week 1

Lecture 1

Need of high speed computing; Ways to increase

speed of computer

Open House Discussion

PPT (01) (02)

Lecture 2

Computer Generations; Trends towards parallel

processing

->Reference :1,
Section 1.1

Lecture 3

Utilizing Temporal and Data Parallelism; Inter-task

dependency

->Reference :2,
Chapter 1

PPT (02) (03) (04)

Approved for Autumn Session 2011-12

Week 1

Lecture 4

Parallelism in Uniprocessor Systems

->Reference :1,
Section 1.2

PPT (04)

Week 2

Lecture 5

Parallel Computer Structures: Pipeline Computers,

Array processors, Multiprocessor systems

->Reference :1,
Sections 1.3.1; 1.3.2;
1.3.3

PPT (04)

Lecture 6

Parallel Computer Structures: Data Flow Computers ->Reference :1,

and VLSI Computing structures; Performance of
Sections 1.3.5; 1.3.4
Parallel Computers

PPT (05)

Lecture 7

Architectural Classification Schemes: Multiplicity of

Instruction-Data streams

->Reference :1,
Section 1.4.1

PPT (05) (06)

Lecture 8

Architectural Classification Schemes: Serial v/s

Parallel Processing; Parallelism v/s Pipelining

->Reference :1,
Sections 1.4.2; 1.4.3

PPT (05)

Lecture 9

Parallel Processing Applications

->Reference :1,
Section 1.5

Lecture 10

Memory Hierarchy; Addressing Schemes for main

memory

->Reference :1,
Sections 2.1.1; 2.1.3

PPT (07) (08) (09)

Lecture 11

Concepts of Virtual Memory; Paged-memory system ->Reference :1,

Sections 2.2.1; 2.2.2

PPT (09) (10) (11)

Lecture 12

Segmented-memory system

->Reference :1,
Section 2.2.3

PPT (11)

Lecture 13

Cache Memory: Characteristics and related

concepts

->Reference :1,
Section 2.4.1

PPT (12)

Lecture 14

Cache Memory: Organization Schemes

->Reference :1,
Section 2.4.2

PPT (12)

Lecture 15

I/O Subsystem: Characteristics; Overview of

->Reference :1,
Programmed I/O, Interrupt driven I/O, DMA and IOP Section 2.5.1

Lecture 16

Pipelining: Principles of Linear Pipeline

->Reference :1,
Section 3.1.1

Lecture 17

Classification of Pipeline Processors; General

Pipelines and Reservation Tables

->Reference :1,
Sections 3.1.2 3.1.3

Lecture 18

Design of Pipelined Instruction Units

->Reference :1,
Section 3.2.1

Lecture 19

Arithmetic Pipeline Design: Example

->Reference :1,
Section 3.2.2

Lecture 20

Difficulties in Pipelining: Instruction Prefect & Branch ->Reference :1,

Handling; Data buffering & Busing Structures
Sections 3.3.1; 3.3.2

Lecture 21

Difficulties in Pipelining: Internal Forwarding &

Register Tagging; Hazard Detection & Resolution

Week 3

Week 4

Part 2
Week 4

Week 5

Week 6

PPT (13) (14)

->Reference :1,
Sections 3.3.3; 3.3.4
Approved for Autumn Session 2011-12

Week 6

Week 7

Lecture 22

Vector Processing: Characteristics

->Reference :1,
Section 3.4.1

Lecture 23

Vector Supercomputers & Scientific Attached

Processors

->Reference :1,
Sections 4.1.1; 4.1.2

Lecture 24

Test #1 Conduct (Topics from week 1-5) followed by

a Discussion on its solution

Lecture 25

Case Study: Cray - I (Vector Processor)

Lecture 26

Pipeline Chaining and Vector Loops (An example in ->Reference :1,

Cray - I)
Section 4.4.2

Lecture 27

Case Study: AP-120B (Scientific Attached

Processor)

Lecture 28

Discussion over Remarks on First Review of Term

Paper

->Reference :1,
Section 4.4.1

PPT (15) (16)

Further Reading: Case

study of other Vectors
Processors: Star-100 or
T1-ASC (Section 4.2.1)
or Cyber-205 (Section
4.4.3)

->Reference :1,
Section 4.3.1

PPT (17)
Further Reading: Case
Study of other
processors: FPS-164 or
IBM-3838 or Datawest
MATP (Section 4.3.3)

MID-TERM
Part 3
Week 8

Week 9

Lecture 29

SIMD Array Processors: SIMD Computer

organization

->Reference :1,
Section 5.5.1

PPT (18)

Lecture 30

Masking and Data Routing Mechanism; Inter-PE

Communication

->Reference :1,
Sections 5.1.2; 5.1.3

PPT (18) (19)

Lecture 31

SIMD Interconnection Networks: Static v/s Dynamic ->Reference :1,

network configurations; Mesh-connected Illiac
Sections 5.2.1; 5.2.2
Network

PPT (18) (20) (21)

Lecture 32

Parallel Algorithm for Matrix Multiplication for SIMD

Processor

->Reference :1,
Section 5.3.1

PPT (18) (21)

Lecture 33

The Space of SIMD Computers: Array and

Associative Processors; SIMD Computer
Perspectives

->Reference :1,
Section 6.1

PPT (21) (22) (23)

Lecture 34

Case Study: Illiac-IV (Architecture & Applications)

->Reference :1,
Sections 6.2.1; 6.2.2

PPT (18) (24)

Further Reading: Case
Study of BSP System
Architecture (Section
6.2.3)
Approved for Autumn Session 2011-12

Week 9

Week 10

Lecture 35

Case Study: The MPP System

->Reference :1,
Section 6.3.1

PPT (24)

Lecture 36

Discussion over Remarks on Second Review of

Term Paper

Lecture 37

Multi-processor systems: Functional Structures and ->Reference :1,

Loosely Coupled Multiprocessors
Section 7.1.1

PPT (24)

Lecture 38

Tightly Coupled Multiprocessor Systems

->Reference :1,
Section 7.1.2

PPT (24) (25)

Lecture 39

Shared Memory & Distributed Shared Memory

Parallel Computers; Message Passing Parallel
Computers; Cache Coherence in Multiprocessor
Systems

->Reference :2,
Sections 4.8.2 - 4.8.6;
4.10; 4.11

PPT (26) (27) (28)

Lecture 40

Test #2 Conduct (Topics from week 6-9) followed by

a Discussion on its solution

Lecture 41

Multiprocessor System: Interconnection Networks

->Reference :1,
Sections 7.2.1; 7.2.2

PPT (24)

Lecture 42

Processor Characteristics for Multiprocessing;

Interleaved Memory Organizations;

->Reference :1,
Sections 7.1.3; 7.3.1

Lecture 43

Classification of Multiprocessor Operating Systems; ->Reference :1,

Language Features to Exploit Parallelism
Sections 7.4.1; 7.5.1

Lecture 44

Exploratory and Commercial Multiprocessor

Systems; Case Study of Cray X-MP System
Architecture and Multitasking on Cray X-MP

->Reference :1,
Sections 9.1.1; 9.6.1;
9.6.2

Further Reading: Case

study of C.mmp (Section
9.2.1); S1 (Section
9.3.1); Mainframe
Multiprocessors IBM
370/168, 3-033 and
3081 (Section 9.5.1)

Lecture 45

Control Flow v/s Data Flow Computers; Static &

Dynamic Data Flow computers' organization

->Reference :1,
Section 10.1.1

PPT (29)

Lecture 46

VLSI Computing Structures and Systolic Array

Architecture

->Reference :1,
Section 10.3.1

Lecture 47

Parallel Overhead & Speed-up Performance Laws

->Reference :2,
Chapter 9

Lecture 48

Scalability metrics & Performance measurement

tools

Part 4
Week 10

Week 11

Week 12

Approved for Autumn Session 2011-12

Spill Over
Week 13

Lecture 49

Design of Vectorizing Compilers

->Reference :1,
Section 4.5.2

Lecture 50

Detection of Parallelism in Programs

->Reference :1,
Section 7.5.2

Lecture 51

Multiprocessor Scheduling Strategies

->Reference :1,
Section 8.3

Lecture 52

Real-Time Image Processing using VLSI structures ->Reference :1,

Section 10.4.4

Details of homework and case studies

Homework No.

Objective

Topic of the Homework

Nature of homework
(group/individuals/field
work

Evaluation Mode

Allottment /
submission
Week

Test 1

Student Evaluation Topics from Week #1 to Week #5

Individual

As per questions
set in test paper

6/6

Test 2

Student Evaluation Topics from Week #6 to Week #9

Individual

As per questions
set in test paper

10 / 10

Term Paper 1

Research Work
As per topic assigned through Term paper allocation list
and Paper Writing

Individual

Written Report
and
Viva/Presentation

3/9

Scheme for CA:out of 100*

Component
Test, Term Paper

Frequency

Out Of
2

Each Marks Total Marks

3

Total :-

10

20

10

20

* In ENG courses wherever the total exceeds 100, consider x best out of y components of CA, as explained in teacher's guide available on the
UMS
List of suggested topics for term paper[at least 15] (Student to spend about 15 hrs on any one specified term paper)
Sr. No. Topic
1 Simulation: Arithmetic Pipeline [Program to Demonstrate the operation of Arithmetic Pipeline. Take some instruction as input and represent its processing
through pipeline mode.]
7

Approved for Autumn Session 2011-12

2 Simulation: Data Flow Computing [Program to demonstrate operation of Data Flow based systems.Take input some statements and process them using data
flow models, diagrams and numerical analysis]
3 Simulation: Virtual Memory System [Program to illustrate the organization & operation of the virtual memory system.]
4 Simulation: Cache Memory System & Cache Mapping [Program to simulate the structure & operation of cache memory; The Mapping policies be
implemented in program with arbitrary data taken as input and hit/miss as output]
5 Simulation: FIFO, LFU and MFU Page Replacement Algorithms [Program to take a Page reference string & frame count as input and diagrammatically
illustrate the Page Allocation & replacement]
6 Simulation: Paged Memory System [Program to perform the mapping of the user input logical address to system required physical address in a simple Paging
system]
7 Simulation: Segmented Memory System [Program to demonstrate the operation & organization of segmented memory system. Take an arbitrary program as
input, segment it & illustrate the access to segments as required]
8 Co-Processors & Parallelism [Dicuss about the concept & need of using co-processors,their benefits & overheads, if any. Also illustrate the degree to which
they can exploit parallelism in machine]
9 Intel's Multi-core Processors [Detail the development in Multi core architecture of Intel Machines.]
10 Cahe Coherence Schemes: An analysis of some practically used scheme. [With the advent of parallel processors that can have multi level of memories and
multilevel caches, Cache consistency and Cache Coherence becomes crucial issue. Taking example of any dual core machine from Intel explain how cache
is being coherence is being managed. Support your answers with some real numerical facts]
11 Processor Chips: From small to smaller and smallest! [With time CPU chips are getting smaller and smaller. Argue on how small a CPU chip can go. What
hurdles may be (or are being) faced by manufacturers in making chips smaller. Give references to practical chips available in market.]
12 64-bit v/s 32-bit processors [Are the 64-bit machines always (and actually) faster than the 32-bit machines? Illustrate the justfication taking some real-world
processors in consideration.]
13 3-D Transistors [Intel released the so-called 3-D (tri-gate) transistors in May 2011. Perform an anlysis of the archtiectire and performance of the 3-D
transisitors.]
14 Intel Processors vs AMD Processors [Collect the clock speed, architecture advancements of Intel & AMD Microprocessor in last 2 decades. Analyse this
evolution with Moores law which state transistors in a microprocessor doubles every 18 months]
15 Itanium Series of Processors [Detail architecture of Itanium series of processor and illustrate the initiatives used to increase the efficiency of itanium machine]

Approved for Autumn Session 2011-12