Professional Documents
Culture Documents
If a large Vds is applied this voltage with deplete the Inversion layer .This
Voltage effectively pinches off the channel near the drain.
12.Give the different types of CMOS process?
p-well process, n-well process
Silicon-On-Insulator Process
Twin- tub Process
13.What are the steps involved in twin-tub process?
Tub Formation
Thin-oxide Construction
Source & Drain Implantation
Contact cut definition
Metallization.
14.What are the advantages of Silicon-on-Insulator process?
No Latch-up
Due to absence of bulks transistor structures are denser than bulk silicon.
15.What is BiCMOS Technology?
It is the combination of Bipolar technology & CMOS technology.
16.What are the basic processing steps involved in BiCMOS process?
Additional masks defining P base region
N Collector area
Buried Sub collector (SCCD)
Processing steps in CMOS process
17.What are the advantages of CMOS
process? Low power Dissipation
High Packing density
Bi directional capability
18.What are the advantages of CMOS
process? Low Input Impedance
Low delay Sensitivity to load.
19.What is the fundamental goal in Device modeling?
To obtain the functional relationship among the terminal electrical variables of
the device that is to be modeled.
20.Define Short Channel devices?
Transistors with Channel length less than 3- 5 microns are termed as Short channel
devices. With short channel devices the ratio between the lateral & vertical
dimensions are reduced.
21.What is pull down device?
A device connected so as to pull the output voltage to the lower supply voltage usually
0V is called pull down device.
22.What is pull up device?
A device connected so as to pull the output voltage to the upper supply voltage usually
VDD is called pull up device.
23. Why NMOS technology is preferred more than PMOS technology?
N- channel transistors has greater switching speed when compared tp PMOS transistors.
24. What are the different operating regions foe an MOS transistor?
Cutoff region
2
CMOS Technology
Low static power dissipation
High input impedance (low drive
current)
Scalable threshold voltage
High noise margin
High packing density
High delay sensitivity to load (fanout limitations)
Low output drive current
Low gm (gm Vin)
Bidirectional capability
Bipolar technology
High power dissipation
Low input impedance (high drive
current)
Low voltage swing logic
Low packing density
Low delay sensitivity to load
High output drive current
High gm (gm eVin)
High ft at low current
Essentially unidirectional
35. Give the CMOS inverter DC transfer characteristics and operating regions
state value.
37. Define Fall time
Fall time, f is the time taken for a waveform to fall from 90% to 10% of its steadystate value.
38. Define Delay time
Delay time, d is the time difference between input transition (50%) and the 50%
output level. This is the time taken for a logic transition to pass from input to output.
39. What are two components of Power dissipation.
There are two components that establish the amount of power dissipated in
a
CMOS circuit. These are:
i)
Static dissipation due to leakage current or other current
drawn continuously from the power supply.
ii)
Dynamic dissipation due
to
- Switching transient current
- Charging and discharging of load capacitances.
40. Give some of the important CAD tools.
Some of the important CAD tools
are:
i)
Layout
editors
ii)
Design Rule checkers
(DRC)
iii)
Circuit
extraction
41.What is Verilog?
Verilog is a general purpose hardware descriptor language. It is similar in
syntax to the C programming language. It can be used to model a digital system
at many levels of abstraction ranging from the algorithmic level to the switch
level.
42. What are the various modeling used in Verilog?
1.
Gate-level
modeling
2.
Data-flow
modeling
3.
Switch-level
modeling
4.
Behavioral
modeling
43. What is the structural gate-level modeling?
Structural modeling describes a digital logic networks in terms of the
5
49
50.
4.
Level-sensitive timing control
Give the different arithmetic operators?
Operator symbol
Operation performed
*
Multiply
/
Divide
+
Add
Subtract
%
Modulus
**
Power (exponent)
Number of operands
Two
Two
Two
Two
Two
Two
Number of operands
One
Two
Two
Two
Two
Two
Two
51.
52.
53.
54.
55.
56.
( [expression3] ) true-statement 3;
else default-statement;
The [expression] is evaluated. If it is true (1 or a non-zero value) truestatement is executed. If it is false (zero) or ambiguous (x), the falsestatement is executed.
Name the types of ports in Verilog
Types of port
Keyword
Input port
Input Output port
Output Bidirectional port
inout
What are the types of procedural assignments?
1.
Blocking assignment
2.
Non-blocking assignment
Give the different symbols for transmission gate.
57.
58.
59.
60.
2.
mask
4.
61.
macros.
67. What are Programmable Interconnects ?
In a PAL, the device is programmed by changing the characteristics if the
switching element. An alternative would be to program the routing.
68. Give the steps inASIC design flow. a.
Design entry
b. Logic synthesisSystem
partitioning c. Prelayout
simulation.
d.
Floorplanning
e. Placement
f.
Routing
g.
Extraction
1.
Postlayout
simulation
function. These tests assert that all the gates in the chip, acting in concert,
achieve a desired function. These tests are usually used early in the design
cycle to verify the functionality of the circuit.
74. Write notes on manufacturing tests?
Manufacturing tests verify that every gate and register in the chip
functions correctly. These tests are used after the chip is manufactured to
verify that the silicon is intact.
75. Mention the defects that occur in a chip?
a) layer-to-layer
shorts b)
discontinous
wires
c) thin-oxide shorts to substrate or well
76. Give some circuit maladies to overcome the defects?
i. nodes shorted to power or
ground ii. nodes shorted to
each other
iii. inputs floating/outputs disconnected
77. What are the tests for I/O integrity?
i. I/O
level test
ii. Speed
test
iii. IDD test
78. What is meant by fault models?
Fault model is a model for how faults occur and their impact on
circuits.
79. Give some examples of fault models?
i. Stuck-At Faults
ii. Short-Circuit and Open-Circuit Faults
80. What is stuck at fault?
With this model, a faulty gate input is modeled as a stuck at
zero or stuck at one. These faults most frequently occur due to thinoxide shorts or metal-to-metal shorts.
81. What is meant by observability?
The observability of a particular internal circuit node is the
degree to which one can observe that node at the outputs of an
integrated circuit.
82. What is meant by controllability?
The controllability of an internal circuit node within a chip is a
measure of the ease of setting the node to a 1 or 0 state.
83. What is known as percentage-fault coverage?
The total number of nodes that, when set to 1 or 0, do result in the
detection of the fault, divided by the total number of nodes in the circuit, is
12
15