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ECE-MAJOR-VLSI Projects

Project Code

Project Name

LowPower and AreaEfficient Carry Select Adder

Design and Characterization of Parallel Prefix Adders using FPGAs

Simulation of Image Encryption using AES Algorithm

An Autonomous Vector/Scalar Floating Point Coprocessor for FPGAs

A FPGA IEEE7542008 DECIMAL64 FLOATINGPOINT ADDER/SUBTRACTOR

Implementation of Convolutional Encoder and Viterbi Decoder using Verilog HDL

Design and Simulation of UART Serial Communication Module Based on VHDL

8
Design of threelift controller based on FPGA
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Design of threelift controller based on FPGA

A Review on Power Optimization of Linear feed back shift register (LFSR) for Low Power BIST

10

The Design of an 8bit CISC CPU Based on FPGA

11

Optimized Design of UART IP Soft Core based on DMA Mode

12

Design of SHA1 Algorithm based on FPGA

13

Implementation of NonPipelined and Pipelined Data Encryption Standard (DES) Using Xilinx Virtex6 FPGA Technology

14

FPGA Implementation of Pipelined 2DDCT and Quantization Architecture for JPEG Image Compression

15

A New VLSI Architecture of Parallel MultiplierAccumulator Based on Radix2 Modified Booth Algorithm

16

Test data Compression using efficient bit mask and dictionary selection method

17

FPGA Implementation of efficient FFT algorithm based on complex sequence

18

Simple Traffic light Controller: A Digital System design product

19

Implementation of FIR Filter on FPGA Using DAOBC Algorithm

20

FPGA based implementation of high performance Architectural Low Level Power 32 bit RISC Core

21

A Fast VLSI design of SMS4 Cipher based on twisted BDD sbox architecture

22

A FPGA IEEE754 2008 Decimal 64 Floating Point Multiplier

23

Design and implementation of lossless high speed data compression and Decompression using VHDL

24

Design and implementation of Encryption module in DES for SECURITY using VERILOG

25

Design and implementation of Decryption module in DES for SECURITY using VERILOG

26

Implementation of real time Candy mechanic using VHDL

27

Design and implementation of pattern generator for circuit under test using VERILOG

28

Efficient design of butterfly architecture for radix 8 fast Fourier transform using VHDL

29

Design and implementation of Digital Code Lock using VHDL

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30

Implementation of First in First out design using VHDL

31

VLSI design of Traffic Light Controller using VHDL

32

Design and implementation of Encryption module for AES core using VERILOG

33

Design and implementation of Decryption module for AES core using VERILOG

34

Design and implementation of Elevator Controller using VHDL

35

Design and implementation of LFSR for low power applications using VERILOG

36

Design and implementation of Serializer and deserializer using VHDL

37

Implementation of Frequency Distributor module using VHDL

38

Design and implementation of Vending machine controller using VHDL

39

Design and implementation of Finite impulse response filter using VHDL

40

VLSI design of 8 bit microprocessor implementation using VHDL

41

Design and implementation of array multiplier in VERILOG

42

Design and implementation of state machine controller

43

Design and implementation of Content Addressable Memory using VHDL

44

Design and implementation of House hold alarm system using VHDL

45

VLSI design of Reduced Instruction Set Computer Processor core using VHDL

46

VLSI implementation of Memory Core design using VHDL

47

Design and implementation of Random number Generator using VERILOG

48

Design and implementation of USB Transmitter

49

Design and implementation of Booth multiplier

50

Design and implementation of Wallace Tree multiplier

51
Performance evaluation of high speed and low power adders
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52

Design of an ATM (Automated Teller Machine) Controller

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