Sequential Circuits

Introduction
ƒ A sequential
q circuit consists of a ffeedback ppath, and
employs some memory elements.
Combinational
outputs Memory outputs

Combinational Memoryy
logic elements

External inputs
Sequential circuit = Combinational logic + Memory Elements
Introduction
ƒ There are two types of sequential circuits:
™synchronous:
h outputs
t t change
h only
l att specific
ifi ti
time
™asynchronous: outputs change at any time

ƒ Multivibrator:
M lti ib t a class
l off sequential
ti l circuits.
i it Th They can bbe:
™bistable (2 stable states)
™monostable or one
one-shot
shot (1 stable state)
™astable (no stable state)

ƒ Bistable logic devices: latches and flip

flip-flops
flops.
ƒ Latches and flip-flops differ in the method used for
changing their state.
state
Memory Elements
ƒ Memory element:
element a device which can remember value
indefinitely, or change value on command from its inputs.

Memory Q
command
d element
l t stored
d value
l

ƒCharacteristic table:
Command Q(t) Q(t+1)
(at time t) Q(t): current state

Set X 1 Q(t+1) or Q+: next state

Reset X 0
Memorise / 0 0
No Change 1 1
Memory Elements
ƒ Memory element with clock
clock. Flip
Flip-flops
flops are memory
elements that change state on clock signals.
Memory Q
command
d element stored
t d value
l

clock
ƒ Clock
Cl k is usually
ll a square wave.

Positive pulses

Positive edges Negative edges

 S-R Latch
ƒ Characteristics table for active-high
active high input S-R
S R latch:
S R Q Q'
0 0 NC NC No change. Latch
remained in present state. S Q
1 0 1 0 Latch SET.
R Q'
0 1 0 1 Latch RESET.
1 1 0 0 Invalidcondition
Invalid condition.

ƒ Characteristics table for active-low input S'-R' latch:

S' R' Q Q'

S Q
1 1 NC NC No change
change. Latch
remained in present state.
R Q'
0 1 1 0 Latch SET.
1 0 0 1 Latch RESET.
0 0 1 1 Invalid condition.
S-R Latch
ƒ Active-HIGH
A ti HIGH input
i t S-R
S R latch
lt h

10 100 R S R Q Q
Q'
Q 11000 1 0 1 0 initial
0 0 1 0 (afer S=1, R=0)
0 1 0 1
Q' 0 0 1 1 0 0 0 0 1 (after S=0, R=1)
10 001 S
ƒ Active-LOW input S’-R’ latch 1 1 0 0 invalid!

S' Q
S' R' Q Q'
R'
R Q'
S'
S 1 0 0 1 initial
Q 1 1 0 1 (afer S'=1, R'=0)
0 1 1 0
1 1 1 0 (after S'=0, R'=1)
Q'
Q
R' 0 0 1 1 i lid!
invalid!
Gated S-R Latch

ƒ S-R latch + enable input

p ((EN)) and 2 NAND
gates → gated S-R latch.

S
Q S
Q
EN
EN
R Q'

Q'
Q

R
Gated D Latch
ƒ Make R input equal to S' → gated D latch.
ƒ D latch eliminates the undesirable condition of invalid state
in the S-R latch.

D
Q D
Q
EN
EN
Q'
Q'
Q
Gated D Latch
ƒ When EN is HIGH,
HIGH
™D=HIGH → latch is SET
™D=LOW → latch is RESET
ƒ Hence when EN is HIGH, Q ‘follows’ the D (data) input.
ƒ Characteristic table:

EN D Q(t+1)
Q(t 1)
1 0 0 Reset
1 1 1 Set
0 X Q(t) No change

When EN=1, Q(t+1) = D

Edge-Triggered Flip-flops
ƒ Flip-flops: synchronous bistable devices
ƒ Output changes state at a specified point on a triggering
input called the clock.
ƒ Change state either at the positive edge (rising edge) or at the
negative edge (falling edge) of the clock signal.

Clock signal

Positive edges Negative edges

Edge-Triggered Flip-flops
ƒ S-R, D and J-K edge-triggered flip-flops. Note the “>”
symbol at the clock input.

S Q D Q J Q
C C C
R Q' Q' K Q'

Positive edge-triggered flip-flops

S Q D Q J Q
C C C
R Q' Q' K Q'

Negative
g edge-triggered
g gg flip-flops
p p
J-K Flip-flop

ƒ JJ-K
K flip
flip-flop:
flop: Q and Q
Q' are fed back to the pulse
pulse-steering
steering
NAND gates.
ƒ No invalid state.
ƒ Include a toggle state.
™JJ=HIGH
HIGH (and K LOW) D SET state
K=LOW)
™K=HIGH (and J=LOW) D RESET state
™both inputs LOW D no change
™both inputs HIGH D toggle
J-K Flip-flop
ƒ J-K flip-flop.
J
Q
Pulse
CLK transition
detector
Q'
K

ƒ Characteristic table.
Q J K Q(t+1)
J K CLK Q(t+1) Comments
0 0 0 0
0 0 ↑ Q(t) No change
0 0 1 0
0 1 ↑ 0 Reset
0 1 0 1
1 0 ↑ 1 Set
1 1 ↑ Q(t)' Toggle 0 1 1 1
1 0 0 1
Q(t+1) = J.Q
J Q' + K
K'.Q
Q 1 0 1 0
1 1 0 1
1 1 1 0
T Flip-flop
ƒ T flip-flop: single-input version of the J-K flip flop,
formed by tying both inputs together.

T
Q T J
Pulse Q
CLK t
transition
iti CLK C
detector
Q' K Q'

ƒ Characteristic table.
T CLK Q(t+1) Comments Q T Q(t+1)
0 ↑ Q(t) No change 0 0 0
1 ↑ Q(t)' Toggle 0 1 1
1 0 1
1 1 0
Q(t+1) = T.Q
T Q' + T
T'.Q
Q
 T Flip-flop

ƒ Application: Frequency division.

High High High

J J QA J QB
Q
CLK C CLK C C

K K K

CLK CLK

Q QA

QB

Divide clock frequency by 2. Divide clock frequency by 4.

ƒ Application: Counter
Asynchronous Inputs
ƒ S-R, D and J-K inputs are synchronous inputs, as data on
these inputs are transferred to the flip-flop’s output only
on the triggered edge of the clock pulse.
pulse
ƒ Asynchronous inputs affect the state of the flip-flop
independent of the clock; example: preset (PRE) and clear
(CLR) [or direct set (SD) and direct reset (RD)]
ƒ When PRE=HIGH,, Q is immediatelyy set to HIGH.
ƒ When CLR=HIGH, Q is immediately cleared to LOW.
ƒ Flip-flop
Flip flop in normal operation mode when both PRE and
CLR are LOW.
Asynchronous Inputs
ƒ A J-K flip-flop with active-LOW preset and clear inputs.

PRE PRE

J
Q
J Q Pulse
C t
transition
iti
CLK
detector
K Q' Q'
K

CLR CLR

CLK

PRE

CLR
Q
J = K = HIGH Preset Toggle Clear
 Introduction: Counters

ƒ Counters are circuits that cycle through a specified

number of states.
ƒ Two
T types off counters:
™synchronous (parallel) counters
™asynchronous (ripple) counters
ƒ Ripple counters allow some flip-flop outputs to be used
as a source of clock for other flip-flops.
ƒ Synchronous counters apply the same clock to all flip-
flops.
Asynchronous (Ripple) Counters
ƒ Asynchronous counters: the flip-flops do not change
states at exactly the same time as they do not have a
common clock pulse.
ƒ Also known as ripple
pp counters,, as the input
p clock pulse
p
“ripples” through the counter – cumulative delay is a
drawback.
ƒ n flip-flops
fl fl → a MOD (modulus) n
d l 2 counter. (Note: A
MOD-x counter cycles through x states.)
ƒ Output of the last flip-flop
flip flop (MSB) divides the input clock
frequency by the MOD number of the counter, hence a
counter is also a frequency divider.
 Asynchronous (Ripple) Counters
ƒ Example:
p 2-bit ripple
pp binaryy counter.
ƒ Output of one flip-flop is connected to the clock input of the
next more-significant flip-flop.
HIGH

J Q0 J Q1
CLK C C
Q0
K K

FF0 FF1
CLK 1 2 3 4

Q0 Timing diagram
Q0 0 1 0 1 0 00 → 01 → 10 → 11 → 00 ...
Q1 0 0 1 1 0
 Asynchronous (Ripple) Counters

ƒ Example: 3-bit ripple binary counter.

HIGH

J Q0 J Q1 J Q2
CLK C Q0 C Q1 C
K K K
FF0 FF1 FF2

CLK 1 2 3 4 5 6 7 8

Q0 0 1 0 1 0 1 0 1 0

Q1 0 0 1 1 0 0 1 1 0

Q2 0 0 0 0 1 1 1 1 0

Recycles back to 0
 Asynchronous (Ripple) Counters

ƒ Propagation delays in an asynchronous (ripple-clocked)

binary counter.
ƒ If the accumulated delay is greater than the clock pulse
pulse, some
counter states may be misrepresented!

CLK 1 2 3 4

Q0

Q1

Q2
tPHL (CLK to Q0) tPHL (CLK to Q0)
tPLH (Q0 to Q1) tPHL (Q0 to
t Q1)
tPLH
(CLK to Q0) tPLH (Q1 to Q2)
 n
Asyn Counters with MOD no
Asyn. no. < 2

ƒ States may be skipped resulting in a truncated sequence.

ƒ Technique:
q force counter to recycle
y before
f ggoingg through
g all
of the states in the binary sequence.
ƒ Example: Given the following circuit, determine the
counting sequence (and hence the modulus no.)

C B A
Q J Q J Q J
All J, K CLK CLK CLK
inputs Q K Q K Q K
CLR CLR CLR
are 1
(HIGH). B
C
 n
Asyn Counters with MOD no
Asyn. no. < 2

ƒ Example (cont’d):
C B A
Q J Q J Q J
All J, K CLK CLK CLK
inputs Q K Q K Q K
CLR CLR CLR
are 1
(HIGH)
(HIGH). B
C

1 2 3 4 5 6 7 8 9 10 11 12
Clock MOD-6 counter
A produced by
clearing (a MOD-8
B
y counter))
binary
C when count of six
NAND 1 (110) occurs.
Output 0
 n
Asyn Counters with MOD no
Asyn. no. < 2

ƒ Decade counters (or BCD counters) are counters with 10

states (modulus-10) in their sequence. They are
commonlyy used in dailyy life (e.g.:
( g utilityy meters,,
odometers, etc.).
ƒ Design an asynchronous decade counter.
(A.C)'

HIGH
D C B A
J Q J Q J Q J Q

CLK C C C C
K K K K
CLR CLR CLR CLR
 n
Asyn Counters with MOD no
Asyn. no. < 2

ƒ Asynchronous decade/BCD counter (cont’d).

HIGH D C B A
J Q J Q J Q J Q (A C)'
(A.C)'
CLK C C C C
K K K K
CLR CLR CLR CLR

0
1 2 3 4 5 6 7 8 9 10 11
Clock 0

D 0 1 0 1 0 1 0 1 0 1 0

C 0 0 1 1 0 0 1 1 0 0 0

B 0 0 0 0 1 1 1 1 0 0

A 0 0 0 0 0 0 0 0 1 1
NAND
output
 Cascading Asynchronous Counters

ƒ Larger asynchronous (ripple) counter can be

constructed by cascading smaller ripple
counters.
ƒ Connect last-stage output of one counter to
the clock input of next counter so as to
achie e higher-modulus
achieve highe mod l s opeoperation.
ation
ƒ Example: A modulus-32 ripple counter
constructed from a modulus-4 counter and a
modulus-8 counter.
Q Q
0 Q 1 Q Q 2 3 4

J Q J Q J Q J Q J Q
CLK C C C C C
Q' K Q' Q' K Q' K Q'
K K

Modulus-4 counter Modulus-8 counter

 Cascading Asynchronous Counters

ƒ If counter is a not a binary counter, requires additional

output.
ƒ Example: A modulus-100 counter using two decade
counters.
freq/10
1 CTEN Decade CTEN Decade freq/100
counter TC counter TC
CLK C Q3 Q2 Q1 Q0 C Q3 Q2 Q1 Q0
freq

TC = 1 when counter recycles

y to 0000
Synchronous (Parallel) Counters
ƒ Synchronous (parallel) counters: the flip-flops
flip flops are
clocked at the same time by a common clock pulse.
ƒ We can design these counters using the sequential logic
d i
design process
ƒ Example: 2-bit synchronous binary counter (using T flip-
flops, or JK flip-flops with identical J,K inputs).

Present Next Flip-flop

state state inputs
00 01 A1 A0 A1+ A0+ TA1 TA0
0 0 0 1 0 1
0 1 1 0 1 1
11 10
1 0 1 1 0 1
1 1 0 0 1 1
 Synchronous (Parallel) Counters

ƒ Example: 2-bit synchronous binary counter (using T flip-

flops, or JK flip-flops with identical J,K inputs).

Present Next Flip-flop

TA1 = A0
state state inputs
A1 A0 A1+ A0+ TA1 TA0 TA0 = 1
0 0 0 1 0 1
0 1 1 0 1 1
1
1 0 1 1 0 1
A0 A1
1 1 0 0 1 1 J Q J Q
C C
Q'
Q K QQ'
K

CLK
 Synchronous (Parallel) Counters

ƒ Example: 3-bit synchronous binary counter (using T

flip-flops, or JK flip-flops with identical J, K inputs).
P res en t N ext F lip - f lo p
s ta te s ta te in p u t s
A2 A1 A0 A 2+ A 1+ A 0+ TA 2 TA1 TA 0

0 0 0 0 0 1 0 0 1
0 0 1 0 1 0 0 1 1
0 1 0 0 1 1 0 0 1
0 1 1 1 0 0 1 1 1
1 0 0 1 0 1 0 0 1
1 0 1 1 1 0 0 1 1
1 1 0 1 1 1 0 0 1
1 1 1 0 0 0 1 1 1

A1 A1 A1

1 1 1 1 1 1 1

A2 1 A2 1 1 A2 1 1 1 1

A0 A0 A0

TA2 = A1.A0 TA1 = A0 TA0 = 1

 Synchronous (Parallel) Counters
ƒ Example: 3-bit synchronous binary counter (cont’d).
TA2 = A1.A0 TA1 = A0 TA0 = 1
A2 A1 A0

Q Q Q
J K J K J K
CP
1
 Synchronous (Parallel) Counters

ƒ Example: 4-bit synchronous binary counter.

TA3 = A2 . A1 . A0
TA2 = A1 . A0
TA1 = A0
TA0 = 1

1 A1.A0 A2.A1.A0

A0 J A1 J A2 J A3
J Q Q Q Q
C C C C
Q' K Q' K Q' K Q'
K

CLK
 Synchronous (Parallel) Counters

ƒ Example: Synchronous decade/BCD counter.

Clock pulse Q3 Q2 Q1 Q0
Initially 0 0 0 0
1 0 0 0 1
2 0 0 1 0 T0 = 1
3 0 0 1 1
4 0 1 0 0 T1 = Q3'.Q0
5 0 1 0 1
6 0 1 1 0 T2 = Q1.Q0
7 0 1 1 1
8 1 0 0 0 T3 = Q2.Q1.Q0 + Q3.Q0
9 1 0 0 1
10 (recycle) 0 0 0 0
 Synchronous (Parallel) Counters

ƒ Example: Synchronous decade/BCD counter (cont’d).

T0 = 1
T1 = Q3'.Q0
T2 = Q1.Q0
T3 = Q2.Q
Q1.QQ0 + Q3.Q
Q0

Q0

1 T T Q1 T Q2 T Q3
Q Q Q Q
C C C C
Q' Q' Q' Q'

CLK
 Up/Down Synchronous Counters

ƒ Example: A 3-bit up/down synchronous binary counter

(cont’d).
TQ0 = 1
TQ1 = (Q0.Up) + (Q0'.Up' )
TQ2 = ( Q0.Q1.Up ) + (Q0'. Q1'. Up' )

Q0 Q1

1 T T T Q2
Q Q Q
Up C C C
Q' Q' Q'

CLK
 Introduction: Registers

ƒ An n-bit register has a group of n flip-flops and some

logic gates and is capable of storing n bits of information.
ƒ The
Th fli
flip-flops
fl store theh iinformation
f i while
hil the
h gates
control when and how new information is transferred
into the register.
ƒ Some functions of register:
™retrieve data from register
™store/load
t /l d new ddata t iinto
t register
i t ((serial
i l or parallel)
ll l)
™shift the data within register (left or right)
 Simple Registers
ƒ No external gates.
ƒ Example: A 4-bit register. A new 4-bit data is loaded every
cclock
oc cycle.
cyc e.

A3 A2 A1 A0

Q Q Q Q
D D D D
CP

I3 I2 I1 I0
 Registers With Parallel Load

ƒ Instead of loading the register at every clock pulse, we

may want to controll when
h to lload.
d
ƒ Loading a register: transfer new information into the
register. Requires a load control input.
ƒ Parallel loading: all bits are loaded simultaneously.
Registers With Parallel Load
Load'.A
Load A0 + Load.
Load I0
Load
D Q A0
I0

D Q A1
I1

D Q A2
I2

D Q A3
I3

CLK
CLEAR
 Using Registers to implement
S
Sequential
ti l Ci
Circuits
it

ƒ A sequential circuit may consist of a register (memory) and a

combinational circuit.
Next-state value

Register Combin-
Clock ational
circuit
Inputs Outputs
The external inputs and present states of the register
determine the next states of the register and the
external outputs, through the combinational circuit.
The combinational circuit mayy be implemented
p by
y any
y
of the methods covered in MSI components and
Programmable Logic Devices.
 Shift Registers

ƒ Another function of a register, besides storage, is to

provide for data movements.
ƒ Each
E h stage (flip-flop)
(fli fl ) in
i a shift
hif register
i represents one bi
bit
of storage, and the shifting capability of a register
permits the movement of data from stage to stage
within the register, or into or out of the register upon
application of clock pulses.
 Shift Registers
ƒ Basic data movement in shift registers (four bits are used for
illustration).

Data in Data out Data out Data in

(a) Serial in/shift right/serial out (b) Serial in/shift left/serial out

Data in Data in
Data in
Data out
Data out
(c) Parallel in/serial out (d) Serial in/parallel out

Data out
(e) Parallel in /
(g) Rotate left parallel out
(f) Rotate right
 Serial In/Serial Out Shift Registers
ƒ Accepts data serially – one bit at a time – and also produces
output serially.

Serial
S i l data
d t Q0 Q1 Q2 Q3 Serial
S i l data
d t
D Q D Q D Q D Q
input output
C C C C

CLK
 Serial In/Serial Out Shift Registers
ƒ Application: Serial transfer of data from one register to
another.

SI SO SI SO
Shift register A Shift register B

Clock CP
Shift control

Clock

Shift Wordtime
control

CP
T1 T2 T3 T4
 P ll l In/Serial
Parallel I /S i l Out
O t Shift R
Registers
gi t

ƒ Bits are entered simultaneously, but output is serial.

Data input

D0 D1 D2 D3
SHIFT/LOAD

Serial
D Q D Q D Q D Q data
Q0 Q1 Q2 Q3 out
C C C C

CLK

SHIFT.Q0 + SHIFT'.D1
 P ll l In/Serial
Parallel I /S i l Out
O t Shift R
Registers
gi t

ƒ Bits are entered simultaneously, but output is serial.

Data in

D0 D1 D2 D3

SHIFT/LOAD SRG 4
Serial data out
CLK C

Logic
g symbol
y
 P ll l In/Parallel
Parallel I /P ll l Out
O t Shift R
Registers
gi t

ƒ Simultaneous input and output of all data bits.

Parallel data inputs

D0 D1 D2 D3

D Q D Q D Q D Q
C C C C

CLK

Q0 Q1 Q2 Q3

Parallel data outputs