INFORME FINAL

Curso: Diseo Digital

Tema: Estilo algortmico para el diseo e

implementacin de circuitos combinacionales y
secuenciales.

Apellidos y nombres:

Herrera Castro, Angelo

Marco

Cdigo:

11190012

1. Implemente un contador con ENABLE y CLEAR que cuente de

0 a 5.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity c_5 is
port
(clk: in std_logic;
enable, clear: in std_logic;
q: buffer std_logic_vector(2 downto 0));
end c_5;
architecture solucion of c_5 is
begin
Process(clk,clear)
begin
if rising_edge(clk) then
q <= q+1;
if q = "101" then
q <= "000";
end if;
end if;
end process;
end solucion;

2. Implemente un contador con ENABLE y CLEAR que cuente de

4,7,0,1,5, 4,7,0,1,5,.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity c_x is
port( clk: in std_logic;
q: out std_logic_vector(2 downto 0));
end c_x;
architecture solucion of c_x is
signal c: std_logic_vector(2 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
c<=c+1;
if c=4 then
c<="000";
end if;
end if;
end process;
with c select q <=
"100" when "000",
"111" when "001",
"000" when "010",
"001" when "011",
"101" when others;
end solucion;

3. Implemente un divisor de frecuencia programable:

Selector
Fo
00 Fi / 2
01
Fi / 4
10
Fi / 8
11
Fi / 32
Donde:
Fi: frecuencia de entrada.
Fo: frecuencia de salida.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity div_prog is
Port( clk: in std_logic;
sel : in std_logic_vector(1 downto 0);
z :out std_logic);
end div_prog;
architecture solucion of div_prog is
signal c: std_logic_vector(5 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
c <= c +1;
if sel = "00" then
if c <2 then
z<= '0';
elsif c = 2 then
z<= '1';
c<= (others =>'0');
end if;
elsif sel = "01" then
if c <4 then
z<= '0';
elsif c = 4 then
z<= '1';
c<= (others =>'0');
end if;
elsif sel = "10" then
if c <8 then
z<= '0';
elsif c = 8 then
z<= '1';

c<= (others =>'0');

end if;
elsif sel = "11" then
if c <32 then
z<= '0';
elsif c = 32 then
z<= '1';
c<= (others =>'0');
end if;
end if;
end IF;
end process;
end solucion;

4. Implemente un contador con control de cuenta UP/DOWN de

mdulo 8.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity c_u_d is
port( clk: in std_logic;
up: in std_logic;
down: in std_logic;
q: buffer std_logic_vector(3 downto 0));
end c_u_d;
architecture solucion of c_u_d is
begin
process(clk,up,down)
begin
if rising_edge(clk) then
if up='1' then
q<=q+1;
if down='1' then
q<=q-1;
if q="1000" then
q<="0000";
end if;
end if;
end if;
end if;
end process;
end solucion;

5. Implemente el siguiente circuito:

Donde: f
Donde la seal Y varia de frecuencia de manera
peridica. As tenemos que durante 100ms genera una
seal de 100KHz y durante el otro 100ms genera otra
frecuencia de 300KHz, repitindose de esta manera.

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity pwm3 is
port( clk: in std_logic;
z: buffer std_logic);
end pwm3;
architecture solucion of pwm3 is
signal p : std_logic;
signal c1, c2, c3: std_logic_vector(25 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
c1<=c1+1;
if c1=2499999 then
p<= not p;
c1<=(others=>'0');
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
if p='0' then
c2<=c2+1;
if c2=499 then
y<= not y;
c2<=(others=>'0');
end if;
elsif p='1' then
c3<=c3+1;
if c3=166 then
y<=not y;
c3<=(others=>'0');
end if;
end if;
end if;
end process;
end solucion;