ANAND INSTITUTE OF HIGHER TECHNOLOGY Chennai-603 103

DEPARTMENT OF ELECTRONICS AND INSTRUMENTATION ENGINEERING

CS2071 COMPUTER ARCHITECTURE
Faculty Name: C.MAGESHKUMAR

Class: IV EIE A&B Semester: VII

UNIT II ARITHMETIC/LOGIC UNIT

Page no.
2
2
2
2
2
2
2
2

CONTENT
I.

Number Representation
1.
2.
3.
4.
5.
6.

II.

Positional Number Systems

Digit Sets and Encodings
Number-Radix Conversion
Signed Integers
Fixed-Point Numbers
Floating-Point Numbers

Design of Adders and design of simple ALUs

3
3
3
4
5
5
5
6

7. Simple Adders
8. Carry Propagation Networks
Design of ripple carry adder
Design of Carry Lookahead Adders
9. Counting and Incrementation
10. Design of Fast Adders
11. Logic and Shift Operations
12. Multifunction ALUs
III.

Design of Multipliers and Dividers

8
8
8
8
8
9
9
10
11

13. Shift-Add Multiplication

Design of combinational multiplier
14. Booths algorithm
Combinational multiplier with carry save addition
15. Hardware Multipliers
16. Programmed Multiplication
17. Shift-Subtract Division
18. Hardware Dividers
19. Programmed Division
IV.
20.
21.
22.
23.
24.

Design of Floating-Point Arithmetic

11

Rounding Modes
Special Values and Exceptions
Floating-Point Addition
Other Floating-Point Operations
Floating-Point Instructions

11
11
11
13
14

REFER FROM PAGE NO. 31 TO 77 IN XEROX)

(REFER PAGE NO. 157 - 233 IN TEXT BOOK B.PARHAMI)
1

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CS2071_Computer Architecture

I. NUMBER REPRESENTATION

REFER FROM PAGE NO. 31 TO 51 IN XEROX)

1. Positional Number Systems

Fixed-radix positional representation with k digits
Value of a number: x = (xk1xk2 . . . x1x0)r = S xi r i
For example:

Representation Range and Overflow

Overflow region max

max Overflow region

Numbers smaller
than max

Numbers larger
than max
Finite set of representable numbers

Overflow regions in finite number representation systems. For unsigned representations, max = 0.
Conventional and unconventional digit sets
Decimal digits in [0, 9]; 4-bit BCD, 8-bit ASCII
Hexadecimal, or hex: digits 0-9 & a-f
Conventional ternary digit set in [0, 2]
Conventional digit set for radix r is [0, r 1]
Symmetric ternary digit set in [1, 1]
Conventional binary digit set in [0, 1]
Redundant digit set [0, 2], encoded in 2 bits
( 0 2 1 1 0 )two and ( 1 0 1 0 2 )two represent 22
2.
3.
4.

Digit Sets and Encodings

Number-Radix Conversion
Signed Integers
We dealt with representing the natural numbers

Signed or directed whole numbers = integers

{ . . . , -3, -2, -1, 0, 1, 2, 3, . . . }
Signed-magnitude representation
+27 in 8-bit signed-magnitude binary code 0 0011011
27 in 8-bit signed-magnitude binary code 1 0011011
27 in 2-digit decimal code with BCD digits
1 0010 0111
Biased representation
Represent the interval of numbers [-N, P] by the unsigned
interval [0, P + N]; i.e., by adding N to every number
5. Fixed-Point Numbers
6. Floating-Point Numbers

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II. DESIGN OF ADDERS AND DESIGN OF SIMPLE ALUS

7. Simple Adders, serial adder, parallel adder REFER FROM PAGE NO. 52 TO 56 IN XEROX)
8. Carry Propagation Networks REFER FROM PAGE NO. 52 TO 57 IN XEROX)
x31

y31

c32

x1
c31

FA

. . .

y1

x0

c2

y0

c1

c0

FA

FA

s1

s0

cout
s31

cin

Ripple-carry binary adder with 32-bit inputs and output

Design of Ripple Carry Adders:
Arithmetic operations like addition, subtraction, multiplication, division are basic operations to be
implemented in digital computers using basic gates like AND, OR, NOR, NAND etc. Among all the arithmetic
operations if we can implement addition then it is easy to perform multiplication (by repeated addition), subtraction
(by negating one operand) or division (repeated subtraction).
Half Adders can be used to add two one bit binary numbers. It is also possible to create a logical circuit using
multiple full adders to add N-bit binary numbers.Each full adder inputs a Cin, which is the Cout of the previous
adder. This kind of adder is a Ripple Carry Adder, since each carry bit "ripples" to the next full adder. The first (and
only the first) full adder may be replaced by a half adder.The block diagram of 4-bit Ripple Carry Adder is shown here
below -

The layout of ripple carry adder is simple, which allows for fast design time; however, the ripple carry adder is
relatively slow, since each full adder must wait for the carry bit to be calculated from the previous full adder. The gate
delay can easily be calculated by inspection of the full adder circuit. Each full adder requires three levels of logic.In a
32-bit [ripple carry] adder, there are 32 full adders, so the critical path (worst case) delay is 31 * 2(for carry
propagation) + 3(for sum) = 65 gate delays.
Design Issues:
The corresponding boolean expressions are given here to construct a ripple carry adder. In the half adder circuit the
sum and carry bits are defined as
sum = A B
carry = AB
In the full adder circuit the the Sum and Carry outpur is defined by inputs A, B and Carryin as
Sum=ABC + ABC + ABC + ABC
Carry=ABC + ABC + ABC + ABC
Having these we could design the circuit. But, we first check to see if there are any logically equivalent statements that
would lead to a more structured equivalent circuit.
With a little algebraic manipulation,
Sum= ABC + ABC + ABC + ABC
= (AB + AB) C + (AB + AB) C
= (A B) C + (A B) C =A B C
Carry= ABC + ABC + ABC + ABC

= AB + (AB + AB) C

= AB + (A B) C

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CS2071_Computer Architecture

gi pi

Carry is:

0
0
1
1

annihilated or killed
propagated
generated
(impossible)

0
1
0
1

g k1 p k1

xi

g k2 p k2

g i+1 p i+1

yi

gi

pi

...

...

g1 p1

g0 p0

c0

Carry network
ck

c k1

...
c k2

ci

...
c1

c i+1

c0

si

Carry Propagation Networks -- The main part of an adder is the carry network. The rest is just a set of gates
to produce the g and p signals and the sum bits.
DESIGN OF CARRY LOOKAHEAD ADDERS :
To reduce the computation time, there are faster ways to add two binary numbers by using carry lookahead
adders. They work by creating two signals P and G known to be Carry Propagator and Carry Generator. The carry
propagator is propagated to the next level whereas the carry generator is used to generate the output carry ,
regardless of input carry. The block diagram of a 4-bit Carry Lookahead Adder is shown here below -

The number of gate levels for the carry propagation can be found from the circuit of full adder. The signal from input
carry Cin to output carry Cout requires an AND gate and an OR gate, which constitutes two gate levels. So if there are
four full adders in the parallel adder, the output carry C5 would have 2 X 4 = 8 gate levels from C1 to C5. For an n-bit
parallel adderr, there are 2n gate levels to propagate through.
Design Issues :
The corresponding boolean expressions are given here to construct a carry lookahead adder. In the carry-lookahead
circuit we ned to generate the two signals carry propagator(P) and carry generator(G),
Pi = Ai Bi
Gi = Ai Bi
The output sum and carry can be expressed as
Sumi = Pi Ci and Ci+1 = Gi + ( Pi Ci)
Having these we could design the circuit. We can now write the Boolean function for the carry output of each stage
and substitute for each Ci its value from the previous equations:
C1 = G0 + P0 C0
C2 = G1 + P1 C1 = G1 + P1 G0 + P1 P0 C0
C3 = G2 + P2 C2 = G2 P2 G1 + P2 P1 G0 + P2 P1 P0 C0
C4 = G3 + P3 C3 = G3 P3 G2 P3 P2 G1 + P3 P2 P1 G0 + P3 P2 P1 P0 C0
4

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Third Carry Speed-Up Method: Carry Select -- Allows doubling of adder width with a single-mux additional
x
y
delay
[a, b]
[a, b]

c out

Adder

c in

c out

Version 0
of sum bits

Adder

c in

Version 1
of sum bits
a

[a, b]

9. Counting and Incrementation (Refer page no. 183 - 185 in text book B.Parhami)
k
/

Data in
IncrInit

k
/

k
/

Count
register
D

k
/

c in

_
C

Adder /
k

Update
a
(Increment
amount)

c out

DESIGN OF REGISTERS AND COUNTERS :

In a sequential circuit the present output is determined by both the present input and the past output. In order
to receive the past output some kind of memory element can be used. The memory element commonly used in the
sequential circuits are time-delay devices. The block diagram of the sequential circuit-

A circuit with flip-flops is considered a sequential circuit even in the absence of combinational logic. Circuits that
include flip-flops are usually classified by the function they perform. Two such circuits are registers and counters:
1. Register is a group of flip-flops. Its basic function is to hold information within a digital system so as to make it
available to the logic units during the computing process.
2. Counter is essentially a register that goes through a predetermined sequence of states.
There are various different kind of Flip-Flops. Some of the common flip-flops are: R-S Flip-Flop, D FlipFlop, J-K Flip-Flop, T Flip-Flop. The block diagram of different flip-flops are shown here -

1. RS flipflop If R is high then reset state occurs and when S=1 set state.the both cannot be high simultaneouly.
this input combination is avoided.
2. JK flipflop If J and K are both low then no change occurs. If J and K are both high at the clock edge then the
output will toggle from one state to the other
3. D flipflop The D flip-flop tracks the input, making transitions with match those of the input D.
4. Tflipflop The T or "toggle" flip-flop changes its output on each clock edge,
5

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Design Issues:
The four different types of flip-flops are supplied here. One can easily build any register or counter using those flipflop and different logic gates. But the automatic clock input is under development, so to build any registers or counters
user can use the manual clock or Dip Switch which toggles on double click over the component.
10.
11.

Design of Fast Adders

LOGIC AND SHIFT OPERATIONS ((Refer page no. 188 to 190 in text book B.Parhami))
Right-shifted
values

Left-shifted
values
00...0, x[31]

RightLeft
Shift amount

00, x[30, 2]
0, x[31, 1]
x[31, 0]

32

32 32

x[30, 0], 0
x[31, 0]

. . .

x[0], 00...0
x[1, 0], 00...0

32

32

31

32

32

. . .

33

32
62

32
63

Multiplexer

32

6-bit code specifying

shift direction & amount

ARITHMETIC SHIFTS
Purpose: Multiplication and division by powers of 2
sra $t0,$s1,2
# $t0 ($s1) right-shifted by 2
srav $t0,$s1,$s0
# $t0 ($s1) right-shifted by ($s0)
31

op

25

31

op

rt

15

rd

10

sh

fn

Unused

25

rs

Source
register

20

rt

Destination
register

15

rd

Shift
amount

10

sh

sra = 3

fn

0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1
ALU
instruction

12.

20

0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 0 1 0 0 0 0 0 1 1
ALU
instruction

rs

Amount
register

Source
register

Destination
register

Unused

srav = 7

MULTIFUNCTION ALUS

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CS2071_Computer Architecture

ConstVar

Shift function

Constant
5
amount

Amount

Variable
amount

00
01
10
11

No shift
Logical left
Logical right
Arith right

Shifter

Function
class

32
5 LSBs

00
01
10
11

Shift
Set less
Arithmetic
Logic

Shifted y
0

Adder
y

0 or 1

c0

32

32

k
/

c 31

xy

MSB

32

32

Shorthand
symbol
for ALU

Control

c 32

x
Func

AddSub

s
ALU

AND
OR
XOR
NOR

00
01
10
11

Ovfl

32input
NOR

Logic
unit

Zero

Logic function

Zero

Ovfl

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III.

DESIGN OF MULTIPLIERS AND DIVIDERS (Refer page no. 197 - 214 in text book B.Parhami)

13. SHIFT-ADD MULTIPLICATION for examples refer page no. 199 in text book b.parhami
Multiplicand
Multiplier

x
y

Partial
products
bit-matrix

y0
y
1
y2
y3

Product

x
x
x
x

20
21
22
23

DESIGN OF COMBINATIONAL MULTIPLIER:

Combinational Multipliers do multiplication of two unsigned binary numbers. Each bit of the multiplier is
multiplied against the multiplicand, the product is aligned according to the position of the bit within the multiplier, and
the resulting products are then summed to form the final result. Main advantage of binary multiplication is that the
generation of intermediate products is simple: if the multiplier bit is a 1, the product is an appropriately shifted copy of
the multiplicand; if the multiplier bit is a 0, the product is simply 0.
The design of a combinational multiplier to multiply two 4-bit binary number is illustrated below: If two n-bit
numbers are multiplied then the output will be less than or equals to 2n bits.

14.

BOOTHS ALGORITHM REFER PAGE NO. 61 70 IN XEROX

14.1 COMBINATIONAL MULTIPLIER WITH CARRY SAVE ADDITION PAGE NO. 70 IN XEROX
15.

HARDWARE MULTIPLIERS ALSO REFER PAGE NO. 59 IN XEROX

Shift
Multiplier y
Doublewidth partial product z (j)
Shift
Multiplicand x

Mux

yj

Enable
Select

c out

Adder

c in

AddSub

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CS2071_Computer Architecture

TREE MULTIPLIERS

ARRAY MULTIPLIER:

x3 0
0

x2 0
0

x1 0
0

x0 0

MA

MA

MA

MA

MA

MA

MA

MA

MA

MA

MA

MA

MA

MA

MA

MA

FA

FA

FA

HA

z7

z6

z5

y0

0
y1

z0

Our original
dot-notation
representing
multiplication

0
y2

z1

0
y3

z2

0
z3

16.

Straightened
dots to depict
array multiplier
to the left

z4

PROGRAMMED MULTIPLICATION

MINIMIPS INSTRUCTIONS RELATED TO MULTIPLICATION

mult $s0,$s1
# set Hi,Lo to ($s0)($s1); signed
multu $s2,$s3
# set Hi,Lo to ($s2)($s3); unsigned
mfhi $t0
# set $t0 to (Hi)
mflo $t1
# set $t1 to (Lo)
17.

SHIFT-SUBTRACT DIVISION. for examples refer page no. 208 in text book B.PARHAMI
x

Divisor

Subtracted
bit-matrix

Quotient

z
Dividend
y 3 x 23
y 2 x 22
y 1 x 21
y 0 x 20
s

Remainder

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CS2071_Computer Architecture

SIGNED DIVISION:
Method 1 (indirect): strip operand signs, divide, set result signs
Dividend
z=5
z=5
z = 5
z = 5

Divisor
x=3
x = 3
x=3
x = 3

Quotient
y=1
y = 1
y = 1
y=1

Remainder
s=2
s=2
s = 2
s = 2

Method 2 (direct 2s complement): develop quotient with digits 1 and 1, chosen based on signs, convert to digits 0
and 1
Restoring division: perform trial subtraction, choose 0 for q digit if partial remainder negative
Nonrestoring division: if sign of partial remainder is correct, then subtract (choose 1 for q digit) else add (choose 1)
18.

HARDWARE DIVIDERS
Shift

yk j

Quotient y
Partial remainder z (j) (initially z)

Load

Shift
Quotient
digit
selector

Divisor x
Enable

0 Mux 1

Select

c out

Adder

c in

1
(Always
subtract)

Trial difference

ARRAY DIVIDERS:

z7

y3

x3

z6

MS

x2

x1
z5

MS

x0
z4

MS

MS

z3
0

z2

y2
MS

MS

MS

MS

z1

y1
MS

MS

MS

MS

Our original
dot-notation
for division

z0

y0
MS

s3

MS

s2

MS

s1

MS

0
Straightened
dots to depict
an array divider

s0

10

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CS2071_Computer Architecture

19.

PROGRAMMED DIVISION

MiniMIPS instructions related to division

div $s0,$s1
# Lo = quotient, Hi = remainder
divu $s2,$s3
# unsigned version of division
mfhi $t0
# set $t0 to (Hi)
mflo $t1
# set $t1 to (Lo)
IV.

DESIGN OF FLOATING-POINT ARITHMETIC

20. ROUNDING MODES

max

Negative numbers
FLP

Sparser

min

Denser

Overflow
region

min +

Positive numbers
FLP +

Denser

Sparser

Underflow
regions
Midway
example

max +

Overflow
region

Underflow
example

Typical
example

Overflow
example

Distribution of floating-point numbers on the real line.

21. SPECIAL VALUES AND EXCEPTIONS

Zeros, infinities, and NaNs (not a number)
0
Biased exponent = 0, significand = 0 (no hidden 1)

Biased exponent = 255 (short) or 2047 (long), significand = 0
NaN
Arithmetic operations with special operands
(+0) + (+0) = (+0) (0) = +0;
(+0) * (+5) = +0
(+0) / (5) = 0; (+) + (+) = +
x (+) = ;
(+) * x = , depending on the sign of x
x / (+) = 0, depending on the sign of x
(+) = +
22. FLOATING-POINT ADDITION

11

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HARDWARE FOR FLOATING-POINT ADDITION

Input 1

Input 2
Unpack

Signs Exponents

Significands

AddSub
Mu x

Sub

Possible swap
& complement
Align
significands

Control
& sign
logic

Add
Normalize
& round

Sign

Exponent

Significand

Pack
Output

12

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CS2071_Computer Architecture

23. Other Floating-Point Operations

Floating-point multiplication
(2e1s1) (2e2s2) = 2e1+ e2(s1 s2)
Product of significands in [1, 4)
If product is in [2, 4), halve to normalize (increment exponent)
Floating-point division
(2e1s1) / (2e2s2) = 2e1 e2(s1 / s2)
Ratio of significands in (1/2, 2)
If ratio is in (1/2, 1), double to normalize (decrement exponent)
Floating-point square-rooting
(2es)1/2 = 2e/2(s)1/2
when e is even
= 2(e1)2(2s)1/2
when e is odd
Normalization not needed
Hardware for Floating-Point Multiplication and Division

Input 1

Input 2
Unpack

Signs Exponents

Significands

MulDiv

Multiply
or divide

Control
& sign
logic

Normalize
& round

Sign

Exponent

Significand

Pack
Output

13

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CS2071_Computer Architecture

24. FLOATING-POINT INSTRUCTIONS

FLOATING-POINT ARITHMETIC INSTRUCTIONS FOR MINIMIPS:
add.s $f0,$f8,$f10 # set $f0 to ($f8) +fp ($f10)
sub.d $f0,$f8,$f10 # set $f0 to ($f8) fp ($f10)
mul.d $f0,$f8,$f10
# set $f0 to ($f8) fp ($f10)
div.s $f0,$f8,$f10 # set $f0 to ($f8) /fp ($f10)
neg.s $f0,$f8
# set $f0 to ($f8)
op

31

ex

25

ft

20

15

fs

fd

10

fn

0 1 0 0 0 1 0 0 0 0 x 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 x x x
Floating-point
instruction

s=0
d=1

Source
register 2

Source
register 1

Destination
register

add.* = 0
sub.* = 1
mul.* = 2
div.* = 3
neg.* = 7

MINIMIPS INSTRUCTIONS FOR NUMBER FORMAT CONVERSION:

cvt.s.w $f0,$f8
# set $f0 to single(integer $f8)
cvt.d.w $f0,$f8
# set $f0 to double(integer $f8)
cvt.d.s $f0,$f8
# set $f0 to double($f8)
cvt.s.d $f0,$f8
# set $f0 to single($f8,$f9)
cvt.w.s $f0,$f8
# set $f0 to integer($f8)
cvt.w.d $f0,$f8
# set $f0 to integer($f8,$f9)
op

31

ex

25

ft

20

fs

15

10

fd

fn

0 1 0 0 0 1 0 0 0 0 x 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 x x x
Floating-point
instruction

*.w = 0
w.s = 0
w.d = 1
*.* = 1

Unused

Source
register

Destination
register

To format:
s = 32
d = 33
w = 36

MINIMIPS INSTRUCTIONS FOR FLOATING-POINT LOAD, STORE, AND MOVE:

lwc1 $f8,40($s3) # load mem[40+($s3)] into $f8
swc1 $f8,A($s3) # store ($f8) into mem[A+($s3)]
mov.s $f0,$f8
# load $f0 with ($f8)
mov.d $f0,$f8
# load $f0,$f1 with ($f8,$f9)
mfc1 $t0,$f12
# load $t0 with ($f12)
mtc1 $f8,$t4
# load $f8 with ($t4)
31

op

25

ft

20

fs

15

fd

10

fn

0 1 0 0 0 1 0 0 0 0 x 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0
Floating-point
instruction

31

ex

op

rs

25

s=0
d=1

20

rt

Unused

15

rd

Source
register

sh

10

Destination
register

fn

mov.* = 6

0 1 0 0 0 1 0 0 x 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Floating-point
instruction

mfc1 = 0
mtc1 = 4

Source
register

Destination
register

Unused

Unused

MINIMIPS INSTRUCTIONS FOR FLOATING-POINT LOAD, STORE, AND MOVE:

bc1t L
# branch on fp flag true
bc1f L
# branch on fp flag false
c.eq.* $f0,$f8
# if ($f0)=($f8), set flag to true
c.lt.* $f0,$f8
# if ($f0)<($f8), set flag to true
c.le.* $f0,$f8
# if ($f0)($f8), set flag to true

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31

op

25

ft

20

15

fs

10

fd

fn

0 1 0 0 0 1 0 0 0 0 x 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0
Floating-point
instruction

31

ex

op

s=0
d=1

25

rs

Source
register 2

20

rt

Source
register 1

15

Unused

operand / offset

c.eq.* = 50
c.lt.* = 60
c.le.* = 62
0

0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 x 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1
Floating-point
instruction

bc1? = 8

true = 1
false = 0

Offset

15

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CS2071_Computer Architecture