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ANINTRODUCTIONTOINTERRUPTS
INTERRUPTS
There are two main types of interrupt in the 8086 microprocessor, internal and external
hardware interrupts. Hardware interrupts occur when a peripheral device asserts an interrupt
input pin of the microprocessor. Whereas internal interrupts are initiated by the state of the
CPU(e.g.dividebyzeroerror)orbyaninstruction.
Providedtheinterruptispermitted,itwillbeacknowledgedbytheprocessorattheendofthe
current memory cycle. The processor then services the interrupt by branching to a special
service routine written to handle that particular interrupt. Upon servicing the device, the
processoristheninstructedtocontinuewithwhatiswasdoingpreviouslybyuseofthe"return
frominterrupt"instruction.
Thestatusoftheprogrammebeingexecutedmustfirstbesaved.Theprocessorsregisterswill
besavedonthestack,or,atveryleast,theprogrammecounterwillbesaved.Preservingthose
registerswhicharenotsavedwillbetheresponsibilityoftheinterruptserviceroutine.Oncethe
programme counter has been saved, the processor will branch to the address of the service
routine.
EdgeorLevelsensitiveInterrupts
Edgelevelinterruptsarerecognisedonthefallingorrisingedgeoftheinputsignal.Theyare
generallyusedforhighpriorityinterruptsandarelatchedinternallyinsidetheprocessor.Ifthis
latching was not done, the processor could easily miss the falling edge (due to its short
duration)andthusnotrespondtotheinterruptrequest.
Levelsensitiveinterruptsovercometheproblemoflatching,inthattherequestingdeviceholds
theinterruptlineataspecifiedlogicstate(normallylogiczero)tilltheprocessoracknowledges
theinterrupt.Thistypeofinterruptcanbesharedbyotherdevicesinawired'OR'configuration,
whichiscommonlyusedtosupportdaisychainingandothertechniques.
MaskableInterrupts
Theprocessorcaninhibitcertaintypesofinterruptsbyuseofaspecialinterruptmaskbit.This
maskbitispartoftheflags/conditioncoderegister,oraspecialinterruptregister.Inthe8086
microprocessor if this bit is clear, and an interrupt request occurs on the Interrupt Request
input,itisignored.
NonMaskableInterrupts
Therearesomeinterruptswhichcannotbemaskedoutorignoredbytheprocessor.Theseare
associatedwithhighprioritytaskswhichcannotbeignored(likememoryparityorbusfaults).In
general, most processors support the NonMaskable Interrupt (NMI). This interrupt has
absolute priority, and when it occurs, the processor will finish the current memory cycle, then
branchtoaspecialroutinewrittentohandletheinterruptrequest.
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AdvantagesofInterrupts
Interruptsareusedtoensureadequateserviceresponsetimesbytheprocessing.Sometimes,
withsoftwarepollingroutines,servicetimesbytheprocessorcannotbeguaranteed,anddata
maybelost.Theuseofinterruptsguaranteesthattheprocessorwillservicetherequestwithin
aspecifiedtimeperiod,reducingthelikelihoodoflostdata.
InterruptLatency
ThetimeintervalfromwhentheinterruptisfirstassertedtothetimetheCPUrecognisesit.This
will depend much upon whether interrupts are disabled, prioritized and what the processor is
currently executing. At times, a processor might ignore requests whilst executing some
indivisible instruction stream (readwritemodify cycle). The figure that matters most is the
longestpossibleinterruptlatencytime.
InterruptResponseTime
The time interval between the CPU recognising the interrupt to the time when the first
instruction of the interrupt service routine is executed. This is determined by the processor
architectureandclockspeed.

TheOperationofanInterruptsequenceonthe8086
Microprocessor:
1.Externalinterfacesendsaninterruptsignal,totheInterruptRequest(INTR)pin,oran
internalinterruptoccurs.
2.TheCPUfinishesthepresentinstruction(forahardwareinterrupt)andsendsInterrupt
Acknowledge(INTA)tohardwareinterface.
3.TheinterrupttypeNissenttotheCentralProcessorUnit(CPU)viatheDatabusfromthe
hardwareinterface.
4.Thecontentsoftheflagregistersarepushedontothestack.
5.Boththeinterrupt(IF)and(TF)flagsarecleared.ThisdisablestheINTRpinandthetrapor
singlestepfeature.
6.Thecontentsofthecodesegmentregister(CS)arepushedontotheStack.
7.Thecontentsoftheinstructionpointer(IP)arepushedontotheStack.
8.Theinterruptvectorcontentsarefetched,from(4xN)andthenplacedintotheIPandfrom
(4xN+2)intotheCSsothatthenextinstructionexecutesattheinterruptserviceprocedure
addressedbytheinterruptvector.
9.WhilereturningfromtheinterruptserviceroutinebytheInterruptReturn(IRET)instruction,
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theIP,CSandFlagregistersarepoppedfromtheStackandreturntotheirstatepriortothe
interrupt.

MultipleInterrupts
Ifmorethanonedeviceisconnectedtotheinterruptline,theprocessorneedstoknowtowhich
device service routine it should branch to. The identification of the device requesting service
canbedoneineitherhardwareorsoftware,oracombinationofboth.Thethreemainmethods
are:
1. SoftwarePolling,
2. HardwarePolling,(DaisyChain),
3. HardwareIdentification(VectoredInterrupts).

SoftwarePollingDeterminationoftheRequestingDevice
Asoftwareroutineisusedtoidentifythedevicerequestingservice.Asimplepollingtechnique
isused,eachdeviceischeckedtoseeifitwastheoneneedingservice.

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Havingidentifiedthedevice,theprocessorthenbranchestotheappropriateinterrupthandling
routine address for the given device. The order in which the devices appear in the polling
sequencedeterminestheirpriority.

SummaryofSoftwarePolledI/O
PollingisthemostcommonandsimplestmethodofI/Ocontrol.Itrequiresnospecialhardware
and all I/O transfers are controlled by the CPU programme. Polling is a synchronous
mechanism,bywhichdevicesareservicedinsequentialorder.
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Thepollingtechnique,however,haslimitations.
1)itiswastefuloftheprocessorstime,asitneedlesslychecksthestatusofalldevicesallthe
time,
2)itisinherentlyslow,asitchecksthestatusofallI/Odevicesbeforeitcomesbacktocheck
anygivenoneagain,
3) when fast devices are connected to a system, polling may simply not be fast enough to
satisfytheminimumservicerequirements,
4) priority of the device is determined by the order in the polling loop, but it is possible to
changeitviasoftware.

Software/HardwareDrivenIdentification(DaisyChain)
Thisissignificantlyfasterthanapuresoftwareapproach.Adaisychainisusedtoidentifythe
devicerequestingservice.

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DaisyChainPollingArangement

Daisy chaining is used for level sensitive interrupts, which act like a wired 'OR' gate. Any
requestingdevicecantaketheinterruptlinelow,andkeepitassertedlowuntilitisserviced.
Because more than one device can assert the shared interrupt line simultaneously, some
method must be employed to ensure device priority. This is done using the interrupt
acknowledgesignalgeneratedbytheprocessorinresponsetoaninterruptrequest.
Eachdeviceisconnectedtothesameinterruptrequestline,buttheinterruptacknowledgeline
ispassedthrougheachdevice,fromthehighestprioritydevicefirst,tothelowestprioritydevice
last.
Afterpreservingtherequiredregisters,themicroprocessorgeneratesaninterruptacknowledge
signal. This is gated through each device. If device 1 generated the interrupt, it will place its
identificationsignalonthedatabus,whichisreadbytheprocessor,andusedtogeneratethe
addressoftheinterruptserviceroutine.Ifdevice1didnotrequesttheservicing,itwillpassthe
interrupt acknowledge signal on to the next device in the chain. Device 2 follows the same
procedure,andsoon.

HardwareIdentification(VectoredInterrupts)
Thisisthefastestsystem.Theonusisplacedontherequestingdevicetorequesttheinterrupt,
andidentifyitself.Theidentitycouldbeabranchingaddressforthedesiredinterrupthandling
routine.
If the device just supplies an identification number, this can be used in conjunction with a
lookup table to determine the address of the required service routine. Response time is best
whenthedevicerequestingservicealsosuppliesabranchingaddress.

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PriorityInterruptManagementController
Priority Interrupt Controller Chips (PIC's) are hardware chips designed to make the task of a
devicepresentingitsownaddresstotheCPUsimple.ThePICalsoassessesthepriorityofthe
devices connected to it. Modern PIC's can also be programmed to prevent the generation of
interruptswhicharelowerthanadesiredlevel.
Thedecodedlocationisconnectedtotheoutputofapriorityencoder.Theinputofthepriority
encoder is connected to each device. When a device requests service, the priority encoder
presentsaspecialcodecombination(uniqueforeachdevice)tothedecodedmemorylocation.
Theportthusholdsthevalueoraddressassociatedwiththehighestdevicerequestingservice.
The priority encoder arranges all devices in a list, devices given a lower priority are serviced
when no other higher priority devices need servicing. This simplifies the software required to
determinethedevice,resultinginanincreaseinspeed.
Thedisadvantagesare:
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1)theextrachiprequired,
2)resultantincreasesincost,
3)moreboardspaceandpowerconsumption,
4)fixedpriorityinhardware.

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