DNSK1

A wind turbine with a diameter of 100 ft operates during a 24-h period in

which the wind velocity may be approximated by half a sine wave as V(
)=V_m*sin(

/24), where

is time in hours and V_m=10^5 ft/h. The

wind density is 0.076 lb_m/ft^3. Calculate (a) the theoretical maximum

turbine energy during that 24-h period, in foot pound force and kilowatt
hours, and (b) the wind mean energy velocity, in feet per hour.
answer to (a) should be 1627 kW*hr and (b) 75,150 ft/hr
Please show work and how to obtain answer, thanks!

DNSK2
Consider the following state machine description that is very similar to
the room control state machine from the practice exam for midterm 2
(changes have been made apparent):
A room has a capacity of four people. It has an exit door and an entry
door. Two outputs indicate whether the door is open (1) or closed (0) for
each of the doors. There is an additional output that will turn on/off the
lights. No one can enter at the exit door or leave through the entry door.
The entry door will lock itself if there are already four people in the room
and remain unlocked otherwise. The exit door will lock itself if there is no
person inside the room. The lights will turn on when there is at least one
person and turn off if there is no person. Only one person can enter or
leave at the same time. At each time step, a person may
attempt to enter or not, and a person may leave, or not.

Thus, all four possible combinations of entry and exit

during one time step are potentially valid, assuming a
non-zero number of people present to exit. Each of the
doors has a sensor that will trigger an input of one, when a person
enters or leaves the room. The doors will not allow a person to change
their mind, once they start entering or exiting. The room control can
be reset to the empty state.
Tasks:
Implement the above state machine in Verilog, using the following
module interface:
module entryControl(input clock, input reset, input entered, input exited,
output entryLock, output exitLock, output lightOn);

Use the following testwrapper to drive the entryControl module in

simulation
module Top(output enL, output exL, output lit);
reg clk;
reg rst;
always
#1 clk=~clk;
initial
begin
clk=1b0;

rst=1b1;
#4
rst=1b0;
#512
$stop;
end
reg [3:0] lfsr4;
always@(posedge clk)
if(rst)
lfsr4<=4b0001;
else
begin
lfsr4[3]<=lfsr4[2];
lfsr4[2]<=lfsr4[1];
lfsr4[1]<=lfsr4[0]^lfsr4[3];
lfsr4[0]<=lfsr4[3];
end
entryControl NQ(clk, rst, (lfsr4[3]|lfsr4[2])&(enL), (lfsr4[1]|lfsr4[0])&lit,
enL, exL, lit);
endmodule

Submit a single Verilog file containing all Verilog code.

Add the following information as a comment in this file:

For each of the last 8 cycles of simulation, what are the

values of enL, exL, and lit?
DNSK3

DNSK4

Exit

Exit

DNSK5

Exit