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OUTLINE
Preliminary:
Contact Information, Preliminary Matters, Specifications,
Plasma Overview, General Troubleshooting Steps,
Disassembly Instructions, Voltage and Signal Distribution
Troubleshooting: No Main Power Switch (Vacation Switch).
Circuit Board Operation, Troubleshooting and Alignment of :
Switch Mode Power Supply No VS On command input to SMPS
Y-SUS Board Delivers Logic Signals and FG5V to lower Y-Drive board.
Y-Drive Boards (1 Upper and 1 Lower).
Lower can run separately, but you MUST remove the Upper completely.
Z-SUS Output Board (Also uses one Z-SUB board for bottom panel connector)
Control Board
X Drive Boards (3)
Main Board
Interconnect Diagram: 11X17 Foldout Section used as a quick reference sheet.
July 2010
50PJ350
Plasma
The next section will get the Technician familiar with the Disassembly, Identification
and Layout of the Plasma Display Panel.
At the end of this Section the Technician should be able to Identify the Circuit
Boards and have the ability and knowledge necessary to safely remove and
replace any Circuit Board or Assembly.
July 2010
50PJ350
Plasma
LG Contact Information
Customer Service (and Part Sales)
(800) 243-0000
(800) 847-7597
http://gsfs-america.lge.com
us.lgservice.com
Knowledgebase Website
lgtechassist.com
LG Web Training
lge.webex.com
LG CS Academy
lgcsacademy.com
http://136.166.4.200
LCD-DV: 32LG40, 32LH30, 37LH55, 42LG60, 42LG70, 42LH20, 42LH40, 42LH50, 42LH90, 42SL80,
47LG90, 47LH85, 47LE8500
PLASMA: 42PG20, 42PQ20, 42PQ30, 50PG20, 50PJ350, 50PK750, 50PS80, 50PS60, 60PK750,
60PS11, 60PS60, 60PS80
Also available on the Plasma Page:
PDP Panel Alignment Handbook, Schematics with Bookmarks
Plasma Control Board ROM Update (Jig required)
July 2010
50PJ350
Plasma
CAUTION
To avoid personal injury, disconnect the power before servicing this product. If electrical power
is required for diagnosis or test purposes, disconnect the power immediately after performing
the necessary checks. Also be aware that many household products present a weight hazard.
At least two people should be involved in the installation or servicing of such devices.
Failure to consider the weight of an product could result in physical injury.
July 2010
50PJ350
Plasma
ESD Notice
Todays sophisticated electronics are electrostatic discharge (ESD) sensitive. ESD can weaken or damage
the electronics in a manner that renders them inoperative or reduces the time until their next failure.
Connect an ESD wrist strap to a ground connection point or unpainted metal in the product. Alternatively,
you can touch your finger repeatedly to a ground connection point or unpainted metal in the product. Before
removing a replacement part from its package, touch the anti-static bag to a ground connection point or
unpainted metal in the product. Handle the electronic control assembly by its edges only. When
repackaging a failed electronic control assembly in an anti-static bag, observe these same precautions.
Regulatory Information
This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to
Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful
interference when the equipment is operated in a residential installation. This equipment generates, uses,
and can radiate radio frequency energy, and, if not installed and used in accordance with the instruction
manual, may cause harmful interference to radio communications. However, there is no guarantee that
interference will not occur in a particular installation. If this equipment does cause harmful interference to
radio or television reception, which can be determined by turning the equipment off and on, the user is
encouraged to try to correct the interference by one or more of the following measures: Reorient or relocate
the receiving antenna; Increase the separation between the equipment and the receiver; Connect the
equipment to an outlet on a different circuit than that to which the receiver is connected; or consult the
dealer or an experienced radio/TV technician for help.
July 2010
50PJ350
Plasma
Approximately 10 minute pre-run time is required before any adjustments are performed.
2.
Refer to the Voltage Sticker inside the Panel when making adjustments on the Power Supply, Y-SUS and Z-SUS Boards.
3.
Always adjust to the specified voltage level (+/- volt) unless otherwise specified.
4.
Be cautious of electric shock from the PDP module since the PDP module uses high voltage, check that the Power Supply
and Drive Circuits are completely discharged because of residual current stored before Circuit Board removal.
4.
C-MOS circuits are used extensively for processing the Drive Signals and should be protected from static electricity.
5.
The PDP Module must be carried by two people. Always carry vertical NOT horizontal.
6.
7.
Exercise care when making voltage and waveform checks to prevent costly short circuits from damaging the unit.
8.
Be cautious of lost screws and other metal objects to prevent a possible short in the circuitry.
9.
New Panels and Frames are much thinner than previous models. Be Careful with flexing these panels. Be careful
with lifting Panels from a horizontal position. Damage to the Frame mounts or panel can occur.
10. New Plasma models have much thinner cabinet assemblies and mounts.
Be extremely careful when moving the set around as damage can occur.
July 2010
50PJ350
Plasma
July 2010
50PJ350
Plasma
July 2010
50PJ350
Plasma
50PJ350 Specifications
10
July 2010
50PJ350
Plasma
TruSlim Design:
At less than 1" thick the new TruSlim Frame trims away distraction without
compromising screen size.
USB 2.0:
View videos and photos and listen to music on your TV through USB 2.0.
11
July 2010
50PJ350
Plasma
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50PJ350
Plasma
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July 2010
50PJ350
Plasma
600 Hz Sub Field Driving is achieved by using 10 sub-fields per frame process
(vs. Comp. 8 sub-field/frame)
Original Image
Sub Field firing occurs using wall charge and polarity differences between Y-SUS and Z-SUS signals.
14
July 2010
50PJ350
Plasma
BOTTOM PORTION
p/n AKB72914201
TOP PORTION
15
July 2010
50PJ350
Plasma
AC In
SIDE
INPUTS
REAR
INPUTS
USB
HDMI 3
Composite
Video/Audio
16
July 2010
50PJ350
Plasma
50PJ350 Dimensions
Power:
340W (Typical)
0.1W (Stand-By)
2-3/16"
55.88mm
46-1/8"
1170.94mm
15-3/16
385.8mm
15-3/4"
400mm
30-13/16"
782.32mm
5-1/4
133.6mm
15-3/4"
400mm
28-3/8"
721.36mm
Model No.
Serial No.
Label
Remove 4 screws
to remove stand
for wall mount
7-3/8
187.2mm
2-3/8"
60.96mm
Weight:
2-3/4"
70mm
78.5 lbs with Stand
60.8 lbs without Stand
20-7/8"
530mm
12-3/16"
309.88mm
17
July 2010
50PJ350
Plasma
DISASSEMBLY SECTION
This section of the manual will discuss Disassembly, Layout and Circuit
Board Identification, of the 50PJ350 Advanced Single Scan Plasma Display Panel.
Upon completion of this section the Technician will have a better
understanding of the disassembly procedures, the layout of the printed
circuit boards and be able to identify each board.
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July 2010
50PJ350
Plasma
19
July 2010
50PJ350
Plasma
FPC
Y-Drive Upper
FPC
FPC
Z-SUS
FPC
Power Supply
(SMPS)
Y-SUS
FPC
FPC
Y-Drive Lower
FPC
Z-SUB
Main Board
Control
FPC
TCP
Heat Sink
AC In
FPC
Left X
Center X
Right X
Side
Input
(part of
main)
Conductive Tape
Conductive Tape
IR/LED
Board
Soft Touch
Keyboard
Invisible Speakers
20
July 2010
50PJ350
Plasma
PANEL
p/n: EAJ60716304 (PDP50T10000.ADLGB)
p/n: EAJ60716316 (PDP50T10000.ASLGB)
Y-DRIVE
UPPER
Board
p/n: EBR63551601
P102
P101
P2
P812
P211
P103
P201
P110
Y-SUS
Board
P204
P202
P205
p/n: EBR63551701
P203
SC101
L N
p/n: EBR63039801
P101
P203
P212
P100
P102
P3
P813
LVDS
Z-SUB Board
CONTROL
Board P101
P301
P704
P162
P161
P801
AC
In
LEFT X
Board
p/n: EBR64062301
P121
P212
P231
p/n: EBR64062201
P210
P211
P331
CENTER X
P703
P900
n/c
MAIN
Board
p/n: EBT60953802
RIGHT X
Board
p/n: EBR64062001
P101
FRONT IR
p/n: EBR65007704
21
P7
P202
P121
p/n: EBR63549501
Y-DRIVE
LOWER
Board
P122
P102
n/c
P1
p/n: EAY60968701
P111
P101
p/n: EBR63040301
SMPS
POWER SUPPLY
Board
P210
Z-SUS
Board
July 2010
50PJ350
Plasma
Disconnect the following connectors: P210, P211, P212 and Ribbon Cable P110.
To remove P110, lift up on the locking mechanism and pull the ribbon cable out.
Remove the 16 screws holding the Y-SUS in place. Do not run the set with P117 or P118 removed.
Remove the Y-SUS board. When replacing, be sure to readjust the Va/Vs voltages in accordance with the
Panel Label.
Confirm VSC, -Vy and Z-bias as well.
Note: The Y-SUS does not come with the
Board Standoff
Y-Drive Boards Removal
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July 2010
50PJ350
Plasma
23
July 2010
50PJ350
Plasma
24
July 2010
50PJ350
Plasma
D
Left
D
Right
Warning:
Never run the TV with the
TCP Heat Sink removed
E
Heat Sink
Ground
Wire
Warning Shorting Hazard: Conductive Tape. Do not allow to touch energized circuits.
25
July 2010
50PJ350
Plasma
P121 to P212
Left to Center X
Remove tape (if present) and Gently pry the
P211 to P331
locking mechanism upward and remove the ribbon
Center to Right X
cable from the connector.
Carefully lift the TCP ribbon up and off.
It may stick, be careful not to crack TCP.
(See next page for precautions)
TCP
Gently lift the locking mechanism
upward on all TCP connectors
Left X: P101~108
Center X: P201~207
Right X: P301~308
Cushion (Chocolate)
26
Example
July 2010
50PJ350
Plasma
Tab
Tab
27
July 2010
50PJ350
Plasma
The Left X Board drives the Right 5/16 of the side of the screen vertical electrodes
The Center X Board drives the Center 3/8 of the of the screen vertical electrodes
The Right X Board drives the Left 5/16 of the side of the screen vertical electrodes
28
July 2010
50PJ350
Plasma
At the end of this Section the technician should understand the operation of each
circuit board and how to adjust the controls. The technician should be able with
confidence to troubleshoot a circuit board failure, replace the defective circuit and
perform all necessary adjustments.
29
July 2010
50PJ350
Plasma
Y Drive
Upper
FPCs
P101
Error Com
P211
FG
FG
P103
Note:
Va not used
by Y-SUS only
fused and routed
to the X-Board
Scan
P110
FPCs
P204
P110 / P204
Floating Gnd (FG)
Drive Signals, FG5V
and Vscan.
FG5V
FG15V
16V
VSC
-VY
P201
Scan
P202
SMPS
Board
M5V, Vs, Va
Y-SUS Board
FG
SK101
16V / M5V
Note: 16V not used
by Control
Y Drive
Lower
P212
Floating Gnd (FG)
Drive Signals, FG5V
X-Board-Left
3.3V
P122
P102
P103
P104
Z-SUB
Board
Stand By:
STB +5
Run:
AC Det +5, 17V
P121
P231
P212
P232
3.3V
P232
P105
P703
MAIN Board
RGB Logic
Signals
3.3V
P211
P7
P202
Speakers
3.3V
Key Board
Pull Up
P704
P801
3.3V
STBY
P3
FPCs
P301
IR,
Intelligent Sensor
P100
P101
X-Board-Right
P331
Va
Va
P101
M5V, Va, Vs
P162
RGB Logic
Signals
P2
3.3V
Va
P101
CONTROL
Board P101
P114
Z-SUS
Board
P102
P121
P111
P101
M_On
Vs
LVDS Video
Display Enable
P161
P205
P813
SMPS
Turn On
Commands
RL_ON
AC
Input
Filter
Logic Signals
To Y-SUS and Y-Drive
FG
P203
FPCs
P812
P210
P102
Display Panel
Horizontal
Electrodes
Sustain
P201
P202 P203
P204 P205
P206
P301
P302
P303
P304
P305
30
July 2010
50PJ350
Plasma
(11)
(3)
(4)
(5)
(6)
(10)
(9)
(8)
(12)
(13)
(14)
(15)
(7)
31
July 2010
50PJ350
Plasma
Adjustment Notice
Set-Up
-Vy
Vsc
Ve
ZBias
Panel
Rear View
32
July 2010
50PJ350
Plasma
33
July 2010
50PJ350
Plasma
Y-SUS Board
Z-SUS Board
Main Board
VS
VA
M5V
Used to develop Bias Voltages on the Y-SUS then routed to the Control
board and then to the Z-SUS Board.
VS
STBY 5V
Microprocessor Circuits
17V
5V
Also AC_Det (if missing, shuts of TV in 10 seconds) and Error_Det (not used)
Adjustments
There are 2 adjustments located on the Power Supply Board VA and VS. The
M5V is pre-adjusted and fixed. All adjustments are made referenced to Chassis
Ground. Use Full White Raster 100 IRE
VS
VR901
VA
VR502
34
July 2010
50PJ350
Plasma
VS TP
VR901
VS Adj
T901
VS and VA
TP
F801
4A
250V
SMPS
p/n: EAY60968701
ZD803
Stand-By: 0.9V
Run: 388V
VR502
VA Adj
T902
D805
D609
ZD302
D601
ZD401
ZD301
D307
ZD101
ZD303 D303
D601
D305
Stand-By: 1.5V
Run: 388V
L601
T301
F302
2.5A
250V
D308
D309
D306
F101
10A
250V
D103
D302
D301
P813
L602
SC101
35
July 2010
50PJ350
Plasma
P812
VS VR901
VS Source
To Y-SUS
Fuse F801
0.9V Stby
388V Run
4Amp/250V
VA Source
VA VR502
Fuse F302
1.5V Stby
388V Run
17V Source
PFC
Circuit
2.5Amp/250V
RL104
STBY 5V,
5V Source
RL103
Bridge
Rectifier
N/C
To MAIN
10Amp/250V
36
Main Fuse
F101
P813
AC Input
SC 101
July 2010
50PJ350
Plasma
37
July 2010
50PJ350
Plasma
AC In
AC
Det
+5V
Regulator
Stand
By 5V Reg
STBY
3.46V
AC
Det.
RUN
5.14V
17V
Reg
5V
Vs
Reg
Vs
Va
Reg
Va
M_On
3.3V Reg
3.3VST
IC302
2
17V
Audio
IC801
3
6
+5V HDMI
EDID
And other
circuits
5
Error Relay
Det. On
Microprocessor
IC1
Vs M5V Vs
9
M_On
Va
16V
5VFG
8
Y DRIVE Upper
7
8
3.3V
3.3V
X PWB
Center
Va
Y DRIVE Lower
X PWB
Left
2
Soft
Touch
Key Pad
Front IR
Board
July 2010
X PWB
Right
Va
Power Key
38
16V / M5V
3.3V_ST
Power On
3.3V
3.3V
8
M5V
16V / M5V
MAIN
Board
CONTROL
Z-SUS
5V
Floating
Gnd
At point 3
TV is in
Stand-By
state. It is
Energy Star
Compliant.
Less than 1
Watt
7
4
Vs
Y-SUS
8
AC Det.
If missing,
set will not
turn on.
Vs
RL On
Error Det.
Reset
C108, D1,
R62
M5V
17V
Not
Used
M5V
Reg
Va
If
missing
set
shuts
off in 10
Sec.
50PJ350
Plasma
VS TP
VR901
VS Adj
T901
VS and VA
TP
F801
4A
250V
SMPS
p/n: EAY60968701
ZD803
Stand-By: 0.9V
Run: 388V
VR502
VA Adj
T902
D805
D609
ZD302
D601
ZD401
ZD301
D307
ZD101
ZD303 D303
D601
D305
Stand-By: 1.5V
Run: 388V
L601
T301
F302
2.5A
250V
D308
D309
D306
F101
10A
250V
D103
D302
D301
P813
L602
SC101
39
July 2010
50PJ350
Plasma
Pins
or
P812
100W
VS
VR901
VS Adj
T901
P812
VA VS
Test Points
Check Pins 1 or 2
for Vs voltage
100W
F801
4A 250V
Pins
Gnd
or
or
Check Pins 6 or 7
for Va voltage
VR502
VA Adj
T902
POWER SUPPLY
p/n: EAY60968701
ZD401
D609
ZD302
F302
2.5A
250V
Note:
Always test the SMPS under a
load using the 2 light bulbs.
Abnormal operational
conditions may result if not
loaded.
T301
L601
F101
10A 250V
P813
L602
SC101
Note:
To turn on the Power Supply;
1) With Main Board connected, press power.
2) Without Main Board connected SMPS will turn on automatically.
P813
Any time AC is applied to the SMPS, STBY 5V will be 3.46V and will
be 5.14V when the set turns on.
AC DET WILL NOT be present until set comes on.
If AC Det is missing, the TV will come on and shut off in 10 Seconds.
Check Pins 13 or 14
for 5V SBY (5.14V)
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July 2010
50PJ350
Plasma
Pins
or
P812
100W
VS
Use Main
Board Side
Pin 1
(Front Right)
P301
VR901
VS Adj
T901
17V
17V
Gnd
Gnd
+5V
+5V
Error Det
+5V
Gnd
10
Gnd
Gnd
VA VS
Test Points
100W
F801
4A 250V
Pins
Gnd
or
or
VR502
VA Adj
T902
POWER SUPPLY
p/n: EAY60968701
ZD401
ZD302
D609
L601
F101
10A 250V
L602
SC101
P813
11
13
AC Det 16
15
A
Auto Gnd
18
17
STBY
5V
RL
ON
M_On
When the supply is operational in its normal state the Auto Ground line at Pin 18 of P813 is held at ground by the Main Board.
This Power Supply can be powered on sequentially to test the Controller Chip IC701 operational capabilities and for
troubleshooting purposes.
Disconnect P301 from the Main board and use the holes in that end of the connector to insert the jumper and resistors.
Warning: Remove AC before adding or removing any plug or resistor.
Note: Leave previous installed 100 resistor in place when adding the next resistor.
(A) Ground the Auto Gnd Line (Pin 18) will allow the supply to be powered up one section at a time.
(B) Add a 100 watt resistor from 5V Standby to RL_ON and the AC Det, 17V and 5V Lines on P813 will become active.
(C) Add a 100 watt resistor from any 5V line to M_ON (Monitor_On) to make the M5V, VS and VA lines operational.
P812 (VS pins 1 and 2) (VA pins 6 and 7) and (M5V pins 9 and 10).
41
July 2010
50PJ350
Plasma
B
100
T301
100
F302
2.5A
250V
Gnd 12
STBY
14
5V
Label
STBY
Run
Diode Mode
1-2
16V
0V
17V
3.17V
3-4
Gnd
Gnd
Gnd
Gnd
5-7
5V
0.46V
5.17V
1.16V
Error Det
2.85V
4.1V
3.09V
ac
9-12
Gnd
Gnd
Gnd
Gnd
13-14
Stby 5V
3.46V
5.14V
2.55V
15
RL On
0V
2.43V
Open
AC Det
0V
4.44V
3.06V
M_ON
0V
3.29V
Open
Auto Gnd
Gnd
Gnd
Open
16
ad
17
18
P813
1
a Note: The 17V, 5V, AC_Det and Error Det turn on when the RL_On command arrives.
b Note: The M5V, Va and Vs turn on when the M_On (Monitor On) command arrives.
c Note: The Error Det line is not used in this model.
d Note: If the AC Det line is Missing, the TV will shut off after 10 seconds of operation.
e Note: Pin 18 is grounded on the Main board. If this line is floated, the SMPS turns on
Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode.
42
July 2010
50PJ350
Plasma
SMPS Connector SC101 and P812 Identification, Voltages and Diode Check
SC101 AC INPUT
Connector
SC101
Vs TP
L and N
Standby
Run
120VAC
120VAC
Diode Mode
Open
P812
Va TP
Pin Number
Pin
Label
Run
Diode Mode
1, 2
*Vs
*206V
Open
n/c
n/c
n/c
4, 5
Gnd
Gnd
Gnd
6, 7
*Va
*60V
Open
Gnd
Gnd
Gnd
9, 10
M5V
5V
2.16V
Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode.
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July 2010
50PJ350
Plasma
(Overview)
Y-SUS Board develops the V-Scan drive signal to the Y-Drive boards.
This Section of the Presentation will cover alignment and troubleshooting the Y-SUS Board
for the Single Scan Plasma. Upon completion of the Section the technician will have a better
understanding of the operation of the circuit and will be able to locate voltage and
Diode mode test points needed for troubleshooting and alignments.
Adjustments
DC Voltage and Waveform Checks
Diode Mode Measurements
Operating Voltages
SMPS Supplied
VA
VS
M5V
Y-SUS Developed
-VY VR502
VSC VR501
V SET UP VR401
V SET DN VR402
16V
Floating Ground
FG 5V
FG 15V
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July 2010
50PJ350
Plasma
Distributes
VA
Left X Board
Circuits generate
Y-Sustain Waveform
Z-SUS Board
VA
Distributes Vs
Control Board
Y-Drive Boards
Display Panel
45
July 2010
50PJ350
Plasma
p/n: EBR63039801
P211
FS203 (VS)
4A/250V
VS to the Z-SUS
Floating Gnd
P210
To Y-Drive Upper
Floating Gnd
Scan Signal
FS201 (VA)
10A/125V
-Vy TP
FS202 (M5V)
10A/125V
VR401
Set Dn
VSC TP
FS204 (16V)
2A/125V
Floating Gnd
To Y-Drive Lower
VR501
VSC
Floating Gnd
Logic Signals to
Lower Y-Drive Board
P212
P101
VR502
-Vy
P203
c
Va to Left X Board Pins 5~7
46
July 2010
50PJ350
Plasma
50PJ350 Y-SUS
Layout Drawing
VR402
Set-Up
Example:
Model : PDP 50T1###
Voltage Setting: 5V/ Va:60/ Vs:206
N.A. / -198 / 135 / N.A. / 95
Max Watt : 330 W (Full White)
P211
D401
FS203 VS
Diode Check reads Open with
Board Disconnected or Connected
FS203 4A
VS
Label
Run
1~2
Gnd
Gnd
n/c
n/c
n/c
4~5
+Vs
*206V
Open
n/c
n/c
6
FG
7~11
D409
D407
P210
VSC
SUS_DN (FG)
FG
SUS_DN (FG)
FG
FG
YB_OC2
2.63V
1.47V
YB_OC2
2.63V
1.47V
YT_DATA
0V
1.38V
VS
n/c
n/c
p/n: EBR63039801
4~5
Gnd
Gnd
Gnd
6~7
VA
*60V
Open
Gnd
Gnd
Gnd
9~10
M5V
5.1V
1.19V
Diode Check
YT_DATA
0V
1.38V
YTB_OC1
2.2V
1.47V
YTB_OC1
2.2V
1.47V
FS201 10A
VA
2.8V
1.37V
2.8V
1.37V
11
YB_CLK
0.86V
1.38V
12
YB_CLK
0.86V
1.38V
13
SUS_DN (FG)
FG
FG
14
SUS_DN (FG)
FG
FG
15
FG5V
4.9V
1.82V
16
FG5V
4.9V
1.82V
17
SUS_DN (FG)
FG
FG
VSC
TP
D503
T302
VSC
FG
IC502
D501
IC302
Q502
D513
P212
D514
2
1
3
2
1
3
Label
Run
Diode Check
1~3
Pin
+15V
16V
1.61V
4~7
8
+5V
Gnd
4.9V
Gnd
1.19V
Gnd
1.54V
FS202
10A
5VDC
VR502
-Vy
IC503
D502 Q503
VR401
Set-Dn
D504
ZD501
YB_STB
YB_STB
TP
IC508
D511
D512
T502
9
10
VSC
TP
FS202 M5V
Diode Check reads
0.97V Board Connected
or 1.19 Disconnected
-Vy
TP
-VY
FG
Scan
*195V
Diode
Check
Open
n/c
FS201 Va
Diode Check reads Open with
Board Disconnected or Connected
VR501
VSC
Run
Label
1~2
WARNING:
Both Y-DRIVE Boards must be
removed completely if P205 /
P204 / P110 is pulled.
Label
Open
Y-SUS BOARD
Scan
Pin
n/c
ER_PASS 98V~102V
-Vy
Diode
Check
Gnd
Pin
D515
FS204 2A
16VDC
P101
IC509
P203
47
July 2010
CTRL_OE
0V
10
Gnd
Gnd
Gnd
11
OE
0V
1.75V
12
Gnd
Gnd
Gnd
13
Gnd
Gnd
Gnd
14
OC2
1.78V
1.19V
15
Delta_VY_Det
2.08V
1.18V
16
DATA
0V
1.02V
17
SET_ON
2.09V
1.14V
18
OC1
1.43V
1.14V
19
Det_Level_Sel
0.03V
1.14V
20
STB
1.97V
1.14V
21
Slope_Rate_Sel
1.34V
1.14V
22
CLK
0.59V
1.14V
23
YER_DN
0V
1.14V
24
SET_UP
0.24V
1.14V
25
YSUS_DN
0.95V
1.14V
26
Ramp_Slope
1.01V
1.14V
27
YER_UP
0.62V
1.14V
28
Y_Pass_Top
1.08V
1.14V
29
YSUS_UP
0.06V
1.14V
30
Gnd
Gnd
Gnd
50PJ350
Plasma
CAUTION: Use the actual panel label and not the book for exact voltage settings.
This is just for example
Set should run for 15 minutes, this is the Heat Run mode.
Set screen to White Wash.
1) Adjust Vy VR502 to Panels Label voltage (+/- 1V)
2) Adjust VSC VR501 to Panels Label voltage (+/- 1V)
-Vy
VSC
-Vy TP
VSC TP
VR501
VSC Adj
VR502
-Vy Adj
Voltages Reads
Positive
Location: Bottom Center of board
Just above Transformer
48
July 2010
50PJ350
Plasma
2MSec
75 to 90 VRMS
548V p/p
White to Black
200uSec
100uSec
49
July 2010
50PJ350
Plasma
50
July 2010
50PJ350
Plasma
Adjustment
Area
Fig 1:
As an example of how to lock in to the Y-Drive Waveform.
Fig 1 shows the signal locked in at 2ms per/div.
Note the 2 blanking sections.
The area for adjustment is pointed out within the Waveform
Fig 2:
At 200uSec per/division, the area of the waveform to
use for SET-UP or SET-DN is now becoming clear.
Now the only two blanking signals are present.
Area to
expand
FIG1
2mS
Blanking
Blanking
Adjustment
Area
FIG2
200uS
Area to
expand
Blanking
Fig 3:
At 100us per/div the area for adjustment of SET-UP or SET-DN
is now easier to recognize. It is outlined within the Waveform.
Remember, this is the 1st large signal to the right of blanking.
FIG3
100uS
Expanded from above
224V
p/p
180 uSec
51
July 2010
50PJ350
Plasma
Observe the Picture while making these adjustments. Normally, they do not have to be done.
ADJUSTMENT LOCATION:
Top Left of the board.
VR402
Y-Drive Test Point
Lower Y-Drive Top Buffer
SET-UP ADJUST:
1) Adjust VR402 and set the (A) portion of the signal to
match the waveform above. (224V p/p 5V)
SET-DN ADJUST:
2) Adjust VR401 and set the (B) time of the signal to match
the waveform above. (180uSec 5uSec)
VR401
ADJUSTMENT LOCATION:
Lower Center Right
of the board.
52
July 2010
50PJ350
Plasma
53
July 2010
50PJ350
Plasma
Too Low
116uSec
54
July 2010
50PJ350
Plasma
P/N EBR6303801
Scan
Scan
55
July 2010
50PJ350
Plasma
Y-SUS Board P212 Connector to P205 Lower Y-Drive (Logic and FG5V)
TIP: Connectors do not come with a new Y-SUS or Y-Drives.
TIP: Use Scan Screw Lugs to test for Y-Scan signal if the Y-Drive boards are removed.
P205
P212
FGnd
FG5V (4.9V) measured from Pins 15 or 16
To Floating Gnd
Use screw just above P212 on the Y-SUS
c
Y-Drive Lower
Y-SUS Board
56
July 2010
50PJ350
Plasma
c
FGnd
P205
P212
c
c
Y-Drive Lower
Y-SUS Board
Pin
Label
17
SUS_DN (FG)
16
FG5V
15
FG5V
14
SUS_DN (FG)
13
SUS_DN (FG)
12
YB_CLK
11
YB_CLK
10
YB_STB
YB_STB
YTB_OC1
YTB_OC1
YT_DATA
YT_DATA
YB_OC2
YB_OC2
SUS_DN (FG)
SUS_DN (FG)
Pins 3~12
(4mSec per/div)
The signal for these pins look very similar
due to the fact they are read from Chassis Gnd,
but they are actually Floating Ground related.
DO NOT hook scope Gnd to Floating Gnd TP
without an Isolation Transformer.
57
July 2010
50PJ350
Plasma
FGnd
P205
P212
c
c
Y-Drive Lower
Y-SUS Board
Red Lead on FG
Pin
Label
Run
Diode Check
Diode Check
17
SUS_DN (FG)
FG
FG
FG
16
FG5V
4.9V
1.82V
0.56V
15
FG5V
4.9V
1.82V
0.56V
14
SUS_DN (FG)
FG
FG
FG
13
SUS_DN (FG)
FG
FG
FG
12
YB_CLK
0.86V
1.38V
0.54V
11
YB_CLK
0.86V
1.38V
0.56V
10
YB_STB
2.8V
1.37V
0.66V
YB_STB
2.8V
1.37V
0.66V
YTB_OC1
2.2V
1.47V
0.68V
YTB_OC1
2.2V
1.47V
0.68V
YT_DATA
0V
1.38V
0.54V
YT_DATA
0V
1.38V
0.55V
YB_OC2
2.63V
1.47V
0.68V
YB_OC2
2.63V
1.47V
0.68V
SUS_DN (FG)
FG
FG
FG
SUS_DN (FG)
FG
FG
FG
58
July 2010
50PJ350
Plasma
P118
D511
FG 19.86V
D512
FG 9.17V
FG 15V
Regulator
IC508
D513
FG 15.24V
Location
D514
FG 4.97V
FG 5V
Regulator
IC509
59
Location
Back Side of Board
July 2010
50PJ350
Plasma
Location
Run: 16V
T502
D515
16V Source
Cathode Right Side
Just above T502
60
July 2010
50PJ350
Plasma
Diode Check
Open
With Board
Disconnected
or Connected
FS201 (M5V)
10V/125V
Diode Check
1.19V
With Board
Disconnected.
0.97V with board
connected.
FS204
(16V)
2A/125V
61
July 2010
50PJ350
Plasma
Label
Run
Diode Check
1~2
Vs
*195V
Open
n/c
n/c
n/c
4~5
Gnd
Gnd
Gnd
6~7
Va
*60V
Open
Gnd
Gnd
Gnd
9~10
M5V
5.1V
1.19V
P210
Label
Run
Diode Check
1~3
Gnd
Gnd
Gnd
n/c
n/c
Open
5~7
Va
*60V
Open
P203
62
July 2010
50PJ350
Plasma
P211
P211 Connector "Y-SUS" to "Z-SUS" P2
Pin
Label
Run
Diode Check
1~2
Gnd
Gnd
Gnd
n/c
n/c
n/c
4~5
*Vs
*206V
Open
n/c
n/c
n/c
7~11
*ER_PASS
98V~102V
Open
Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode.
63
July 2010
50PJ350
Plasma
Label
Run
Diode
Pin
Label
Run
Diode
+15V
16V
1.61V
16
DATA
0V
1.02V
+15V
16V
1.61V
17
SET_ON
2.09V
1.14V
+15V
16V
1.61V
18
OC1
1.43V
1.14V
+5V
4.9V
1.19V
19
Det_Level_Sel
0.03V
1.14V
+5V
4.9V
1.19V
20
STB
1.97V
1.14V
+5V
4.9V
1.19V
21
Slope_Rate_Sel
1.34V
1.14V
+5V
4.9V
1.19V
22
CLK
0.59V
1.14V
Gnd
Gnd
Gnd
23
YER_DN
0V
1.14V
CTRL_OE
0V
1.54V
24
SET_UP
0.24V
1.14V
10
Gnd
Gnd
Gnd
25
YSUS_DN_IN
0.95V
1.14V
11
OE
0V
1.75V
26
Ramp_Slope
1.01V
1.14V
12
Gnd
Gnd
Gnd
27
YER_UP
0.62V
1.14V
13
Gnd
Gnd
Gnd
28
Pass_Top
1.08V
1.14V
14
OC2
1.78V
1.19V
29
YSUS_UP_IN
0.06V
1.14V
15
Delta_VY_Det
2.08V
1.18V
30
Gnd
Gnd
Gnd
64
July 2010
50PJ350
Plasma
65
July 2010
50PJ350
Plasma
Y-DRIVE UPPER
(TOP)
66
July 2010
50PJ350
Plasma
p/n: EBR63551601
PANEL
SIDE
Y-SUS
SIDE
Floating
Ground
Standoff
VScan
The VScan
Standoff delivers the
VScan signal to the
Y-Drive Boards.
There is per/board.
P110
67
July 2010
50PJ350
Plasma
P204
PANEL
SIDE
p/n: EBR63551701
Y-SUS
SIDE
VScan
The VScan
Standoff delivers the
VScan signal to the
Y-Drive Boards.
There is per/board.
Floating
Ground
Standoff
The Floating Ground
Standoff delivers FG
To the Y-Drive Boards.
There are 2 per/board.
P205
68
July 2010
50PJ350
Plasma
Y-SUS
SIDE
Floating Gnd
Floating Gnd
Scan Signal
Scan Signal
Floating Gnd
Floating Gnd
69
FG5V TP
Open with Red Lead on Scan
0.41V with Black Lead on Scan
Any Output Buffer TP
Open with Red Lead on Scan
0.79V with Black Lead on Scan
July 2010
50PJ350
Plasma
BACK SIDE
FRONT SIDE
BUFFER IC
(FGnd)
RED LEAD On
BLACK LEAD On ANY
Floating Ground
Output Lug Reads 0.79V
Indicated by white outline
BACK
SIDE
BLACK LEAD On
RED LEAD On ANY
Floating Ground
Output Lug Reads Open
Indicated by white outline
6 Ribbon cables communicating with the Panels (Horizontal
Electrodes) totaling 768 lines determining the Panels Vertical
resolution pixel count.
70
July 2010
50PJ350
Plasma
Y-Drive Upper
P110 "Upper Y-Drive"
c
P110
P204
Black Lead
on FG
Red Lead
on FG
Pin
Label
Run
Diode Check
Diode Check
1~10
SUS_DN (FG)
FG
FG
FG
11
YSUS_DATA
0V
Open
Open
12
YT_OCR
2.4V
Open
0.53V
13
YT_OC1
2.2V
Open
0.55V
14
YT_LE(STB)
2.6V
Open
0.52V
15
YT_CLK
0.8V
Open
0.52V
16
YT_DATA
0V
Open
0.52V
17~20
SUS_DN (FG)
FG
FG
FG
21~23
FG5V
4.97V
2.8V
0.41V
24~30
SUS_DN (FG)
FG
FG
FG
Y-Drive Lower
Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode.
71
July 2010
50PJ350
Plasma
Y-Drive Upper
P204 "Lower Y-Drive"
c
P110
P204
Black Lead
on FG
Red Lead
on FG
Pin
Label
Run
Diode Check
Diode Check
1~7
SUS_DN (FG)
FG
FG
FG
8~10
FG5V
4.97V
Open
0.41V
11~14
SUS_DN (FG)
FG
FG
FG
15
YT_DATA
0V
Open
0.52V
16
YT_CLK
0.8V
Open
0.52V
17
YT_LE(STB)
2.6V
Open
0.52V
18
YT_OC1
2.2V
Open
0.55V
19
YT_OCR
2.4V
Open
0.53V
20
YSUS_DATA
0V
Open
Open
21~30
SUS_DN (FG)
FG
FG
FG
Y-Drive Lower
Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode.
72
July 2010
50PJ350
Plasma
Gently Pry
Up Here
Locking tab in
upright position
Fig 1
Fig 3
Fig 2
To reinstall the Ribbon Cable, carefully slide it back into the slot see ( Fig 3 ), be sure the Tab is seated
securely and press the Locking Tab back to the locked position see ( Fig 2 then Fig 1).
73
July 2010
50PJ350
Plasma
74
July 2010
50PJ350
Plasma
Z-SUS SECTION
This Section of the Presentation will cover troubleshooting the Z-SUS Board Assembly.
Upon completion of this section the Technician will have a better understanding of the circuit and be
able to locate voltage and diode mode test points needed for troubleshooting and all alignments.
Note: The Z-SUS can not be run Stand-Alone in the 50T1 Panel Models.
Locations
Operating Voltages
Power Supply Supplied
VS
M5V Routed through Control Board
Y-SUS Supplied
Developed on Z-SUS
Z Bias
75
July 2010
50PJ350
Plasma
Y-SUS Board
16V
M5V
Control Board
VS
M5V
16V
Receives
Logic
Signals
Via 3 FPC
Flexible
Printed
Circuits
NO IPMs
PDP
Display
76
July 2010
Z-SUB
50PJ350
Panel
Plasma
P/N EBR63040301
P101
P2
VS from Y-SUS.
Error Com to
the Y-SUS
No IPMs
Z-SUS
Output
FETs
No IPMs
P12
from
Control
Z-Bias TPs
Z-SUS
Waveform
Development
FETs
Z-SUS
Waveform
Test Point
J36
No IPMs
Z-Bias
VR201
P102
M5V from SMPS to the Y-SUS generates +16V.
M5V and 16V are routed through the Control board.
Logic Signals generated on the Control board.
P3 To Z-SUB
77
July 2010
50PJ350
Plasma
P4
D312
P2
Z-SUS BOARD
p/n: EBR63040301
Z-Bias
Waveform
J36
VZB
TP
P1
VR201
VZB
P5
P3
78
July 2010
50PJ350
Plasma
Z-SUS Waveform
The Z-SUS (in combination with the Y-SUS) generates a
SUSTAIN Signal and an ERASE PULSE for generating
SUSTAIN and DISCHARGE in the Panel.
This waveform is supplied to the panel through two FPC
(Flexible Printed Circuit) connections P101 and P102 and
to the Z-SUB P3 to P7 and then to one FPC (Flexible
Printed Circuit) connections P202.
Reset
Y Drive
Waveform
Z Drive
Waveform
This Waveform is just for reference to observe the effects of Zbz adjustment
79
July 2010
50PJ350
Plasma
VZB (Z-Bias) TP
+
VZB (Z Bias)
VR201
Set should run for 15 minutes, this is the Heat Run mode.
Set screen to White Wash mode or 100 IRE White input.
All SMPS adjustments should have been completed.
1. Place DC Volt meter between VZB TPs.
2. Adjust VZB (Z Bias) VR201 in accordance with your Panels voltage label.
80
July 2010
50PJ350
Plasma
Label
Run
Diode Check
1~2
Gnd
Gnd
Gnd
n/c
n/c
n/c
4~5
+Vs
*206V
Open
n/c
n/c
n/c
7~11
ER_COM
98V~102V
Open
Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode.
81
July 2010
50PJ350
Plasma
Label
Run
Diode Check
1~2
(+15V)
16V
Open
3~4
(+5V)
4.9V
1.52V
Gnd
Gnd
Gnd
Y_OE
0.058V
3.09V
ZBIAS
1.83V
Open
SLOP_CONTROL
Gnd
Open
Z_ER
0.14V
Open
10
ZSUS_DN
0.77V
Open
11
ZSUS_UP
0.17V
Open
12
Gnd
Gnd
Gnd
Pin 1
82
July 2010
50PJ350
Plasma
Signals
Main Board Supplied Panel Control and LVDS (Video) Signals
Control Board Generated Y-SUS and Z-SUS Drive Signals (Sustain)
X Board Drive Signals (RGB Address)
Operating Voltages
Y-SUS Supplied
July 2010
50PJ350
Plasma
p/n: EBR63549501
P102
P121
P111
IC211
IC231
P101
IC801
Pattern Generator
For Panel Test
D201 Should
be blinking
P161
P162
84
July 2010
50PJ350
Plasma
LVDS Video
P121
P102
IC231
4-7 (M5V)
Ribbon Cable
Y-SUS and Y Drive Signals
CONTROL BOARD
p/n: EBR63549501
X101
IC141
IC211
P111
IC101
IC101
IC1
16V protected by
FS204 on Y-SUS
D201 LED
VS_DA
P162
P161
85
July 2010
IC801
(1) 1.79V
(2) 3.29V
(3) n/c
(4) 0V
(5) 0V
50PJ350
IC211
(1) Gnd
(2) 1.8V
(3) 3.27V
Plasma
Chocolate
(Heat Transfer Material)
Pin 1
IC121
04) 3.3V 03) Gnd
05) Gnd 02) Gnd
06) 3.3V 01) 3.3V
86
July 2010
50PJ350
Plasma
87
July 2010
50PJ350
Plasma
X101
CONTROL
BOARD
CRYSTAL
LOCATION
88
July 2010
50PJ350
Plasma
MCM
DRAM
16 bit words
MCM IC201
To Center
X-Board
X-DRIVE BOARD
Resistor Array
EEPROM
89
PANEL
There are 16 total TCPs.
2 Buffer
Outputs
per TCP
To Center
X-Board
CONTROL BOARD
July 2010
4986 (RGB) / 3 =
1365 Total Pixels (H)
50PJ350
Plasma
Control Board Connector P111 to Y-SUS P101 Voltages and Diode Mode Checks
These pins are very close together. Use Caution when taking Voltage measurements.
Pins 1 through 3
Receive 16V from the Y-SUS.
Protected on Y-SUS by FS204
Pin c
90
July 2010
50PJ350
Plasma
Pin
Label
Run
Diode Check
Pin
Label
Run
Diode Check
+15V
16V
Open
+15V
16V
Open
+15V
16V
Open
+5V
4.9V
1.4V
+5V
4.9V
1.52V
+5V
4.9V
1.4V
+5V
4.9V
1.52V
Gnd
Gnd
Gnd
CTRL_OE
0V
2.98V
10
Gnd
Gnd
Gnd
11
OE
0V
1.64V
12
Gnd
Gnd
Gnd
13
Gnd
Gnd
Gnd
14
I_OC2
1.78V
2.84V
15
I_Delta_VY_Det
2.08V
2.81V
16
I_DATA
0V
2.84V
17
I_SET_ON
2.09V
2.81V
18
I_OC1
1.43V
2.84V
19
I_Det_Level_Sel
0.03V
2.81V
20
I_STB
1.97V
2.84V
21
I_Slope_Rate_Sel
1.34V
2.81V
22
I_CLK
0.59V
2.82V
23
I_YER_DN
0V
2.81V
24
I_SET_UP
0.24V
2.82V
25
I_YSUS_DN_IN
0.95V
2.82V
26
I_Ramp_Slope_Opt1
1.01V
2.82V
27
I_YER_UP
0.62V
2.83V
28
I_Pass_Top
1.08V
2.82V
29
I_YSUS_UP_IN
0.06V
2.84V
30
Gnd
Gnd
Gnd
Diode Mode Readings taken with all connectors Disconnected. Black lead on Gnd. DVM in Diode Mode.
91
July 2010
50PJ350
Plasma
P121
LVDS
Video Signals from the Main Board to the Control Board are referred
to as Low Voltage Differential Signals or LVDS. The video is
delivered in 12 bit LVDS format. Their presence can be confirmed
with the Oscilloscope by monitoring the LVDS signals with SMPTE
Color Bar input. Loss of these Signals would confirm the failure is on
the Main Board or the LVDS Cable itself.
Example of LVDS Video Signal
LVDS
LVDS Removed
Pins 2~5, 7~8, 11~12, 15~16, 24~25 are LVDS Video Signals.
Pins 9~10 and 22~23 are clock signals for the data.
92
July 2010
50PJ350
Plasma
Pin
Label
Run
Diode
Check
Pin
Label
Run
Diode
Check
Gnd
Gnd
Gnd
17
ROM_TX
3.3V
3.09V
RA2-
1.13V
1.32V
18
ROM_RX
3.29V
3.09V
RA2+
1.35V
1.36V
19
Gnd
Gnd
Gnd
RB2-
1.21V
1.36V
20
n/c
n/c
Open
21
n/c
n/c
Open
22
PC_SER_CLK
0.59V
3.08V
23
PC_SER_DATA
3.3V
3.09V
24
RE2-
1.23V
1.36V
25
RE2+
1.25V
1.36V
26
Gnd
Gnd
Gnd
27
DISP_EN
2.87V
Open
28
Module_SDA1
3.3V
Open
29
Module_SCL1
3.3V
Open
30
n/c
n/c
Open
31
Gnd
Gnd
Gnd
RB2+
1.27V
1.36V
Gnd
Gnd
Gnd
RC2-
1.26V
1.32V
RC2+
1.22V
1.36V
RCLK2-
1.23V
1.36V
10
RCLK2+
1.23V
1.36V
11
RD2-
1.21V
1.36V
12
RD2+
1.26V
1.36V
13
Gnd
Gnd
Gnd
14
Gnd
Gnd
Gnd
15
RF2-
1.23V
1.32V
16
RF2+
1.25V
1.36V
1
Pin 27 is the reason the LVDS
cable must be removed to use the
EX_AUTO_GEN shorting pins to
create multiple internal generated
test patterns (Panel Test).
Enables the
Control Board
93
July 2010
50PJ350
Plasma
P101 Label
Label
Run
Diode Check
(+15V)
16V
Open
(+15V)
16V
Open
(+5V)
4.9V
1.52V
(+5V)
4.9V
1.52V
Gnd
Gnd
Gnd
Y_OE
0.058V
3.09V
ZBIAS
1.83V
Open
SLOP_CONTROL
Gnd
Open
Z_ER
0.14V
Open
10
ZSUS_DN
0.77V
Open
11
ZSUS_UP
0.17V
Open
12
Gnd
Gnd
Gnd
5V
16V
Diode Mode Readings taken with all connectors Disconnected. Black lead on Gnd. DVM in Diode Mode.
94
July 2010
50PJ350
Plasma
Pin
Run
Diode Mode
Pin
Run
Diode Mode
1.27V
0.97V
33
1.0V
0.97V
1.0V
0.97V
34
1.27V
0.97V
1.27V
0.97V
35
1.0V
0.97V
1.0V
0.97V
37
1.27V
0.97V
1.27V
0.97V
38
1.0V
0.97V
1.0V
0.97V
39
1.27V
0.97V
11
1.27V
0.97V
40
1.0V
0.97V
12
1.0V
0.97V
42
1.27V
0.97V
14
1.27V
0.97V
43
1.0V
0.97V
15
1.0V
0.97V
44
1.27V
0.97V
16
1.27V
0.97V
45
1.0V
0.97V
17
1.0V
0.97V
46
1.27V
0.97V
19
1.27V
0.97V
47
1.0V
0.97V
20
1.0V
0.97V
49
1.27V
0.97V
21
1.27V
0.97V
50
1.0V
0.97V
22
1.0V
0.97V
51
1.27V
0.97V
24
1.27V
0.97V
52
1.0V
0.97V
25
1.0V
0.97V
53
1.27V
0.97V
26
1.27V
0.97V
54
1.87V
1.2V
27
1.0V
0.97V
56
1.87V
1.2V
29
1.27V
0.97V
57
3.22V
1.2V
30
1.0V
0.97V
58
0.49V
1.1V
32
1.27V
0.97V
59
0.49V
1.1V
95
White hash
marks count
as 5
July 2010
50PJ350
Plasma
56~60
3.3V
Run
Diode
Mode
Pin
Run
Diode
Mode
Pin
Run
Diode
Mode
Pin
Run
Diode
Mode
1.27V
0.97V
15
1.27V
0.97V
29
1.27V
0.97V
43
1.0V
0.97V
1.0V
0.97V
17
1.0V
0.97V
30
1.0V
0.97V
46
1.27V
0.97V
1.27V
0.97V
18
1.0V
0.97V
32
1.27V
0.97V
47
1.0V
1.2V
1.0V
0.97V
19
1.27V
0.97V
33
1.0V
0.97V
48
1.27V
1.2V
1.27V
0.97V
20
1.0V
0.97V
35
1.27V
0.97V
49
1.0V
1.2V
1.0V
0.97V
22
1.27V
0.97V
36
1.0V
0.97V
50
1.27V
1.1V
1.27V
0.97V
23
1.0V
0.97V
37
1.27V
0.97V
51
1.0V
0.97V
10
1.0V
0.97V
24
1.27V
0.97V
38
1.0V
0.97V
52
1.27V
0.97V
11
1.27V
0.97V
25
1.0V
0.97V
40
1.27V
0.97V
56~60
3.3V
0.67V
12
1.0V
0.97V
27
1.27V
0.97V
41
1.0V
0.97V
14
1.27V
0.97V
28
1.0V
0.97V
42
1.27V
0.97V
96
July 2010
Note:
There are no voltages in
Stand-By mode.
50PJ350
Plasma
97
July 2010
50PJ350
Plasma
98
July 2010
50PJ350
Plasma
99
July 2010
50PJ350
Plasma
VA
Pins 4~7
3.3V
Pins 32~33
VA
Pins 44~47
On Gnd
On the below:
VA source
disconnected
from Left X board
100
Gnd
On Gnd
On the below:
July 2010
50PJ350
Plasma
Y-SUS Board
Logic
X_B/D
Frame
Rear panel Vertical Address
Front panel Horizontal Address
256 Vertical
Electrodes
Va
Control Board
3.3V
ctor
Conne
TCP
Taped Carrier
Package
Chocolate
128 lines
Con
nect
or
Flex
ibl
Cabl e
e
TCP
Attached directly
to Flexible cable
Long Black
Heat Sink
101
July 2010
50PJ350
Plasma
TCP Testing
3.3V Origination
From Control board IC231 center leg.
Arrives on X board Cent P232 Pins 1~5
On any Gnd
Gnd
Reversed
On Va (0.51V)
On 3.3V (0.535V)
On EC (Open)
On Va (Open)
On 3.3V (2.8V)
On EC (Open)
Gnd
Va
On the below:
Gnd Va
3.3V
n/c
n/c
1
10
15
102
20
25
30
35
40
45
50
July 2010
50PJ350
Plasma
IC231
Gnd
3.29V
4.94V
3.3V
All Connectors to All TCPs look very
similar for the 3.3V test point. The trace
at pins 32 and 33 of each connector.
There is a small feed trough and a Cap,
you can use for Test Points.
Example here from P204. You can only
check for continuity back to IC231, you
can not run the set with heat sink
removed.
103
July 2010
50PJ350
Plasma
TCP
Tapped
Carrier
Package
Look for burns, pin
holes, damage, etc.
104
July 2010
50PJ350
Plasma
Pin
Label
Run
Diode Check
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
n/c
n/a
n/a
VA
*60V
Open
VA
*60V
Open
VA
*60V
Open
Diode Mode Readings taken with all connectors Disconnected. Black lead on Gnd. DVM in Diode Mode.
105
July 2010
50PJ350
Plasma
P121, P212, P211 and P331 X Board Connector (VA Diode Check)
Out
In
Out
In
Va 1~5
3.3V 11~12
Va 48~50
3.3V 41~42
Va 1~5
3.3V 11~12
Va 48~50
3.3V 41~42
On Chassis Gnd
P212 Center X
P211 Center X
+
P121 Left X
106
P331 Right X
On Chassis Gnd
On Va (0.55) Y-SUS connector
removed, TCPs connected.
On Va (0.6V) all connectors removed,
TCPs disconnected.
July 2010
50PJ350
Plasma
107
July 2010
50PJ350
Plasma
P703
LVDS
P301 to
SMPS
P801
Audio
Optical
Audio
HDMI
USB
IC1
Microprocessor
Video Processor
PC
Audio
Remote
RS232
PC
HDMI
RF
In
Rear
Inputs
108
July 2010
50PJ350
Plasma
C
C
A1 A2
P301
P703
IC308
D2
P704
IC201
IC202
To Ft IR
L313
IC1
L803
IC801
D1
C2
C1
L804
P801
To SPK
12Mhz
X1
Mstar
Micro/
Video
MAIN BOARD
p/n: EBT60953802
C A2
A1
IC402
X402
25Mhz
31.875Mhz
X401
E B
C
IC401
D501
Q404
Q402
E B C
D505
C B
A1
C
A2 C
B E
Q401 Q403
Tuner
C A2
D504
A1
109
July 2010
50PJ350
Plasma
7V (to IC405)
Regulator
Gnd
Gnd
Gnd
Gnd
3.3V
3.3V
Gnd
3.3V
Pin
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
1.3V_VDDC
Regulator
Use scope:
Do not measure Pin 1: 1.4~1.7V P/P
Using DVM, set
Gnd
shuts off.
5.04V
6.07V
4.99V
1.28V
Use scope:
1.28V
Pin 8: 600mV P/P
4.27V
IC308
Q401
Pin
[B]
[E]
[C]
Tuner CVBS
Buffer (Analog)
1.19V
1.86V
Gnd
Pin
[B]
[E]
[C]
IF_P Buffer
(Digital)
1.18V
1.18V
Gnd
Pin
[B]
[E]
[C]
Tuner SIF
Buffer (Digital)
1.32V
1.99V
Gnd
Pin
[B]
[E]
[C]
IF_N Buffer
(Digital)
1.32V
1.99V
Gnd
Q402
Q403
Q404
110
Q502
Pin
[1 B]
[2 S]
[3 D]
[4 G]
HDMI CEC
Buffer
Gnd
3.18V
3.29V
3.3V
Pin
[A1]
[A]
[A2]
Reset
Speed Up
Gnd
0V
Gnd
Pin
[A1]
[C]
[A2]
LED-R
Routing
0V
0.13V
0.28V
D501
Pin
[A1]
[A]
[A2]
B+ Routing
to IC502
0V
4.54V
5.0V
Pin
[A1]
[A]
[A2]
B+ Routing
to IC504
0V
4.54V
5.0V
Pin
[A1]
[A]
[A2]
B+ Routing
to IC503
0V
4.54V
5.0V
D504
D1
D505
D2
IC302
2
2 1E B
3
Q301
S G
D
IC501
Q302
IC701
IC203
IC303
IC304
Q504
E B
Q303
S GE B
Q304
IC703
IC504
D502
IC306
3
A2
MAIN BOARD
p/n: EBT60953802
A1
Q501
E B
C
IC502
2
3
Q702
C E
B
Q503
E B
C
IC503
IC307
IC602
111
July 2010
50PJ350
Plasma
IC203
Pin
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]
[16]
Winbond Serial
Flash
0V
3.30V
n/c
n/c
n/c
n/c
0V
3.3V
0V
Gnd
n/c
n/c
n/c
n/c
0V
0V
Pin
[1]
[2]
[3]
1.8V_MST
Regulator
0.6V
1.85V (Out)
3.3V (In)
IC303
Pin
[1]
[2]
[3]
IC304
IC501
Pin
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
1.2V_DVDD Reg
Pin
Dig Ch Only
[1] Gnd
Only on
[2] 1.2V (Out) with Dig
Channel
[3] 3.3V (In)
IC306
Pin
[1]
[2]
[3]
3.3V_TU
Regulator
Gnd
3.3V (Out)
4.97V (In)
Pin
[1]
[2]
[3]
1.8V_TU
Regulator
Gnd
1.8V (Out)
3.3V (In)
IC307
IC301
3.3V_MST
Regulator
Gnd
3.3V (Out)
5.04V (In)
IC502
Pin
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
IC503, IC504
EDID Data
For HDMI
Gnd
Gnd
Gnd
Gnd
4.52V
4.52V
3.33V
4.53V
Pin
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
RGB
EEPROM
Gnd
Gnd
Gnd
Gnd
5.09V
5.09V
3.33V
5.09V
IC602
IC302
Pin
[1]
[2]
[3]
3.3V_VST
Regulator
Gnd
3.3V (Out)
5.09V (In)
HDCP Data
EEPROM
Gnd
Gnd
3.3V
Gnd
3.3V
3.3V
3.3V
3.3V
IC701
Pin
[1]
[2]
[3]
[4]
[5]
[6]
IC703
Q301
3.3V
5.45V
0V
0V
(-5.37V)
(-5.4V)
(-5.4V)
0V
3.3V
3.3V
n/c
n/c
0V
5.45V
Gnd
3.3V (B+)
Q702
Pin
[B]
[C]
[E]
5V_MST
Switch
0V
5.09V
5.04V
D502
Pin
[G]
[S]
[D]
Q302
RS232 Tx/Rx
Pin
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]
[16]
112
USB 5V
Limiter
4.97V (In)
Gnd
3.3V (Enable)
0V
0V
4.97V (Out)
Q303
3.3V_PVSB Sw
Pin
Dig Ch Only
[G] 0V
Only on
[S] 3.3V with Dig
[D] 3.3V Channel
Q304
Pin
[B]
[C]
[E]
Q501, Q503
Q504
Hot Swap
Pin Switch for HDMI
[B] 0V
[C] 0V
[E] Gnd
Pin
[B]
[C]
[E]
RS232
Tx Buffer
0.6V
0V
Gnd
113
July 2010
50PJ350
Plasma
X1 12Mhz
X1
1.58V
1.49V
X402 25MHZ
X402
1.48V
1.6V
X401 31.875MHZ
X1
X401
MAIN Board
0.54V
0.66V
Crystal Location
Left Side 0.7V p/p
114
July 2010
50PJ350
Plasma
P301 or P703
115
July 2010
50PJ350
Plasma
MAIN Board
Main Board P703 Location
116
July 2010
50PJ350
Plasma
1
P703 Main Board Connector to P121 "Control Board
Pin
Label
Run
Diode
Check
Pin
Label
Run
Diode
Check
n/c
n/c
Open
n/c
n/c
Open
ROM_RX
3.29V
2.6V
ROM_TX
3.3V
2.6V
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Gnd
Module_SCL1
3.3V
2.6V
10
Module_SDA1
3.3V
2.6V
11
RE2+
1.25V
0.77V
12
RE2-
1.23V
1.09V
13
RD2+
1.26V
0.77V
14
RD2-
1.21V
1.09V
15
RCLK2+
1.23V
0.77V
16
RCLK2-
1.23V
0.77V
17
RC2+
1.22V
0.77V
18
RC2-
1.26V
0.77V
19
RB2+
1.27V
0.77V
20
RB2-
1.21V
0.77V
21
RA2+
1.35V
0.76V
22
RA2-
1.13V
0.77V
23
PC_SER_CLK
0.59V
1.03V
24
PC_SER_DATA
3.3V
1.49V
25
DISP_EN
2.87V
0.49V
26
Gnd
Gnd
Gnd
117
July 2010
50PJ350
Plasma
3&4
Soft Touch
Key Board
7&8
Intelligent
Sensor
Stand-By
3.3V
Pin
Label
STBY
Run
Diode
Check
IR
3.3V
3.76V
3.12V
Gnd
Gnd
Gnd
Gnd
Key_CTL_0
3.3V
3.29V
1.53V
Key_CTL_1
3.3V
3.29V
1.53V
LED_RED
2.7V
0.21V
Open
Gnd
Gnd
Gnd
Gnd
EYE_SCL
0V
3.27V
2.64V
EYE_SDA
0.25V
3.27V
2.64V
Gnd
Gnd
Gnd
Gnd
10
3.3VST
3.3V
3.29V
0.85V
11
3.3V_MST
0V
3.31V
0.50V
12
LED_BLUE
0V
0V
Open
Diode Mode Readings taken with all connectors Disconnected. DVM in Diode Mode.
118
July 2010
50PJ350
Plasma
Main Board Plug P301 to Power Supply Voltages and Diode Check
Pin c front
Diode Mode Check with the Board Disconnected. DVM in the Diode mode.
Label
STBY
Run
Diode
1~2
0V
17V
Open
Gnd
Gnd
Gnd
5V
0.46V
5.17V
0.94V
Error_Det
2.85V
4.9V
3.04V
16V
3~4
Gnd
5~7
ac
9~12
Gnd
Gnd
Gnd
Gnd
13~14
STBY_5V
3.46V
5.14V
1.07V
15
RL_ON
0V
2.43V
2.62V
16
ad
AC Det
0V
4.44V
3.1V
17
M_ON
0V
3.29V
Open
Auto_Gnd
Gnd
Gnd
Gnd
18
P301
a Note: The RL_On turns on +5V, 17V Error Det. and AC_DET.
b Note: The M5-On command turns on M5V, Va and Vs.
c Note: The Error Det line is not used in this model.
d Note: If the AC Det line is Missing, the TV will turn off in 10 Seconds.
e Note: Pin 18 is grounded on the Main. If opened, the power
supply turns on automatically.
119
July 2010
50PJ350
Plasma
Pin
Label
SBY
Run
Diode Mode
R-
0V
8.51V
Open
R+
0V
8.51V
Open
L-
0V
8.51V
Open
L+
0V
8.51V
Open
IC801Audio
Amp
Left (+)
Left (-)
Right (+)
Right (-)
P801
Speaker
Connector
Diode Mode Check with the Board Disconnected. DVM in the Diode mode.
120
July 2010
50PJ350
Plasma
FRONT IR, POWER LED and SOFT TOUCH KEY PAD SECTION
The following section gives detailed information about the Front IR and Soft Touch
Key Pad. These boards contains the Infrared Receiver, Intelligent Sensor and Power
LEDs section. The Soft Touch Function Keys is actually a thin pad adhered to the
front protective shield.
The Power LED Driver and Intelligent Sensor IC communicate with the Main Board
Microprocessor (IC1) via Clock and Data lines.
These boards have no adjustments.
The Front Control Board (IR and Intelligent Sensor) receives its operational B+ from
the Main Board:
3.3V_ST from the Main Board. This voltage is generated on the Main
Board (IC302)
The Front Power LEDs are driven by 2 separate pins from the Main board SCL/SDA
pins 7 and 8.
The IR signal is routed back to the Main Board via pin 1.
Also, the Soft Touch Key Pad is routed through the Front IR board and out P100 to
P704 pins 3 and 4.
121
July 2010
50PJ350
Plasma
Front Control (IR and Intelligent Sensor) Board and Power LED Board Location
Lower Left Side (As viewed from rear).
Front IR Board
P100
To Main
P101
To Soft Touch
Key Board
Soft Touch
Key Pad
122
July 2010
50PJ350
Plasma
7&8
Front LEDs
and
Intelligent
Sensor
Stand-By
3.3V
Pin
Label
STBY
Run
Diode Check
IR
3.3V
3.76V
2.75V
Gnd
Gnd
Gnd
Gnd
Key_CTL_0
3.3V
3.29V
2.58V
Key_CTL_1
3.3V
3.29V
2.58V
LED_RED
2.7V
0.21V
3.13V
Gnd
Gnd
Gnd
Gnd
EYE_SCL
0V
3.27V
2.53V
EYE_SDA
0.25V
3.27V
2.54V
Gnd
Gnd
Gnd
Gnd
10
3.3VST
3.3V
3.29V
2.28V
11
3.3V_MST
0V
3.31V
2.85V
12
LED_BLUE
0V
0V
Open
123
July 2010
50PJ350
Plasma
Front IR Board Plug P101 to Soft Touch Keys (Voltages and Pin Identification)
Voltage and Diode Mode Measurements for the Main Board
STBY
Run
Diode Check
0.07
0.16
2.4V
0.07
0.16
2.4V
0.07
0.16
2.4V
0.07
0.16
2.4V
0.07
0.16
2.4V
0.07
0.16
2.4V
0.07
0.16
2.4V
0.07
0.16
2.4V
Diode Mode Readings taken with all connectors Disconnected. Black lead on Gnd. DVM in Diode Mode.
124
July 2010
50PJ350
Plasma
IC100
static sensitive
key press
decoder
c
Button Identification for the Front the static sensitive key pad
125
July 2010
50PJ350
Plasma
Plastic Frame
Lifted up slightly
P101
Ribbon Cable
Soft Touch
Key Pad
126
July 2010
50PJ350
Plasma
P100 (Key 1, Key 2) Resistance Reading with Soft Touch Key pressed.
KEY
Pin 3 measured
from Gnd
KEY
Pin 4 measured
from Gnd
CH (Up)
0.61K Ohms
Volume (+)
3.6K Ohms
CH (Dn)
9K Ohms
Volume (-)
0.62K Ohms
Input
3.66K Ohms
Enter
22K Ohms
Menu
9K Ohms
Pin 3 measured
from Gnd
KEY
Pin 4 measured
from Gnd
CH (Up)
2.1V
Volume (+)
0.89V
CH (Dn)
1.619V
Volume (-)
0.214V
Input
0.88V
Enter
2.42V
Menu
1.667V
P100 Connector IR/LED Control Board to P703 Main (No Key Pressed)
Diode Mode
Readings taken with
all connectors
Disconnected. Black
lead on Gnd. DVM
in Diode Mode.
Pin
Label
STBY
Run
Diode Mode
KEY 1
3.3V
3.29V
2.58V
KEY 2
3.3V
3.29V
1.58V
127
July 2010
50PJ350
Plasma
p/n: EAB60962801
Installed View
Reading
across speaker
wires, 8.2 ohm.
Cone View
128
July 2010
50PJ350
Plasma
129
July 2010
50PJ350
Plasma
2mS
224V p/p
5V
VR402
Set-up
0V
P812
VR401
Set-Dn
75VAC rms White
90VAC rms Black
VA TP
180uSec 5uSec
100V
100uS
IC110
P101
WARNING:
Remove upper Y-DRIVE
Board completely if P110
or P204 is removed.
Y-DRIVE UPPER
BOARD
p/n: EBR63551601
D401
SET-UP
VR402
P102
Floating
GND
FS203 VS
Diode Check reads Open with
Board Disconnected or Connected
D305
FS203
4A
VS
6
7~11
P210
D407
C105
Y-SUS
p/n: EBR63039801
Scan
250V
220uf
P201
Y Signal
TP
P110
P108
N/C
P209
N/C
250V
220uf
FS201 10A
VA
250V
220uf
250V
220uf
P204
Y Signal
TP
FS202
10A
5VDC
250V
220uf
-VY
TP
Scan
IC201
SET-DN
n/c
ER_PASS
n/c
98V~102V
Diode
Gnd
n/c
Open
L601
n/c
Open
L602
P212
P205
D514
2
1
3
Label
SUS_DN (FG)
2
3
IC204
Run
0V
FG5V
4.9V
FG5V
4.9V
SUS_DN (FG)
0V
SUS_DN (FG)
0V
YB_CLK
0.86V
YB_CLK
0.86V
YB_STB
Pin
Label
Run
VS
*195V
n/c
n/c
4~5
Gnd
Gnd
Gnd
Gnd
6~7
VA
*60V
Open
Open
Gnd
Gnd
Gnd
Gnd
9~10
M5V
5.1V
1.19V
2.1V
Run
No Load
Diode
1~2
3~4
16V
0V
Gnd
Gnd
17V
17V
3.17V
Gnd
Gnd
5~7
5V
Gnd
0.46V
5.17V
5.19V
1.13V
8
9~12
Error_Det
2.85V
4.9V
4.9V
3.0V
Gnd
Gnd
Gnd
Gnd
Gnd
3.46V
5.14V
5.19V
2.56V
15
RL_ON
0V
2.43V
0V
Open
16
AC Det
0V
4.44V
4.92V
3.1V
17
M_ON
0V
3.29V
0V
Open
18
Auto_Gnd
Gnd
Gnd
4.84V
Open
FS1
50V
250V
220uf
250V
220uf
250V
220uf
100uS
248V p/p
250V
220uf
D309
P101
P2
D312
Z-SUS
p/n: EBR63040301
n/c
n/c
J36
Z-SUS
OUT
TP
2.8V
YB_STB
2.8V
10
YTB_OC1
2.2V
11
YTB_OC1
2.2V
12
YT_DATA
0V
13
YT_DATA
0V
14
YB_OC2
2.63V
15
YB_OC2
2.63V
16
SUS_DN (FG)
FG
17
SUS_DN (FG)
FG
Note:
Connectors
between
P212~P205
and
P204~P110
DO NOT
come with
a new
board
WARNING:
Va Remove lower Y-DRIVE
Board completely if P212
or P205 is removed.
P203 Y-SUS and P122 X-Left
Pin
1,2,3
4
5,6,7
Y-DRIVE Lower
p/n: EBR63551701
Run
Gnd
nc
VA Voltage
Diode Check
Gnd
nc
Open
IC231
4-7 (M5V)
Ribbon Cable
Y-SUS and Y Drive Signals
P111
P102
P103
Ft IR
Intelligent
Sensor P100
CONTROL
BOARD
p/n:
EBR63549501
No Load
17V
Gnd
5.19V
4.9V
Gnd
5.19V
0V
4.92V
0V
P102
VR201
P162
PANEL TEST:
Disconnect P301,
Remove LVDS Cable.
Short across Auto Gen
TPs to generate a test
pattern. When A/C
power is applied.
P201
P202
P7
NOTE: Diode tests are conducted with the board disconnected.
P202
LVDS
P704
To Ft IR
IC303
STBY Run
3.3V
Gnd
3.3V
3.3V
2.7V
Gnd
0V
0.25V
3.76V
Gnd
3.29V
3.29V
0.21V
Gnd
3.27V
3.27V
Q301
B E1 2
C 3 IC302 STBY
Regulator
G S
Q302
D1
A
1~8
Stby/Run
Diode
0.07V/0.16V
2.4V
Diode
Gnd
0.85V
0.50V
Open
D501
D504
A2
IC202
C2
IC1
Mstar
Micro/
Video
X1
12Mhz
L313
IC701
IC203
IC402
IC304
2
B E G S
L804
MAIN BOARD
p/n: EBT60953802
IC703
D502
Q304
X402
25Mhz
B E
C
Q504
1
31.875Mhz
X401
Q402
Q404
E B C
D505
C
A1 A2
Q401
C
B E
C
A1
Q501
IC401
IC503
A2
A1
IC308
IC501
Q303
P801
IC502
STBY Run
Diode Pin Label
Gnd Gnd
3.12V 9 Gnd
3.3V 3.29V
Gnd 10 3.3V_ST
1.53V 11 3.3V_MST 0V 3.31V
0V
0V
1.53V 12 LED Blue
Open
Gnd
2.64V
2.64V
C1
P703
IC801
L803
IC201
IC301
1 3
D2
A1 A2
Tuner
B E
C
Q503
E
Q702 B C
B
E B E
C
C
B E
P203
X-Board Center
p/n: EBR64062201
3
IC307
2
IC602
P204
P205
P211
Va out on pins 1-5
3.3V out on pins 11 & 12
P206
P331
X-Board Right
p/n: EBR64062001
Va in on pins 48-50
3.3V in on pins 41~42
P301
P302
P303
P304
A1 C
A2
IC504
3Q403
IC306
2
Va in on pins 48-50
3.3V out on pins 41~42
P201
To SMPS
Measuring Voltage on
Pin 1 of P101 with DVM
turns the TV on. If TV is
on, Input Menu pops up.
Pin
P3
Ft Key Pad
Diode
Open
Gnd
0.94V
3.04V
Gnd
1.07V
2.62V
3.1V
Open
P101
IR Board
p/n: EBR65007704
VS_DA
D201
LED
P105
Run
17V
Gnd
5.17V
4.9V
Gnd
5.14V
2.43V
4.44V
3.29V
To SPK
P212
P1
P301
IC211
IC211 (1) Gnd
(2) 1.8V
IC101 (3) 3.27V
P161
P104
IC141
IC101
IC801
P121
X-Board Left
p/n: EBR64062301
IC231
(1) Gnd
(2) 3.29V
(3) 4.94V
X101
P122
P101
IC1
IC801
(1) 1.79V
(2) 3.29V
(3) n/c
(4) 0V
(5) 0V
VZB TP
+
-
P102
1~3 (16V)
Note: The RL_On turns on +5V, 17V Error Det. and AC_DET.
Note: The M5-On command turns on M5V, Va and Vs.
c
Note: The Error Det line is not used in this model.
d
Note: If the AC Det line is Missing, the TV will turn off in 10 Seconds.
e
Note: Pin 18 is grounded on the Main. If opened, the power
supply turns on automatically.
b
FS202 M5V
Diode Check reads
0.97V Board Connected
or 1.19 Disconnected
P203
P813
P210 P812
Diode Diode
Open Open
1~2
FS201 Va
Diode Check reads Open
with Board Disconnected
or Connected
P203
Test FG5V
across C205
F101
10A
250V
D103
P121
IC509 D512
P202
C205
T301
SC101
D504
Anode = 5VFG
F302
2.5A
250V
D302
D301
ZD502 FB ref
for 15VFG
VR401
Grayed out components
D503
-VY
are on the back
ZD501
VR502
T302
IC503
VSC
IC202
D501
VSC
FS204 2A
TP
IC502
P101
16VDC
Floating
Anti PRV D502
IC302
D515 Cathode
GND
Source for +16V
Q503
Q502
D515
IC510
IC508
Anode = 15VFG
FG5V
2
1
D511
3
FL201
D504 Cathode Source for VSC
D513
T502
IC203
ZD301
ZD101
ZD303 D303
D601
D308
D309
D306
STBY
D609 ZD401
ZD302
D307
Stand-By: 1.5V
Run: 388V
P103
VA
ADJ
D805
D601
Label
D409
IC130
Test FG5V
across C105
IC140
SMPS
p/n: EAY60968701
ZD803
Pin
13~14 STBY_5V
T902
P211
IC120
Stand-By: 0.9V
Run: 388V
VS
ADJ
VS TP
F801
4A
250V
548V p/p
T901
P305
7V (to IC405)
Regulator
Gnd
Gnd
Gnd
Gnd
3.3V
3.3V
Gnd
3.3V
Pin
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
1.3V_VDDC
Regulator
Do not measure
Gnd
5.04V
6.07V
4.99V
1.28V
1.28V
4.27V
IC308
Q401
Pin
[B]
[E]
[C]
Tuner CVBS
Buffer (Analog)
1.19V
1.86V
Gnd
Pin
[B]
[E]
[C]
IF_P Buffer
(Digital)
1.18V
1.18V
Gnd
Pin
[B]
[E]
[C]
Tuner SIF
Buffer (Digital)
1.32V
1.99V
Gnd
Pin
[B]
[E]
[C]
IF_N Buffer
(Digital)
1.32V
1.99V
Gnd
Q402
Use scope:
Pin 1: 1.4~1.7V P/P
Using DVM, set
shuts off.
Q403
Q404
Use scope:
Pin 8: 600mV P/P
Using DVM, set
shuts off.
Q502
Pin
[1 B]
[2 S]
[3 D]
[4 G]
HDMI CEC
Buffer
Gnd
3.18V
3.29V
3.3V
Pin
[A1]
[A]
[A2]
Reset
Speed Up
Gnd
0V
Gnd
Pin
[A1]
[C]
[A2]
LED-R
Routing
0V
0.13V
0.28V
D501
Pin
[A1]
[A]
[A2]
B+ Routing
to IC502
0V
4.54V
5.0V
Pin
[A1]
[A]
[A2]
B+ Routing
to IC504
0V
4.54V
5.0V
Pin
[A1]
[A]
[A2]
B+ Routing
to IC503
0V
4.54V
5.0V
D504
D1
D505
D2
Winbond Serial
Flash
0V
3.30V
n/c
n/c
n/c
n/c
0V
3.3V
0V
Gnd
n/c
n/c
n/c
n/c
0V
0V
Pin
[1]
[2]
[3]
1.8V_MST
Regulator
0.6V
1.85V (Out)
3.3V (In)
IC303
Pin
[1]
[2]
[3]
IC304
IC501
Pin
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
1.2V_DVDD Reg
Pin
Dig Ch Only
[1] Gnd
Only on
[2] 1.2V (Out) with Dig
Channel
[3] 3.3V (In)
IC306
Pin
[1]
[2]
[3]
3.3V_TU
Regulator
Gnd
3.3V (Out)
4.97V (In)
Pin
[1]
[2]
[3]
1.8V_TU
Regulator
Gnd
1.8V (Out)
3.3V (In)
IC307
IC301
3.3V_MST
Regulator
Gnd
3.3V (Out)
5.04V (In)
IC502
Pin
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
IC503, IC504
EDID Data
For HDMI
Gnd
Gnd
Gnd
Gnd
4.52V
4.52V
3.33V
4.53V
Pin
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
RGB
EEPROM
Gnd
Gnd
Gnd
Gnd
5.09V
5.09V
3.33V
5.09V
IC602
IC302
Pin
[1]
[2]
[3]
3.3V_VST
Regulator
Gnd
3.3V (Out)
5.09V (In)
HDCP Data
EEPROM
Gnd
Gnd
3.3V
Gnd
3.3V
3.3V
3.3V
3.3V
IC701
Pin
[1]
[2]
[3]
[4]
[5]
[6]
IC703
USB 5V
Q301
Limiter
4.97V (In)
Gnd
3.3V (Enable)
0V
0V
Q302
4.97V (Out)
RS232 Tx/Rx
Pin
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]
[16]
3.3V
5.45V
0V
0V
(-5.37V)
(-5.4V)
(-5.4V)
0V
3.3V
3.3V
n/c
n/c
0V
5.45V
Gnd
3.3V (B+)
Q303
Q702
Pin
[B]
[C]
[E]
5V_MST
Switch
0V
5.09V
5.04V
D502
Pin
[G]
[S]
[D]
3.3V_PVSB Sw
Pin
Dig Ch Only
[G] 0V
Only on
[S] 3.3V with Dig
[D] 3.3V Channel
Q304
Pin
[B]
[C]
[E]
Q501, Q503
Q504
Pin
[B]
[C]
[E]
Hot Swap
Switch for HDMI
0V
0V
Gnd
Pin
[B]
[C]
[E]
RS232
Tx Buffer
0.6V
0V
Gnd
10
12
11
14
13
16
15
18
17
20
19
22
21
24
23
26
25
15 and 16
Is the Video Clock and
Data lines
End of Presentation
133
July 2010
50PJ350
Plasma