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You are on page 1of 24

October-2015

Abstract

Please read through this entire document carefully before embarking on your assignment or asking any

queries.

Introduction

For this assignment, you are required to design a simple operational amplifier (Op-Amp). You will be

given a few classes of circuits along with the specifications. You are required to meet all the given

specifications.

You need to make the choice and then decide numerical values for each of the system specs that will be

enumerated for you. For this job, you might need to refer to journals and other publications. The library

IEEE site is a good place to start. The Internet is of course an excellent place to scrounge around for

information.

In real life, the specifications would be provided to you by a "customer". As a designer your job is to meet

those specifications. The ability to look at system specifications and translate them to specs for individual

building blocks is an important aspect of design. This assignment will help you get a feel for this.

Assignment Requirement

The instructions given here will need to be followed by all students. Please note that failure to do the

same will result in a penalty of marks. You have to work on this assignment in groups of FOUR only.

Each group is required to submit one copy of the assignment report.

For simulation you have to use Spectre simulator.

Your design should meet all the specifications, at Schematic level.

If you are not able to meet your specs, you can go ahead, but you need to explain why it has

happened at the time of demonstration and in report.

You are advised to use the gm/ID method for meeting gain requirements, while simultaneously

using the OCTC method for meeting bandwidth requirements.

Validate your design for all process corners and temperatures 0, 27 and 100 C.

Library for circuit simulation; is located at /linuxeda/dk/tsmc018/models/fp1/spectre/log018.scs

with Sections TT_3V, FF_3V, SS_3V

Use Model names pch3 for PMOS and nch3 for NMOS, unless otherwise specified. Connect the

body of PMOS to VDD and NMOS to Ground.

Minimum channel length that can be used is 0.35um.

Current sink means that one of the nodes is connected to ground and current source means that

one of the nodes is connected to the supply.

Your Design Should have only one ideal current Source/Sink .

The suggested topologies are to be used unless there is a valid reason not to do the same.

Make sure that all the transistors are working in saturation region.

OTA stands for Operational Trans-conductance Amplifier, which is basically an OPAMP with

high output resistance.

All OPAMPs/OTAs used feedback must be compensated for a phase margin of about 50 to 60,

unless your application requires it to be some other value.

Discussing with your friends is highly encouraged (but not copying). Plagiarism will be

penalized.

There will be no deadline extensions or other considerations based on server or software issues.

You are being given ample time and it is expected that you partition your work well into that time

and not just turn up in the O-Lab on the last couple of days to complete the same.

Based on the specification given, you will need to decide which OPAMP architecture will help you meet

the specs most easily. For example, if a large bandwidth is required it might be inadvisable to use a twostage OPAMP since the compensation capacitance reduces the bandwidth heavily. At the same time

trying to use a large bandwidth OPAMP architecture when a moderate or small bandwidth is required is

considered overkill and will result in penalization in terms of marks.

Specifications

There will be some common specifications which all of the assignment have to meet or follow.

Parameters

Technology

VDD

CL

Current mirror ratios

Reference Current

Specifications

TSMC 180nm technology*

3.3V

500fF

20

Single ideal current source of arbitrary value, with the positive

node tied to VDD or negative node tied to ground

Power Dissipation

3mW unless stated

* Although the technology is 180nm, you are to use the 350nm transistors which are in the design kit for

analog design. The 180nm transistors specifically refer to the digital transistors and will not be able to

sustain the power supply of 3.3V. You will be given a zero in your assignment if you fail to follow this

particular directive.

------------------------------------------------------------------------------------------------------------------------------Ques 1. Design a Two Stage Single-ended output CMOS OPAMP with a -3dB bandwidth of 1KHz, a phase

margin of 600, a gain of 105 V/V.

(a) Analog schematic for OPAMP (choose appropriate OPAMP).

(b) Analysis of all equations for OPAMP, with a systematic derivation of all transistors W/L ratios.

(Do not use hit-and-trial method)

(c) Use STB Analysis to find the closed loop gain and phase margin for your OPAMP.

(d) Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain and

phase, CMRR plot, ICMR plot, PSRR plot, slew rate, settling time, output voltage swing (dc +

Transient), power consumption, and input and output offset voltage.

Ques 2. Design a two stage single-ended output CMOS OPAMP with a UGB of 100MHz, a phase margin

of 600, a gain of 15000 V/V.

(a) Analog schematic for OPAMP (choose appropriate OPAMP).

(b) Analysis of all equations for OPAMP, with a systematic derivation of all transistors W/L ratios.

(Do not use hit-an-trial method)

(c) Use STB Analysis to find the closed loop gain and phase margin for your OPAMP.

(d) Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain and

phase, CMRR plot, ICMR plot, PSRR plot, slew rate, settling time, output voltage swing (dc +

Transient), power consumption, and input and output offset voltage.

Ques 3. Design a two stage single-ended output CMOS OPAMP having PSRR and CMRR 120dB.

(a) Analog schematic for OPAMP (choose appropriate OPAMP).

(b) Analysis of all equations for OPAMP, with a systematic derivation of all transistors W/L ratios.

(Do not use hit-an-trial method)

(c) Use STB Analysis to find the closed loop gain and phase margin for your OPAMP.

(d) Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain and

phase, CMRR plot, ICMR plot, PSRR plot, slew rate, settling time, output voltage swing (dc +

Transient), power consumption, and input and output offset voltage.

Ques 4. Design a two stage single-ended output CMOS OPAMP having slew rate greater than 20 V/us,

settling time less than 1us, a phase margin of 600 and a gain of 5000 V/V.

(a) Analog schematic for OPAMP (choose appropriate OPAMP).

(b) Analysis of all equations for OPAMP, with a systematic derivation of all transistors W/L ratios.

(Do not use hit-an-trial method)

(c) Use STB Analysis to find the closed loop gain and phase margin for your OPAMP.

(d) Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain and

phase, CMRR plot, ICMR plot, PSRR plot, slew rate, settling time, output voltage swing (dc +

Transient), power consumption, and input and output offset voltage.

Ques 5. Design a two stage single-ended output CMOS OPAMP having power dissipation 0.1mW and a

gain of 1500V/V.

(a) Analog schematic for OPAMP (choose appropriate OPAMP).

(b) Analysis of all equations for OPAMP, with a systematic derivation of all transistors W/L ratios.

(Do not use hit-an-trial method)

(c) Use STB Analysis to find the closed loop gain and phase margin for your OPAMP.

(d) Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain and

phase, CMRR plot, ICMR plot, PSRR plot, slew rate, settling time, output voltage swing (dc +

Transient), power consumption, and input and output offset voltage.

b) Analysis of all equations of your design, with a systematic derivative of all transistors W/L ratios

and spectre simulation of circuit for the following specifications.

i)

UGB 400 MHz

ii)

Phase margin 600

iii)

Slew rate 50 V/s

c) Use STB Analysis to find the closed loop gain and phase margin for your OPAMP.

d) Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain and

phase, CMRR plot, ICMR plot, PSRR plot, slew rate, settling time, output voltage swing (dc +

Transient), power consumption, and input and output offset voltage.

Ques 7. Design a CMOS OPAMP.

b) Analysis of all equations of your design, with a systematic derivative of all transistors W/L ratios

and spectre simulation of circuit for the following specifications.

i)

DC Gain 120 dB

ii)

Phase margin 600

iii)

Power dissipation 2mW

c) Use STB Analysis to find the closed loop gain and phase margin for your OPAMP.

d) Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain and

phase, CMRR plot, ICMR plot, PSRR plot, slew rate, settling time, output voltage swing (dc +

Transient), power consumption, and input and output offset voltage.

Ques 8. Design a CMOS OPAMP.

b) Analysis of all equations of your design, with a systematic derivative of all transistors W/L ratios

and spectre simulation of circuit for the following specifications.

i)

CMRR 140 dB

ii)

PSRR 120dB

iii)

Output Swing 1.6V

c) Use STB Analysis to find the closed loop gain and phase margin for your OPAMP.

d) Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain and

phase, CMRR plot, ICMR plot, PSRR plot, slew rate, settling time, output voltage swing (dc +

Transient), power consumption, and input and output offset voltage.

Ques 9. Design a CMOS OPAMP.

b) Analysis of all equations of your design, with a systematic derivative of all transistors W/L ratios

and spectre simulation of circuit for the following specifications.

i)

3dB Frequency 100 KHz

ii)

Phase margin 600

iii)

Output swing 2V

c) Use STB Analysis to find the closed loop gain and phase margin for your OPAMP.

d) Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain and

phase, CMRR plot, ICMR plot, PSRR plot, slew rate, settling time, output voltage swing (dc +

Transient), power consumption, and input and output offset voltage.

Ques 10. Design a telescopic OPAMP given in figure 9.8(a) of Razavi: (Iss should be designed using a

transistor)

a) Analysis of all equations of your design, with a systematic derivative of all transistors W/L ratios

and spectre simulation of circuit for the following specifications.

i)

-3dB Bandwidth 10 KHz

ii)

Slew rate 50 V/s

iii)

Output offset voltage 40mV

b) Use STB Analysis to find the closed loop gain and phase margin for your OPAMP.

c) Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain and

phase, CMRR plot, ICMR plot, PSRR plot, slew rate, settling time, Output voltage swing (dc +

Transient), power consumption, and input and output offset voltage.

Ques 11. Design a Single-ended output Folded Cascode OTA.

a) Analog schematic for OTA

b) Analysis of all equations for OTA, with a systematic derivative of all transistors W/L ratios and

spectre simulation of circuit for the following specifications.

i)

DC Gain 120 dB

ii)

Phase margin 550

c) Show a biasing circuitry to bias all the voltages in your design (except the input).

d) Use STB analysis to measure the closed loop gain and phase margin.

e) Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain and

phase, CMRR plot, ICMR plot, PSRR plot, slew rate, Output voltage swing (dc + Transient), power

consumption, and input and output offset voltage.

Ques 12. Design a Single-ended output Folded Cascode [Differential amplifier + common gate stage]

OTA. Use PMOS as the input transistor.

a)

b)

c)

d)

e)

Analysis of all equations for OTA, with a systematic derivative of all transistors W/L ratios and

spectre simulation of circuit for the following specifications.

i)

ICMR 1.8 V

ii)

CMRR 120dB

iii)

output Swing 2V

Show a biasing circuitry to bias all the voltages in your design (except the input).

Use STB analysis to measure the closed loop gain and phase margin.

Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain and

phase, CMRR plot, ICMR plot, PSRR plot, slew rate, Output voltage swing (dc + Transient), power

consumption, and input and output offset voltage.

Ques 13. Design a two stage single-ended output OPAMP (Differential + gain stage) for the following

specification

a) Analysis of all equations of your design, with a systematic derivative of all transistors W/L ratios

and spectre simulation of circuit for the following specifications.

i)

DC gain 100 dB

ii)

Output voltage swing 1.5V

iii)

ICMR 1.5V

iv)

Slew rate 100V/s

v)

Settling time 50ns

b) Show a biasing circuitry to bias all the voltages in your design (except the input).

c) STB analysis to calculate the closed loop gain and phase margin for the OPAMP.

d) Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain and

phase, CMRR plot, ICMR plot, PSRR plot, slew rate, settling time, Output voltage swing (dc +

transient), power consumption, and input and output offset voltage.

.

Ques 14. Design a two stage single-ended output CMOS OPAMP with a UGB of 500KHz, a phase margin

of 600, a gain of 120dB.

(a) Analog schematic for OPAMP (choose appropriate OPAMP).

(b) Analysis of all equations for OPAMP, with a systematic derivation of all transistors W/L ratios.

(Do not use hit-an-trial method)

(c) Use STB Analysis to find the closed loop gain and phase margin for your OPAMP.

(d) Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain and

phase, CMRR plot, ICMR plot, PSRR plot, slew rate, settling time, output voltage swing (dc +

Transient), power consumption, and input and output offset voltage.

Ques 15. Design a telescopic OPAMP given in figure 9.8(a) of Razavi: (Iss should be designed using a

transistor)

a) Analysis of all equations of your design, with a systematic derivative of all transistors W/L ratios

and spectre simulation of circuit for the following specifications.

i) Open loop gain (DC gain) 80 dB

ii) CMRR 100 dB

iii) power dissipation 1mW

b) Use STB Analysis to find the closed loop gain and phase margin for your OPAMP.

c) Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain and

phase, CMRR plot, ICMR plot, PSRR plot, slew rate, Settling time, Output voltage swing (dc +

Transient), power consumption, and input and output offset voltage.

Ques 16. Design a telescopic OPAMP given in figure 9.8(a) of Razavi: (Iss should be designed using a

transistor)

a) Analysis of all equations of your design, with a systematic derivative of all transistors W/L ratios

and spectre simulation of circuit for the following specifications.

i)

Open loop gain (DC gain) 80 dB

ii) Settling time 20 us

iii) power dissipation 0.5mW

b) Use STB Analysis to find the closed loop gain and phase margin for your OPAMP.

c) Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain and

phase, CMRR plot, ICMR plot, PSRR plot, slew rate, Settling time, Output voltage swing (dc +

Transient), power consumption, and input and output offset voltage.

Ques 17. Design a telescopic OPAMP given in figure 9.8(a) of Razavi: (Iss should be designed using a

transistor)

a) Analysis of all equations of your design, with a systematic derivative of all transistors W/L ratios

and spectre simulation of circuit for the following specifications.

i)

PSSR 100 dB

ii)

DC Gain (open loop) 100dB

iii)

Power Dissipation 1mW

b) Use STB Analysis to find the closed loop gain and phase margin for your OPAMP.

c) Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain and

phase, CMRR plot, ICMR plot, PSRR plot, slew rate, settling time, Output voltage swing (dc +

Transient), power consumption, and input and output offset voltage.

Ques 18. Design a telescopic OPAMP given in figure 9.8(a) of Razavi: (Iss should be designed using a

transistor)

a) Analysis of all equations of your design, with a systematic derivative of all transistors W/L ratios

and spectre simulation of circuit for the following specifications.

i)

UGB 100 MHz

ii)

Output swing 1.5 V

b) Use STB Analysis to find the closed loop gain and phase margin for your OPAMP.

c) Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain and

phase, CMRR plot, ICMR plot, PSRR plot, slew rate, settling time, Output voltage swing (dc +

Transient), power consumption, and input and output offset voltage.

Ques 19. Design a two stage single-ended output OPAMP (Telescopic + gain stage) for the following

specification

a) Analysis of all equations of your design, with a systematic derivative of all transistors W/L

ratios and spectre simulation of circuit for the following specifications.

i)

-3dB Frequency 100 KHz

ii)

Phase margin 600

iii)

ICMR 0.9V to 2.2V

b) Show a biasing circuitry to bias all the voltages in your design (except the input).

c) Use STB analysis to measure the closed loop gain and phase margin.

d) Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain and

phase, CMRR plot, ICMR plot, PSRR plot, slew rate, Output voltage swing (dc + Transient), power

consumption, and input and output offset voltage.

Ques 20. Design a two stage single-ended output OPAMP (Telescopic + gain stage) for the following

specification

a) Analysis of all equations of your design, with a systematic derivative of all transistors W/L

ratios and spectre simulation of circuit for the following specifications.

i)

Gain 90 dB

ii)

UGB 100 MHz

iii)

Phase margin 600

b) Show a biasing circuitry to bias all the voltages in your design (except the input).

c) Use STB analysis to measure the closed loop gain and phase margin.

d) Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain and

phase, CMRR plot, ICMR plot, PSRR plot, slew rate, Output voltage swing (dc + Transient), power

consumption, and input and output offset voltage.

Ques 21. Design a two stage single-ended output OPAMP (Telescopic + gain stage) for the following

specification

a) Analysis of all equations of your design, with a systematic derivative of all transistors W/L

ratios and spectre simulation of circuit for the following specifications.

i)

Gain 120 dB

ii)

Phase margin 600

iii)

Output swing 1.5V

b) Show a biasing circuitry to bias all the voltages in your design (except the input).

c) Use STB analysis to measure the closed loop gain and phase margin.

d) Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain and

phase, CMRR plot, ICMR plot, PSRR plot, slew rate, Output voltage swing (dc + Transient), power

consumption, and input and output offset voltage.

Ques 22. Design a two stage single-ended output OPAMP (Telescopic + gain stage) for the following

specification

a) Analysis of all equations of your design, with a systematic derivative of all transistors W/L

ratios and spectre simulation of circuit for the following specifications.

i)

Gain 80 dB

ii)

power dissipation .2mW

iii)

Output swing 2V

b) Show a biasing circuitry to bias all the voltages in your design (except the input).

c) Use STB analysis to measure the closed loop gain and phase margin.

d) Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain and

phase, CMRR plot, ICMR plot, PSRR plot, slew rate, Output voltage swing (dc + Transient), power

consumption, and input and output offset voltage.

Ques 23. Design a two stage single-ended output OPAMP (Telescopic + gain stage) for the following

specification

a) Analysis of all equations of your design, with a systematic derivative of all transistors W/L ratios

and spectre simulation of circuit for the following specifications.

i)

Gain 100 dB

ii)

PSRR 120 dB

iii)

Output swing 1.5V

b) Show a biasing circuitry to bias all the voltages in your design (except the input).

c) Use STB analysis to measure the closed loop gain and phase margin.

d) Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain and

phase, CMRR plot, ICMR plot, PSRR plot, slew rate, Output voltage swing (dc + Transient), power

consumption, and input and output offset voltage.

Ques 24. Design a two stage single-ended output OPAMP (Telescopic + gain stage) for the following

specification

a) Analysis of all equations of your design, with a systematic derivative of all transistors W/L ratios

and spectre simulation of circuit for the following specifications.

i)

CMRR 150 dB

ii)

PSRR 150 dB

b) Show a biasing circuitry to bias all the voltages in your design (except the input).

c) Use STB analysis to measure the closed loop gain and phase margin.

d) Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain and

phase, CMRR plot, ICMR plot, PSRR plot, slew rate, Output voltage swing (dc + Transient), power

consumption, and input and output offset voltage.

Ques 25. Design a two stage single-ended output OPAMP (Folded Cascode[Differential amplifier +

common gate stage] + gain stage) for the following specification

a) Analysis of all equations of your design, with a systematic derivative of all transistors W/L

ratios and spectre simulation of circuit for the following specifications.

i)

Gain 90 dB

ii)

UGB 100 MHz

iii)

Phase margin 600

b) Show a biasing circuitry to bias all the voltages in your design (except the input).

c) Use STB analysis to measure the closed loop gain and phase margin.

d)

Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain and

phase, CMRR plot, ICMR plot, PSRR plot, slew rate, Output voltage swing (dc + Transient), power

consumption, and input and output offset voltage.

Ques 26. Design a two stage single-ended output OPAMP (Folded Cascode[Differential amplifier +

common gate stage] + gain stage) for the following specification

a) Analysis of all equations of your design, with a systematic derivative of all transistors W/L ratios

and spectre simulation of circuit for the following specifications.

i)

Gain 120 dB

ii)

Phase margin 600

b) Show a biasing circuitry to bias all the voltages in your design (except the input).

c) Use STB analysis to measure the closed loop gain and phase margin.

d) Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain and

phase, CMRR plot, ICMR plot, PSRR plot, slew rate, Output voltage swing (dc + Transient), power

consumption, and input and output offset voltage.

Ques 27. Design a two stage single-ended output OPAMP (Folded Cascode[Differential amplifier +

common gate stage] + gain stage) for the following specification

a) Analysis of all equations of your design, with a systematic derivative of all transistors W/L

ratios and spectre simulation of circuit for the following specifications.

i)

Gain 80 dB

ii)

power dissipation .2mW

iii)

Output swing 2V

b) Show a biasing circuitry to bias all the voltages in your design (except the input).

c) Use STB analysis to measure the closed loop gain and phase margin.

d) Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain and

phase, CMRR plot, ICMR plot, PSRR plot, slew rate, Output voltage swing (dc + Transient), power

consumption, and input and output offset voltage.

Ques 28. Design a two-stage CMOS OPAMP as shown in figure;

a)

b)

c)

derivative of all transistors W/L ratios and spectre

simulation of circuit for the following specifications.

i) Open loop gain(DC gain) 90 dB

ii) UGB 200 MHz

iii) Phase margin 550

iv) Differential Output Swing 4.5V

Show a biasing circuitry to bias all the voltages in your

design (except the input).

Calculate and plot the following parameters for your

OPAMP: DC gain, Bode plot for AC gain and phase, ICMR plot, slew rate, Differential Output

voltage swing (dc + Transient), power consumption, and input and output offset voltage.

a)

b)

c)

systematic derivative of all transistors W/L ratios and

spectre simulation of circuit for the following

specifications.

i) Open loop gain(DC gain) 110 dB

ii) Phase margin 600

iii) power dissipation 1mW

Show a biasing circuitry to bias all the voltages in your

design (except the input).

Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain

and phase, ICMR plot, slew rate, Differential Output voltage swing (dc + Transient), power

consumption, and input and output offset voltage.

Ques 30. Design a Single-ended output Folded Cascode [Differential amplifier + common gate stage]

OTA.

a) Analog schematic for OTA

b) Analysis of all equations for OTA, with a systematic derivative of all transistors W/L ratios and

spectre simulation of circuit for the following specifications.

i)

DC Gain 100 dB

ii)

UGB 200 MHz

iii)

Phase margin 600

iv)

Slew rate 100 V/s

c) Show a biasing circuitry to bias all the voltages in your design (except the input).

d) Use STB analysis to measure the closed loop gain and phase margin.

e) Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain and

phase, CMRR plot, ICMR plot, PSRR plot, slew rate, settling time, Output voltage swing (dc +

Transient), power consumption, and input and output offset voltage.

Ques 31. Design a Single-ended output Folded Cascode [Differential amplifier + common gate stage]

OTA.

a) Analog schematic for OTA

b) Analysis of all equations for OTA, with a systematic derivative of all transistors W/L ratios and

spectre simulation of circuit for the following specifications.

i)

CMRR 120dB

ii)

PSRR 120dB

c) Show a biasing circuitry to bias all the voltages in your design (except the input).

d) Use STB analysis to measure the closed loop gain and phase margin.

e) Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain and

phase, CMRR plot, ICMR plot, PSRR plot, slew rate, settling time, Output voltage swing (dc +

Transient), power consumption, and input and output offset voltage.

Ques 32. Design a Single-ended output Folded Cascode [Differential amplifier + common gate stage]

OTA.

b) Analysis of all equations for OTA, with a systematic derivative of all transistors W/L ratios and

spectre simulation of circuit for the following specifications.

i)

DC Gain 80 dB

ii)

UGB 600 MHz

iii)

Phase margin 550

c) Show a biasing circuitry to bias all the voltages in your design (except the input).

d) Use STB analysis to measure the closed loop gain and phase margin.

e) Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain and

phase, CMRR plot, ICMR plot, PSRR plot, slew rate, Output voltage swing (dc + Transient), power

consumption, and input and output offset voltage.

Ques 33. Design a wide Swing Folded-Cascode CMOS OTA as shown in figure;

a) Analysis of all equations of your design, with a systematic derivative of all transistors W/L ratios

and spectre simulation of circuit for the following specifications.

i)

Open loop gain(DC gain) 80 dB

ii) UGB 200 MHz

iii) Phase margin 550

iv) ICMR 2 V

b) Show a biasing circuitry to bias all the

voltages in your design (except the input).

c) Use STB analysis to measure the closed loop

gain and phase margin.

d) Calculate and plot the following parameters

for your OPAMP: DC gain, Bode plot for AC

gain and phase, CMRR plot, ICMR plot, PSRR

plot, slew rate, settling time, Output voltage swing (dc + Transient), power consumption, and

input and output offset voltage.

Ques 34. Design a wide Swing Folded-Cascode CMOS OTA as shown in figure;

a) Analysis of all equations of your design, with a

systematic derivative of all transistors W/L ratios

and spectre simulation of circuit for the following

specifications.

i)

Open loop gain(DC gain) 100 dB

ii) UGB 100 MHz

iii) Phase margin 550

iv) CMRR 150dB

b) Show a biasing circuitry to bias all the voltages

in your design (except the input).

c) Use STB analysis to measure the closed loop

gain and phase margin.

d) Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain

and phase, CMRR plot, ICMR plot, PSRR plot, slew rate, settling time, Output voltage swing (dc

+ Transient), power consumption, and input and output offset voltage.

Ques 35. Design a wide Swing Folded-Cascode CMOS OTA as shown in figure;

a) Analysis of all equations of your design, with a

systematic derivative of all transistors W/L ratios and

spectre simulation of circuit for the following

specifications.

i)

Open loop gain(DC gain) 90 dB

ii) Phase margin 600

iii) output swing 1.4V

iv) power consumption 700 W

b) Show a biasing circuitry to bias all the voltages in

your design (except the input).

c) Use STB analysis to measure the closed loop gain

and phase margin.

d) Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain

and phase, CMRR plot, ICMR plot, PSRR plot, slew rate, settling time, Output voltage swing (dc

+ Transient), power consumption, and input and output offset voltage.

Ques 36. Design a wide Swing Folded-Cascode CMOS OTA

as shown in figure below;

a) Analysis of all equations of your design, with a

systematic derivative of all transistors W/L ratios and

spectre simulation of circuit for the following

specifications.

i)

Open loop gain(DC gain) 80 dB

ii) Phase margin 550

iii) PSRR 120 dB

iv) ICMR 150dB

b) Show a biasing circuitry to bias all the voltages in your design (except the input).

c) Use STB analysis to measure the closed loop gain and phase margin.

d) Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain

and phase, CMRR plot, ICMR plot, PSRR plot, slew rate, settling time, Output voltage swing (dc

+ Transient), power consumption, and input and output offset voltage.

Ques 37. Design a wide Swing Folded-Cascode CMOS OTA as shown in figure below;

a) Analysis of all equations of your design, with a

systematic derivative of all transistors W/L ratios and

spectre simulation of circuit for the following

specifications.

i)

Open loop gain(DC gain) 90 dB

ii) slew rate 100V/s

iii) settling time 50ns

iv) Phase margin 600

v) ICMR 2.2 V

b)

c)

d)

Show a biasing circuitry to bias all the voltages in your design (except the input).

Use STB analysis to measure the closed loop gain and phase margin.

Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain

and phase, CMRR plot, ICMR plot, PSRR plot, slew rate, settling time, Output voltage swing (dc

+ Transient), power consumption, and input and output offset voltage.

Ques 38. Design a wide Swing Folded-Cascode CMOS OTA as shown in figure;

a) Analysis of all equations of your design, with a

systematic derivative of all transistors W/L ratios

and spectre simulation of circuit for the following

specifications.

b)

c)

d)

i)

Open loop gain(DC gain) 80 dB

ii) UGB 100MHz

iii) slew rate 50V/s

iv) Phase margin 600

v) settling time 10ns

Show a biasing circuitry to bias all the voltages in your design (except the input).

Use STB analysis to measure the closed loop gain and phase margin.

Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain

and phase, CMRR plot, ICMR plot, PSRR plot, slew rate, settling time, Output voltage swing (dc

+ Transient), power consumption, and input and output offset voltage.

Ques 39. Design a wide Swing Folded-Cascode CMOS OTA as shown in figure;

a) Analysis of all equations of your design, with a

systematic derivative of all transistors W/L ratios

and spectre simulation of circuit for the following

specifications.

i)

Open loop gain(DC gain) 110 dB

ii) Power Dissipation 1mW

iii) Phase margin 600

iv) Output Offset 100mV

b) Show a biasing circuitry to bias all the voltages

in your design (except the input).

c) Use STB analysis to measure the closed loop gain and phase margin.

d) Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain

and phase, CMRR plot, ICMR plot, PSRR plot, slew rate, settling time, Output voltage swing (dc

+ Transient), power consumption, and input and output offset voltage

Ques 40. Design a two stage single-ended output OPAMP(differential +gain stage) for the following

specification

a) Analysis of all equations of your design, with a systematic derivative of all transistors W/L

ratios and spectre simulation of circuit for the following specifications.

b)

c)

d)

i)

DC gain 80 dB

ii)

UGB 400MHz

iii)

Output voltage swing 2V

iv)

PSRR 120dB

v)

Output offset voltage 40mV

Show a biasing circuitry to bias all the voltages in your design (except the input).

STB analysis to calculate the closed loop gain and phase margin for the OPAMP.

Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain and

phase, CMRR plot, ICMR plot, PSRR plot, slew rate, settling time, Output voltage swing (dc +

Transient), power consumption, and input and output offset voltage.

Ques 41. Design a two stage single-ended output OPAMP (Differential + gain stage) for the following

specification

a) Analysis of all equations of your design, with a systematic derivative of all transistors W/L

ratios and spectre simulation of circuit for the following specifications.

i)

DC gain 110 dB

ii)

Power dissipation 0.5mW

iii)

Settling time 60ns

b) Show a biasing circuitry to bias all the voltages in your design (except the input).

c) STB analysis to calculate the closed loop gain and phase margin for the OPAMP.

d) Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain and

phase, CMRR plot, ICMR plot, PSRR plot, slew rate, settling time, Output voltage swing (dc +

transient), power consumption, and input and output offset voltage.

Ques 42. Design a two stage single-ended output OPAMP (Differential stage + a cascode second stage)

for the following specification.

a) Analysis of all equations of your design, with a systematic derivative of all transistors W/L

ratios and spectre simulation of circuit for the following specifications.

i)

DC gain 120 dB

ii)

Output voltage swing 1.5V

b) Show a biasing circuitry to bias all the voltages in your design (except the input).

c) STB analysis to calculate the closed loop gain and phase margin for the OPAMP.

d) Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain and

phase, CMRR plot, ICMR plot, PSRR plot, slew rate, settling time, Output voltage swing (dc +

transient), power consumption, and input and output offset voltage.

Ques 43. Design a two stage single-ended output OPAMP (Differential stage + a cascode second stage)

for the following specification

a)

b)

c)

Analysis of all equations of your design, with a systematic derivative of all transistors W/L ratios

and spectre simulation of circuit for the following specifications.

i)

DC gain 90 dB

ii)

UGB 300MHz

Show a biasing circuitry to bias all the voltages in your design (except the input).

STB analysis to calculate the closed loop gain and phase margin for the OPAMP.

d)

Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain and

phase, CMRR plot, ICMR plot, PSRR plot, slew rate, settling time, Output voltage swing (dc +

transient), power consumption, and input and output offset voltage.

Ques 44. Design a two stage single-ended output OPAMP (Differential stage + a cascode second stage)

for the following specification

a) Analysis of all equations of your design, with a systematic derivative of all transistors W/L ratios

and spectre simulation of circuit for the following specifications.

i)

CMRR 150 dB

ii)

PSRR 140 dB

b) Show a biasing circuitry to bias all the voltages in your design (except the input).

c) STB analysis to calculate the closed loop gain and phase margin for the OPAMP.

d) Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain and

phase, CMRR plot, ICMR plot, PSRR plot, slew rate, settling time, Output voltage swing (dc +

transient), power consumption, and input and output offset voltage.

Ques 45. Design a two stage single-ended output OPAMP (Differential stage + a cascode second stage)

for the following specification

a) Analysis of all equations of your design, with a systematic derivative of all transistors W/L ratios

and spectre simulation of circuit for the following specifications.

i)

-3dB Frequency 100 KHz

ii)

Power Dissipation 1.5mW

b) Show a biasing circuitry to bias all the voltages in your design (except the input).

c) STB analysis to calculate the closed loop gain and phase margin for the OPAMP.

d) Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain and

phase, CMRR plot, ICMR plot, PSRR plot, slew rate, settling time, Output voltage swing (dc +

transient), power consumption, and input and output offset voltage.

Ques 46. Design a CMOS OPAMP.

b) Analysis of all equations of your design, with a systematic derivative of all transistors W/L ratios

and spectre simulation of circuit for the following specifications.

i)

Gain 100 dB

ii)

Settling time 20ns

iii)

UGB 200 MHz

iv)

Slew rate 20 V/s

c) STB analysis to calculate the closed loop gain and phase margin for the OPAMP.

d)

Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain and

phase, CMRR plot, ICMR plot, PSRR plot, slew rate, settling time, output voltage swing (dc +

Transient), power consumption, and input and output offset voltage.

Ques 47. Design a two-stage single-ended output CMOS OPAMP with a UGB of 600MHz and a phase

margin of 600.

(a) Analog schematic for OPAMP (choose appropriate OPAMP).

(b) Analysis of all equations for OPAMP, with a systematic derivation of all transistors W/L ratios.

(Do not use hit-an-trial method)

(c) What is the closed loop gain and phase margin for your OPAMP using STB analysis?

(d) Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain and

phase, CMRR plot, ICMR plot, PSRR plot, slew rate, settling time, output voltage swing (dc +

Transient), power consumption, and input and output offset voltage.

Ques 48. Design a Two stage single-ended output CMOS OPAMP with a -3dB bandwidth of 5MHz.

(a) Analog schematic for OPAMP (choose appropriate OPAMP).

(b) Analysis of all equations for OPAMP, with a systematic derivation of all transistors W/L ratios.

(Do not use hit-an-trial method)

(c) What is the settling time for your OPAMP?

(d) What is the closed loop gain and phase margin for your OPAMP using STB analysis?

(e) Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain and

phase, CMRR plot, ICMR plot, PSRR plot, slew rate, settling time, output voltage swing (dc +

Transient), power consumption, and input and output offset voltage.

Ques 49. Design a fully differential two stage OPAMP (Differential + gain stage) for the following

specification

a) Analysis of all equations of your design, with a systematic derivative of all transistors W/L

ratios and spectre simulation of circuit for the following specifications.

i)

DC gain 100 dB

ii)

Differential Output voltage swing 3.5V

b) Show a biasing circuitry to bias all the voltages in your design (except the input).

c) Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain and

phase, ICMR plot, slew rate, Differential Output voltage swing (dc + Transient), power

consumption, and input and output offset voltage.

Ques 50. Design a fully differential two stage OPAMP (Differential + gain stage) for the following

specification

a) Analysis of all equations of your design, with a systematic derivative of all transistors W/L ratios

and spectre simulation of circuit for the following specifications.

i)

DC gain 80 dB

ii)

Power Dissipation 1mW

b) Show a biasing circuitry to bias all the voltages in your design (except the input).

c) Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain and

phase, ICMR plot, slew rate, Differential Output voltage swing (dc + Transient), power

consumption, and input and output offset voltage.

a) Analysis of all equations of your design, with a

systematic derivative of all transistors W/L ratios and

spectre simulation of circuit for the following

specifications.

i) Open loop gain(DC gain) 80 dB

ii) UGB 100 MHz

iii) Phase margin 600

b) Show a biasing circuitry to bias all the voltages in your

design (except the input).

c) Calculate and plot the following parameters for your

OPAMP: DC gain, Bode plot for AC gain and phase, ICMR plot, slew rate, Output voltage swing

differential (dc + Transient), power consumption, and input and output offset voltage.

Ques 52. Design a folded Cascode OPAMP as shown in figure;

a) Analysis of all equations of your design, with a

systematic derivative of all transistors W/L ratios and

spectre simulation of circuit for the following

specifications.

i) UGB 300 MHz

ii) Power Dissipation 1mW

b) Show a biasing circuitry to bias all the voltages in your

design (except the input).

c) Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain and

phase, ICMR plot, slew rate, Output voltage swing differential (dc + Transient), power

consumption, and input and output offset voltage.

Ques 53. Design a folded Cascode OPAMP as shown in figure;

a) Analysis of all equations of your design, with a

systematic derivative of all transistors W/L ratios and

spectre simulation of circuit for the following

specifications.

i) DC gain 120dB

ii) Differential Voltage Swing 4V

iii) ICMR 2.2V

b) Show a biasing circuitry to bias all the voltages in

your design (except the input).

c) Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain and

phase, ICMR plot, slew rate, Output voltage swing differential (dc + Transient), power consumption,

and input and output offset voltage.

a) Analysis of all equations of your design, with a

systematic derivative of all transistors W/L ratios and

spectre simulation of circuit for the following

specifications.

i) Open loop gain(DC gain) 90 dB

ii) 3dB Frequency 10 KHz

iii) Phase margin 600

b) Show a biasing circuitry to bias all the voltages in your

design (except the input).

c) Calculate and plot the following parameters for your

OPAMP: DC gain, Bode plot for AC gain and phase, ICMR

plot, slew rate, Output voltage swing differential (dc + Transient), power consumption, and input

and output offset voltage.

Ques 55. Design a folded Cascode OPAMP as shown in figure;

a) Analysis of all equations of your design, with a

systematic derivative of all transistors W/L ratios and

spectre simulation of circuit for the following

specifications.

i) DC Gain 100dB

ii) Differential Voltage Swing 3V

iii) 3dB Frequency 1 KHz

b) Show a biasing circuitry to bias all the voltages in

your design (except the input).

c) Calculate and plot the following parameters for

your OPAMP: DC gain, Bode plot for AC gain and phase, ICMR plot, slew rate, Output voltage swing

differential (dc + Transient), power consumption, and input and output offset voltage.

Ques 56. Design a folded Cascode OPAMP as shown in figure;

a) Analysis of all equations of your design, with a

systematic derivative of all transistors W/L ratios and

spectre simulation of circuit for the following

specifications.

i) Differential Voltage Swing 4V

ii) ICMR 2.2V

iii) power dissipation .1mW

b) Show a biasing circuitry to bias all the voltages in

your design (except the input).

c) Calculate and plot the following parameters for

your OPAMP: DC gain, Bode plot for AC gain and

phase, ICMR plot, Slew rate, Output voltage swing differential (dc + Transient), power consumption,

and input and output offset voltage.

a) Analysis of all equations of your design, with a

systematic derivative of all transistors W/L ratios and

spectre simulation of circuit for the following specifications.

i) DC Gain 90dB

ii) Power dissipation .5mW

b) Show a biasing circuitry to bias all the voltages in your

design (except the input).

c) Calculate and plot the following parameters for your

OPAMP: DC gain, Bode plot for AC gain and phase, ICMR plot, Slew rate, Output voltage swing

differential (dc + Transient), power consumption, and input and output offset voltage.

Ques 58. Design a folded Cascode OPAMP as shown in figure;

d) Analysis of all equations of your design, with a

systematic derivative of all transistors W/L ratios and

spectre simulation of circuit for the following

specifications.

iii) DC Gain 80dB

iv) Power Dissipation 0.4mW

e) Show a biasing circuitry to bias all the voltages in your

design (except the input).

f) Calculate and plot the following parameters for your

OPAMP: DC gain, Bode plot for AC gain and phase, ICMR plot, slew rate, Output voltage swing

differential (dc + Transient), power consumption, and input and output offset voltage.

Ques 59. Design a telescopic OPAMP as shown in figure;

a) Analysis of all equations of your design, with a systematic

derivative of all transistors W/L ratios and spectre

simulation of circuit for the following specifications.

i) Open loop gain(DC gain) 80 dB

ii) UGB 200 MHz

iii) Differential Output voltage swing 4V

b) Show a biasing circuitry to bias all the voltages in your

design (except the input).

c) Also calculate the following parameters for your OPAMP: Bode plot for AC gain and phase

margin, slew rate, ICMR, Differential Output Swing (dc + Transient), Offset voltage and power

consumption.

Ques 60. Design a telescopic OPAMP as shown in figure;

a) Analysis of all equations of your design, with a

systematic derivative of all transistors W/L ratios and

spectre simulation of circuit for the following

specifications.

ii) power dissipation 0.1 mW

b) Show a biasing circuitry to bias all the voltages in your design (except the input).

c) Also calculate the following parameters for your OPAMP: Bode plot for AC gain and phase

margin, slew rate, ICMR, Differential output swing (dc + Transient), input offset voltage and

power consumption.

Ques 61. Design a telescopic OPAMP as shown in figure;

a) Analysis of all equations of your design, with a systematic

derivative of all transistors W/L ratios and spectre

simulation of circuit for the following specifications.

i) Open loop gain(DC gain) 100 dB

b) Show a biasing circuitry to bias all the voltages in your

design (except the input).

c) Also calculate the following parameters for your OPAMP:

Bode plot for AC gain and phase margin, slew rate, ICMR,

Differential output swing (dc + Transient), input offset

voltage and power consumption.

Ques 62. To achieve high swing in telescopic OPAMP a student removed the tail current source but at

cost of common-mode rejection and power-supply rejection.

a)

b)

c)

d)

Analysis of all equations of your design, with a systematic derivative of all transistors W/L ratios

and spectre simulation of circuit for the following specifications.

i)

Open loop gain(DC gain) 75 dB

ii)

Output voltage swing 4V

Show a biasing circuitry to bias all the voltages in your design (except the input).

Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain and

phase, ICMR plot, slew rate, Output voltage swing differential (dc + Transient), power

consumption, and input and output offset voltage.

Ques 63. To achieve high swing in telescopic OPAMP a student removed the tail current source but at

cost of common-mode rejection and power-supply rejection.

a)

b)

c)

d)

Analysis of all equations of your design, with a systematic derivative of all transistors W/L ratios

and spectre simulation of circuit for the following specifications.

i)

Open loop gain(DC gain) 70 dB

ii)

UGB 400 MHz

iii)

Output voltage swing 4V

Show a biasing circuitry to bias all the voltages in your design (except the input).

Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain and

phase, ICMR plot, slew rate, Output voltage swing differential (dc + Transient), power

consumption, and input and output offset voltage.

Ques 64. Design a two-stage fully-differential OPAMP (Telescopic + gain stage) for the following

specification

a)

b)

c)

Analysis of all equations of your design, with a systematic derivative of all transistors W/L ratios

and spectre simulation of circuit for the following specifications.

i)

DC gain 100 dB

ii)

Output voltage swing 4V

iii)

-3 dB frequency 5 KHz

Show a biasing circuitry to bias all the voltages in your design (except the input).

Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain and

phase, ICMR plot, slew rate, Output voltage swing differential (dc + Transient), power

consumption, and input and output offset voltage.

Ques 65. Design a two-stage fully-differential OPAMP (Telescopic + gain stage) for the following

specification

a) Analysis of all equations of your design, with a systematic derivative of all transistors W/L

ratios and spectre simulation of circuit for the following specifications.

i)

UGB 600 MHz

ii)

Phase margin 600

iii)

Settling time 20ns

b) Show a biasing circuitry to bias all the voltages in your design (except the input).

c) Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain and

phase, ICMR plot, slew rate, Output voltage swing differential (dc + Transient), power

consumption, and input and output offset voltage.

Ques 66. Design a two-stage fully-differential OPAMP (Telescopic + gain stage) for the following

specification

a) Analysis of all equations of your design, with a systematic derivative of all transistors W/L

ratios and spectre simulation of circuit for the following specifications.

i)

Gain 90 dB

ii)

UGB 100 MHz

iii)

Phase margin 600

iv)

Differential output Swing 3.5 V

b) Show a biasing circuitry to bias all the voltages in your design (except the input).

c) Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain and

phase, ICMR plot, slew rate, Output voltage swing differential (dc + Transient), power

consumption, and input and output offset voltage.

Ques 67. Design a two-stage Fully-Differential OTA (Folded Cascode [Differential amplifier + common

gate stage] + gain stage).

a) Analog schematic for OTA.

b) Analysis of all equations for OTA, with a systematic derivative of all transistors W/L ratios and

spectre simulation of circuit for the following specifications.

i)

UGB 400 MHz

ii)

Phase margin 550 - 650

iii)

Output voltage swing differential 3V

c) Show the biasing circuitry to bias all the voltages in your design (except the input).

d) Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain and

phase, ICMR plot, slew rate, Differential Output Swing (dc + Transient), power

consumption,

and input and output offset voltage.

Que68. Design a two-stage Fully-Differential OTA (Folded Cascode[Differential amplifier + common gate

stage] + gain stage).

a) Analog schematic for OTA.

b) Analysis of all equations for OTA, with a systematic derivative of all transistors W/L ratios and

spectre simulation of circuit for the following specifications.

i)

Gain 80 dB

ii)

Phase margin 600

iii)

Power dissipation 0.5mA

c) Show the biasing circuitry to bias all the voltages in your design (except the input).

d) Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain and

phase, ICMR plot, slew rate, Output voltage swing differential (dc + Transient), power

consumption, and input and output offset voltage.

Ques 69. Design a two-stage Fully-Differential OTA (Folded Cascode[Differential amplifier + common

gate stage] + gain stage).

a) Analog schematic for OTA.

b) Analysis of all equations for OTA, with a systematic derivative of all transistors W/L ratios and

Spectre simulation of circuit for the following specifications.

i)

DC Gain (Open Loop) 100 dB

ii)

UGB 100MHz

iii)

Phase margin 550 - 650

c) Show the biasing circuitry to bias all the voltages in your design (except the input).

d) Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain and

phase, ICMR plot, slew rate, Output voltage swing differential (dc + Transient), power

consumption, and input and output offset voltage.

Ques 70. Design a two-stage Fully-Differential OTA (Folded Cascode[Differential amplifier + common

gate stage] + gain stage) for the following specifications;

a)

b)

c)

Analysis of all equations of your design, with a systematic derivative of all transistors W/L ratios

and spectre simulation of circuit for the following specifications.

i)

DC gain (Open Loop) 120 dB

ii)

Differential Output swing 2.5V

Show a biasing circuitry to bias all the voltages in your design (except the input).

Calculate and plot the following parameters for your OPAMP: DC gain, Bode plot for AC gain and

phase, ICMR plot, slew rate, Output voltage swing differential (dc + Transient), power

consumption, and input and output offset voltage.

Common Simulations

The following simulations need to be done for all classes of circuits:

1. Performance Evaluation at:

VDD+10%, FF Corner, Minimum Resistance Corner, 00C

VDD-10%, SS Corner, Maximum Resistance Corner, 1000C

Submission Dates

Assignment Submission

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