VHDL Exercises for Computer System Organization Course

1)

Get the exposure of Modelsim-Altera VHDL simulator. Model a simple AND gate using dataflow
modeling. Write the testbench to test the system. Verify the functionality from the output waveform.

2)

(a) Model a 1-bit Fulladder using dataflow modeling. Use this to build an 8-bit ripple carry adder using
structural modeling.
(b) Implement a 4-bit adder using + operator for std_logic_vector data types. Use this to build a 1-digit
BCD adder.
(c) Use for generate statement to implement Part (a).
(d) Implement an Array Multiplier to multiply two 8-bit numbers using the 8-bit fulladdders.

3)

(a) Implement a 2-to-4 Decoder using conditional signal assignment statement with enable facility. Use it to
construct a 4-to-16 decoder.
(b) Model a 4-to-1 multiplexor using Selected Signal Assignment statement. Use it to build 16-to-1
multiplexor.
(c) Implement a 1-bit comparator having 5 inputs (two 1-bit inputs being compared and three 1-bit
comparison result bits of previous stage) and 3 outputs (namely eq, lt, gt). Connect 8 such units to model an
8-bit comparator using generate statement. The 3 outputs of a stage go to its next stage as inputs.

4)

Implement an 8-bit Arithmetic Logic Unit to perform basic arithmetic (add, sub, inc, dec) and logical (or,
and, xor, not) operations using structural modeling that uses a component of 1-bit fulladder and
multiplexor.

5)

Model a combinational circuit in VHDL that performs either shift left, or shift right, or rotate left or rotate
right by 1-bit operations on its input. Do not use the predefined gates/shift/rotate operators.

6)

Model an S-R flip-flop using structural modeling using programmer-defined NAND gates as components.

7)

Model an edge triggered D flip-flop with asynchronous reset facility. Use it to model 8-bit Parallel-InParallel-Out register. Now add preset facility to the DFF and use it to model a Ring Counter.

8)

Implement a Serial Adder using a D flip-flop and a fulladder.

9)

Model a T flip-flop. Use it model a Mod-10 Up-Down counter.

10)

Implement an n-bit Shift-left register using generic facility of VHDL.

11)

Implement the Booths Multiplication Algorithm, Restoring Division Algorithm in VHDL.

12)

Implement a Register file of 8-bit wide 16 registers with two read ports and a write port.

13)

Implement a 3-bit Gray Code counter using Finite State Machine modeling method.

14)

Model a Moore machine based circuit having single serial input and a single output that gives an output 1
whenever it detects 0101 bit sequence in its input stream.

15)

Implement a 16 byte ROM with some predefined data in its locations.

16)

Implement a 1Kx8 RAM with bidirectional data lines.