Impacts of Inverter-based Distributed Generation

Control Modes on Short-circuit Currents in

Distribution Systems
Dao Van Tu

Surachai Chaitusaney

Department of Electrical Engineering

Chulalongkorn University
Bangkok, Thailand
tudv-htd@mail.hut.edu.vn

Department of Electrical Engineering

Chulalongkorn University
Bangkok, Thailand
surachai.C@chula.ac.th

AbstractWith the rapid increase in using New/Renewable

Energy Resources, Inverter-based Distributed Generations
(IBDG) are more and more widely installed in electric power
systems. However, the limited short-circuit current contributed
from these generators should be noted for the operation of the
protection systems. This paper analyzes the changes of shortcircuit currents in distribution system with the penetration of
IBDG and illustrates how the inverter control modes affect the
response of the IBDG. Then, an adaptive algorithm is proposed
for short-circuit currents calculation. A simulation in
Matlab/Simulink environment comprehensively compares the
changes of short-circuit current in the system before and after
installing IBDG as well as verifies the proposed algorithm.
Keywords- Inverter-based distributed generation; short-circuit
currents; inverter controller

I.

INTRODUCTION

The use of new/renewable (NRE) resources has been

increasing recently. For instance, the total power of power
plants using NRE is about 1000 (MW) in Thailand in 2011
and will be 6500 MW in the future [1]. Distributed Generation
(DG), a popular solution in using NRE, produces sustainable
electrical energy to power systems. Additionally, high
technology in power electronics (rectifiers, inverters...) can
improve the quality of DG as long as the generated electricity.
As one kind of this application, the Inverter-based Distributed
Generation (IBDG) converts the direct current (dc), which can
be directly or indirectly produced from NRE, to the alternative
current (ac) by an inverter. This DG type is flexible in control
with high efficiency [2]. However, the introduction of IBDG
requires some new solutions to solve the steady as long as the
transient state of the power systems. This paper concerns the
short-circuit current changes in the power systems during the
transient state due to the short-circuit problems.
Unlike the conventional synchronous generator, the
response of IBDG to a short-circuit is very fast and it may
depend on the control system [3]-[5]. However, model of
IBDG and algorithm for fault calculation still challenge
researchers. This paper first discusses about the control modes
of IBDG in Section II. Based on these modes, fault responses
of IBDG are analyzed in Section III. Then, an adaptive

c
978-1-4577-2119-9/12/$26.00 2011
IEEE

algorithm is proposed for fault calculation. In Section IV, a

Matlab/ Simulink simulation is applied to a simple system for
analyzing the fault response of IBDG as well as verifying the
proposed algorithm.
II.

CONTROL MODES OF IBDG

This section discusses about two main control modes of

IBDG: power control and voltage control. The former is
usually used in grid-connected condition of IBDG and the latter
is used in islanding condition where IBDG is the unique source
supplying to all loads in the system.
A. Power control mode
In practice, new or renewable energy is used to produce dc
power directly (fuel cell, photovoltaic) or indirectly (wind
turbines, micro-turbines). The dc voltage is then converted via
an inverter to three-phase ac voltage. Generally, the dc voltage
is assumed to be constant during short transients. The
controller on the inverter regulates the output complex power
around a desired set point. Fig. 1 depicts the structure of a
controller implemented in the Natural Reference Frame (NRF)
for a three-phase three-leg inverter.
The output LC filter is there to filter out the undesired
switching frequency components from the output current
spectrum. The inclusion of the LC filter makes more difficult
the controller design and controller parameters adjustment.
However, empirical parameters are selected for the filter in
this research, since the design output LC filter is out of scope
of this paper.
The power injected in bus p is desired to be around a set
point (Pref, Qref). Thus, after transforming output currents
(Iinv,abc, Ip,abc) and voltage (Vp,abc) in abc coordinates into dqo
coordinates, they are used to perform the reference inverter
output current Idqinv,ref by the power controller. This current is
then transformed into abc coordinates. All transformations are
used the fundamental frequency generated by PLL (PhaseLocked Loop) from grid voltage to synchronize the inverter
outputs with the grid. Using (Iabcinv,ref, Iinv,abc, Vp,abc), the current
controller generates the reference input voltage UabcPWM,ref for
the PWM (Pulse Width Modulation) generator which controls

1645

I pd ,ref
d

1
V pq

2 Vp

3 V pq V pd

Pref

Qref

d
Iinv
, ref

d
Iinv

I dp

I qp ,ref

q
Iinv
, ref

q
Iinv

abc
U PWM
, ref

I qp

Fig. 2 Power controller structure

abc
Iinv
, ref

( Iinvd ,ref ) + ( Iinvq ,ref )

2

dq
I inv
, ref ,lim

dq
I inv
,ref

dq
I inv
, ref

dq
Iinv
,ref ,lim

dq
Iinv
, sat

Fig. 1 Power controlled mode of grid-connected IBDG

switching signals of inverter to create the desired output power

More details of the control system are discussed as follows.

Fig. 3 Current limiter in the SRF

abc
U PWM
, ref

abc
I inv
, ref

Power controller
By using the set point of output power and the feedback
voltage, the reference current is computed in the Synchronous
Reference Frame (SRF) as shown in Fig. 2.
In the SRF, the reference current is calculated from the
reference three-phase complex power by (1).

I dp ,ref

q
I p ,ref

2
=
3 Vd

V pd

V pq

( ) ( )
2

+ V pq

V pq Pref

V pd Qref

(1)

Because the inner control loop (the current control loop) in

Fig. 1 uses the output current of inverter through the inductor
Iinv, the reference value Idqinv,ref is performed by (2).
d
I inv
, ref

q
I inv , ref

I dp , ref
=
I qp , ref

I d I pd
+ inv
q
I inv
I qp

2 f c
=
+
s
2 f c

I dp ,ref

q
I p ,ref

I d I dp
+ inv
q
I inv
I qp

(3)

With this filter, components that have the frequency of 2 in

Idqinv,ref determined by (2) and caused by the negative-sequence
are filter out. Additionally, the zero-sequence components are
not considered here if three-phase three-leg inverter is used.
Thus, the output signals of power controller are clean dc
currents derived from positive-sequences of Vp,abc, Ip,abc, and
Iinv,abc.
Current limiter

1646

V pabc

Fig. 4 Current controller structure

Inverters are usually designed to supply a maximum

current of typically only twice their nominal values in the
event of a network fault. This can be implemented by using
the current limiter as illustrated in Fig. 3.
Under normal condition, the switch is closed on position
N. When a fault occurs, as soon as one component of Idqinv,ref
reaches the limit Ithres in the saturation block, the switch is
closed on L by set/reset signal. It goes back to N after the
fault is cleared and the system goes back to the normal
operation.
Current controller

(2)

To limit the power controller bandwidth and to filter out

harmonic content from the voltage current spectrum (under
unbalanced conditions), a low-pass filter is applied. The filter
cut-off frequency fc must be satisfied for providing both
sufficient suppression of voltage harmonics and unbalance and
quick enough response of power control loop. Assuming that
the first order low-pass filter with fc is used, the reference
output of power controller is determined by (3) instead of (2).
d
I inv
, ref

q
I inv,ref

abc
I inv

The control in the NRF is straight forward for

understanding and implementing. Although it has poor control
performance with sinusoidal control signal in using with PI
controller, the zero steady-state error is still achieved in using
P+Resonant regulators [6]. The transfer function of this
regulator is defined as (4).

GPR = k p +

2ki
s + 2
2

(4)

The first term in (4) is a proportional gain which is in the

same way as in PI controller. The second term is a second
order generalized integrator which achieves very high gain in
a narrow band center around . Therefore, is usually called
resonant frequency. In this paper, it is the fundamental
frequency (250 rad/s). Then, the feed-forward voltage Vpabc is
applied to generate the reference voltage for the PWM
generator. The structure of the current controller is depicted in
Fig. 4.
B. Voltage control mode
In case of islanding operation, the inverter is the unique
source in the microgrid. Its primary role is to maintain the sup-

2012 7th IEEE Conference on Industrial Electronics and Applications (ICIEA)

abc
U PWM
, ref

V pabc
, ref

V pabc

I abc
p

abc
I inv
, ref

abc
I inv
, ref ,lim

Fig. 5 Voltage control mode

Ithres
Set

-Ithres
abc
Iinv
, sat

abc
Iinv
, ref

abc
I inv
, ref , lim

L
N

Reset

Fig. 6 Current limiter in the NRF

plied voltage and frequency in the system. Thus, the inverter

should be controlled as a slack bus. That is, its voltage is
constant in both magnitude and phase. The choice of multiloop control structure with an outer voltage loop and an inner
current loop has become popular and frequently adopted for
controlling the inverter [7]. Because both loops are controlled
in the NRF, it is simpler if the current is also limited in the
NRF instead of in SRF in Subsection II.A. Therefore, the
structure in Fig. 5 can be applied to control the inverter in the
NRF.
The current controller is the same as in Subsection II.A. A
portion of current Ip,abc is feed-forwarded though the factor F
(0 F 1) to improve the dynamic performance and the
stability of the inverter [8].
Current limiter in the NRF

The phase inductor currents are instantaneously limited

and the resultant distorted waveforms may contain third
harmonic component. However, an advantage of this method
is that there are no any transformations in need. The structure
of the current limiter in the NRF is depicted in Fig. 6.
III.

FAULT RESPONSE OF IBDG

When a fault occurs in the system side, bus voltages go

down and may be unbalanced. Thus, currents contributed by
the IBDG are changed to maintain the desired output (power
output or terminal voltage). The following sections will
discuss the fault response of the IBDG in corresponding to the
control mode of its inverter.
A. Fault response of IBDG in the PQ control mode
With the control system discussed in Subsection II.A,
under normal condition, IBDG can be represented as a PQ
source. When a fault occurs in the network, changes of the
voltage at the connected bus (Bus p in Fig. 1) mainly depend
on type, location, impedance of fault, and line parameters.
Despite the unbalance voltage and current, the inverter
responds to the positive-sequence component only. To remain
the power injected into Bus p, the current through the inductor
is controlled to achieve the reference current determined by
(5).
Phase currents of Iinv,ref include rich positive-sequence
components resulting in well balanced phase currents of Iinv
despite unsymmetrical faults in the network.

Fig. 7 Model for IBDG under fault conditions

I inv,ref =

Pref jQref
3V p*

+ jC f

Vp
3

(5)

If the changes of Vp involving high Iinv,ref cause the dq

reference of Iinv to reach Ithres in Fig. 3, phase currents of Iinv
will have a fixed magnitude even that the output power is not
around the set point.
After all, IBDG can be represented as a constant PQ source
or a constant current source depending on the relation between
Iinv,ref and Iinv,thres as illustrated in Fig. 7.
Note that this model is used for only the positive-sequence
network. The IBDG does not support currents for negativesequence and zero-sequence network. Using this model, the
positive-sequence fault currents in the network can be
calculated by utilizing load flow algorithm as proposed in
Subsection III.C.
B. Fault response of IBDG in the voltage control mode
During faults, the inverter is controlled individually in each
phase because of the current limiter in the NRF. Thus there is
no overvoltage on healthy phases during unbalanced faults and
the healthy phase voltages are kept at the preset value. It will
bring about the higher quality to single phase customers.
On the other hand, if the instantaneous current in each
phase is limited, the distorted waveforms will be produced in
case of big voltage dips due to faults. Fig. 8 illustrates the
distorted waveform of current from IBDG due to a single line
to ground fault.
Recent academic studies have proposed models for IBDG
in case of voltage controlled mode [9]-[10] with a good
accuracy. For instance, in [10], the authors proposed to
represent IBDG as a constant current source in relation to the
transfer function of the control system in inverter-only
microgrid. Unfortunately, this method cannot be applied to PQ
controlled mode in case of grid-connected IBDG. However,
the model in Subsection III.A can be used to integrate IBDG
in fault calculation program by the proposed algorithm as
follows.
C. Algorithm for fault current calculation program
As proposed in Subsection III.A, grid-connected IBDG at
Bus p is represented as a constant PQ source or a constant
current source in corresponding to the changes of Vp. Thus, the
system equation in fault duration is illustrated in (6) with all
elements in per unit.

2012 7th IEEE Conference on Industrial Electronics and Applications (ICIEA)

1647

Single line to ground fault

Phase A

Va1

Va0

Va2

Phase B Phase C

Fig. 9 Sequence network connection for double line to ground fault

Fault
instant

Form bus admittance matrix Ybus

Assume bus voltages V(0)
p=1,2,...,n ps (slack bus)

Fig. 8 Response of IBDG to a single line to ground fault (voltage controlled in

NRF)

Pp jQ p
V p*

= V pYpp +

q =1, p q

YpqVq

Set iteration count k=0

and maximum voltage change maxVk=0

p = 1, n q p (6)

In (6), Ypp and Ypq are elements of the bus admittance

matrix Ybus. The formulation Ybus is based on the positivesequence network with extra impedances at the fault point.
These impedances depend on the fault types, negative and
zero-sequence networks [11]. All synchronous generators
must be represented by a constant voltage source in series with
the machine impedance; the slack bus is in series with the
short-circuit impedance of the system source and all loads
should be modelled as constant impedances. Fig. 9 represents
the sequence-network connection in case of double line to
ground fault.

k=k+1
Bus count p=1

PV bus?
Yes

Q kp +1 = imag V p*

( )

I abc = AI 012

(7)

a ,

a2

1
3
a= + j
2
2

(8)

IV. CASE STUDY

In this section, a simulation in Matlab/Simulink
environment is first applied to show the changes of fault
currents due to interconnecting IBDG to a simple system
depicted in Fig. 11. Then, the algorithm proposed in
Subsection III.C is applied. Results from this application will
be compared with the time-variant results from the Simulink

1648

n
k
k
V p Y pp + Y pqVq
q =1

p q

slack bus?
Yes

Current source bus?

I inv,ref I thres ?

No

Yes

n
1 Pp jQ p p 1

YpqVqk +1 YpqVqk
V pk +1 =
Y pp V * k
q =1
q = p +1

( )

Calculate change in
voltage of bus p?
V pk = V pk +1 V pk

V pk +1 =

V pk > max V k ?

p 1
n

1
I inv, sat YpqVqk +1 YpqVqk

Y pp
q =1
q = p +1

Yes

Set max V k = V pk

No
p=p+1
The end bus?
p > n?
Yes

No

Replace V pk by V pk +1
p = 1, n p s

Yes

Test for convergence

max V k > ?

No

Calculate positivesequence voltages at all

buses and sequence
currents at the fault point

Fig. 10 Algorithm for fault calculation (applied for sequence network

connection)

where A is the transformation matrix as shown in (8).

1 1

A = 1 a 2

1 a

Yes

Q p = Q pk +1

To solve (6), Gauss-Seidel method can be used. The

algorithm depicted in Fig. 10 is the same as a load flow
program except that the limit of supplied current from inverter
is considered.
At inverter bus (Bus p), the reference current Iinv,ref is
calculated at every iteration. Once it reaches the threshold,
Bus p is switched to a constant current source with the injected
current Iinv,sat. Then, all sequence components of current and
voltage are calculated. Phase currents and voltages are
calculated by (7).

PQ bus?

simulation. The simple system has one IBDG connected to

Bus 4, which is the low voltage bus of a step up transformer.
More details of this system as well as the IBDG are listed in
Appendix.
A. Results from Matlab/Simulink simulation
In this simulation, load is represented by constant
impedance at the nominal voltage. At time t = 0.2 (s), a double
line to ground fault occurs at Bus 3 through an impedance ZF =
10 (). Fig. 12 illustrates faults current at the fault point
before and after installing the IBDG at Bus 4.
It can be seen that the fault currents are higher after install-

2012 7th IEEE Conference on Industrial Electronics and Applications (ICIEA)

TABLE I. RESULTS FROM THE PROGRAM USING THE PROPOSED ALGORITH

Bus 1

VApositive p.u.

Bus 2

0.820.02

Currents at Bus 3, p.u.

I Apositive

I Azero

0.472.99

Bus 3
rad

rad

4.48 0.98

Bus 4

0.42 0.06

rad

I Anegative
rad

0.81 0.39rad
IF

4.182.08

rad

1.412.99rad

ing IBDG. However, the increases are small (48.8 (A) in phase
B and 48.15 (A) in phase C) because the power of IBDG is
small and the contributed current is limited due to the current
limiter in the control system of the IBDGs inverter. The peak
values of fault currents after installing IBDG are 1090 (A) in
phase B and 945 (A) in phase C.
It is noted that during the unbalanced fault, phase currents
contributed by IBDG are still symmetrical with the peak phase
value of 2300 (A) as shown in Fig. 13. This is because the
inverter responses to only the positive-sequence component of
the voltage at Bus 4. Additionally, the inverter current is
limited in the SRF.
B. Results from using the proposed algorithm
The equivalent negative and zero-sequence impedances of
the system viewed from Bus 3 are identical to (0.05+j0.08)
p.u. According to the sequence network connection in Fig. 9,
these two impedances and three times of the fault impedance
(3ZF) can be replaced by an equivalent impedance of
(0.06+j0.07) p.u. It is connected to the faulted bus (Bus 3) in
the positive-sequence network for applying the algorithm in
Fig. 10. To easily compare with the results from the simulation
in Subsection IV.A, the load is also modeled as a constant
impedance with respect to the nominal voltage. Results
obtained from the program, that uses the proposed algorithm,
are tabulated in Table I.

Fig. 11 Simple system with the installation of IBDG

Fig. 12 Fault current changes due to installing IBDG

Voltages of phases B and C at Bus 3 are computed from

the current IF through the fault impedance ZF. That is, VB and
VC are identical to 1922 (V) in phase peak value. By using (7),
fault currents of phases B and C are 1094 and 948 (A) in peak
value, respectively.
The current from IBDG (through the filter inductance),
computed from the positive-sequence voltage at Bus 4 (in
Table I) by using (5), is 2216 (A) in peak value.
In comparing the results between Subsections IV.A and
IV.B, fault currents and currents contributed from IBDG
obtained by using the proposed algorithm are close to the
results from the simulation (Fig. 12 and 13).
V.

CONCLUSION

Simulation results show that fault responses of IBDG

depend on their control modes. Generally, fault currents
contributed from a small IBDG may be not significant and can
be neglected in fault calculation. However, in case of high
penetration of these generators, the difference of fault currents
before and after installing IBDGs should be taken into
consideration. In case of the power control mode, IBDG is
modeled as a PQ source or a constant current source and the

Fig. 13 Currents from IBDG during double line to ground fault

proposed algorithm can be applied to calculate fault current in

the system with a good accuracy.

2012 7th IEEE Conference on Industrial Electronics and Applications (ICIEA)

1649

APPENDIX
Parameters of the simple system in Section 4:

Grid: V1 = 6 kV, Zsc,grid = 0, Zline1= 0.75 + j1.26 (),

Zline2 = 2Zline1, Pload + jQload = 1 + j0.5 (MVA).
Transformer: 0.80 (MVA), 6kV/315V, Yn/D11, R
= 0.002 p.u, X = 0.08 p.u (in transformer rating).
IBDG: Pref = 0.75 (MW), Qref = 0 (MVAr), Iinv,thres
= 2 p.u., Iinv,sat = 2 p.u., (in IBDG rating), Cf = 200
(F), Lf = 0.1(mH).
ACKNOWLEDGEMENTS

This work was supported by the Higher Education

Research Promotion and National Research University
Project of Thailand, Office of the Higher Education
Commission (EN262A).
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2012 7th IEEE Conference on Industrial Electronics and Applications (ICIEA)