TD-CAD Tasklist 20151113

Project
ESF3-110LFA
ESF3-55XMC
ESF3-90ATZ
ESF3-90MKN
ESF3-55GFS
ESF3-55UMC
ESF2-130LAP
ESF1-130GFS
ESF1-180SLT
ESF3-40UMC
ESF3-110REN
ESF3-65TID
ESF3-65TBS
PDK.Flow
DTC.Compiler
WAT.Compiler
ESF3-28UMC
ESF3-28GFD
ESF3-40GFS
ESF1-130CSMC
Training
NA
Project.Code
Amber
Coral
Diamond
Emerald
Garnet
Jade
Opal
Onyx
Pearl
Quartz
Ruby
Zircon
Sapphire
PDK.Flow
DTC.Compiler
WAT.Compiler
ESF3-28UMC
ESF3-28GFD
ESF3-40GFS
ESF1-130CSMC
Training
NA
Program.Manager
XL
XL
JS
JS
YC
WY
LC
LC
LC
JK
YC
JK
YC
Flash.Gen
ESF1
ESF2
ESF3
Technology
180
130
110
90
65
55
40
28
Foundry
Amstrong
Global Foundry
Lapis
L-Foundry
Mikron
NationZ
Renessas
Silterra
SMIC
Texas Instruments, Inc.
Toshiba
TSMC
UMC
XMC
Foundry.Short.Name
ATZ
GFS
LAP
LFA
MKN
REN
SLT
TID
TBS
UMC
XMC
Program.Manager
Nhan Do
Liz Cuevas
Yueh-Hsin Chen
Will Yang
Xian Liu
Jinho Kim
Jack Sun
Initial.Name
ND
LC
YC
WY
XL
JK
JS
Task.Status
In.Planning
In.Progress
In.Reviewing
Completed
Cancelled
Postponed
Task.Priority
Critical
Normal
Low
TDCAD.Member
Nitya
Khoe
Tri
Thanh
Duong
Hoang
Binh
PDK.Component
Converted.Layout.Lib
Converted.Schematic.Lib
Cover.Sheet
Device.Library
DRC.Deck
Foundry.PDK
Gate.Library
Internal.Design.Doc
Layout.Compiler
Layout.Library
LEF
LVS.Deck
NA
PDK.Flow
PDK.Install.Hspice
Layout.Router
PDK.QA
PEX.Deck
Pregen.Deck
Schematic.Library
Scripts
SPICE.Library
SST.PDK
Tape.Out
Tech.Files
Unix
Semi.Tech
Programming
Task
Implement PDK compare_db command
Implement PDK db2db command - phase2 Schematic Conversion
Review and improve genLVS.pl tool

Generate the top bank array for pfm_390t16kx72_v1a0 IP
Description
Compare two specified databases: SVS, LVL, LVS, cellname vs cellname
Implement a command-line script to port a database from a specified PDK to
another:
1. Migrate a layout/schematic database from PDK to PDK:
1.1 Build layermap/devicemap file automatically
2. Copy a layout/schematic database follow Pixy's requirements
Generate the top bank array for pfm_390t16kx72_v1a0 IP
Accomplishment
Plant
Project.Code
PDK.Component
Status
Priority
PDK.Flow
NA
In.Planning
Normal
PDK.Flow
Converted.SchematicIn.Progress
Normal
PDK.Flow
PDK.Flow
In.Planning
Normal
tsmc90ce3p6msp013mim1p5_4X1PDK.Flow
Completed
Critical
review and improve my function

use to prepare database for
conversion
review function use to parse excel file from thanh
create first revision for schematic conversion
Owner
Target
Actual
Comments
Hoang
11/30/2015
Hoang
Hoang
Hoang
Generate top
array for
pfm_390t16k
11/16/2015 x72_v1a0 IP
created skill functions use to

prepare database for
conversion
Task
pdk gen command
Build DRC deck
Build LVS deck
Build the layout example to verify LVS deck
Check if stopLayer can be derived layer
Develop a test-line compiler
Develop XLS-based MOS transistor compiler
pdk init/update/install commands
Implement "pdk pccompile" command to compile HV pcells
Release PDK r1.0
Understand ESF1/ESF3 compiler and create the detail userguide document
Layout/Sch Converting Tool -- Feedback
Update pdk compile command to add DRC/LVS running feature
Review ESD/Seal ring/PAD layout in esf3-55umc and pdkumc55eflash
Review and update esf3-55UMC LVS deck to use the tight checking approach
Implementing code to check missing parameters in netlist
ESF3 Compiler Review

Review 28umc HKMG array and upgrade the compiler to support generating
HKMG cells
All_device example is LVS/DRC clean (include

LVMOS/HVMOS/diode/res/probecell/momcap/moscap with min design rule)
Implementing PEX rule deck
Update techfile to support LEF generation
Add Bondpad/sealring/ip phantom/revid/iptag/esdpad layout example
Generate Mini array layout with LVS/DRC clean
Support generate WATs
Build Schematic for WAT spines
Setup PDK with HV/Superflash layers
Convert 55UMC pfm_355u64kx144_v1a2/tc_355u64kx144_v1a2 database to 40
Update the pregen to generate dummy block layers
Install the dummy fill code and verify the tapeout flow
Update pregen to generate layer in
MPW033C_Layer_List_SLPFEOL_6220_WB_FC_NVM_r04_SST
Update pdk ci command to update techfile.tf and display.drf files
Install the new version of foundry PDK DK1.2 and fix probecell issue
Upgrade lypgen tool to support generating layer-property file for Klayout
Update "Refresh CDF Instance Parameters" tool to support the order of parameters
Build Horizontal/Vertical Adjacent Tile Graphs
Implement a path path propagation for a multiple width net
Hi Tri,
This is the feedback to speed up the task of creating device map files for
Description
schematic conversion. This could
be included in the Sch conversion tool, or
a standalone utility.
i. Implement HV LVS rule deck template.
ii. Implement python-based functions to parse Calibre rule desk files.
Phase 1:
1)
Users just
provide
the <src_sch_lib>
Implement
HV
+ memory
design rules to convert, nothing else.
2)
The
tool
scans
through
<src_sch_lib>
and provide
map file
M1 of
i.
Inputs:
pad
cell,
pad
array info
(X*Y),
test-line
size, an
cellinitial
placement
info
Install
LV
deck
and
implement
HV
LVS
deck
the
form:
(each
cell will have pin info), cell DR tables (i.e. a table from MOS compiler),
Create
cells
routing Techprimitive_devices
info (i.e. min metal width/spacing,
if users do not enter then get
(nil
map
from the tech file)
(ii. Output:
<D_TLIB1>
Layout:(<tlib1>
cells are placed among the pads and routing
is done between
<cell1>
<D_CELL1>
ii.
PDK
r1.0
(for
TC1
and
later)
pads and cell pins using Space-Base Router.
<D_CELL2>
Supporting
pinaobjects
objects
defined
bycould
Cadence
Space-Base
Router,
1.
model:
wait<cell2>
for(pin
Mandana
SPICE
Schematic:
simple
schedule
(cell
symbol
be from
a fixed library,
..
should
generic term of Cadence)
2.
DRC:
such
asbe
HVa library)
)
a.
LV:
from foundry: are clean LVS
Layout/schematic
Compare
two
specified
databases:
SVS, LVL, LVS,<D_TLIB2>
cellname vs cellname
(<tlib2>
b. HV: initial
copied
from
GFS40
<cell3>
<D_CELL3>
c.
cell:
initial
from -->
UMC28
1. Mem
Review
pcell
CDFcopied
interfaces
create the best interface for our HV pcell
Implement
the flow
of
these
commands
<cell4>
<D_CELL4>
3.
LVS:
devices
..
a.
from foundry
2. LV:
Implement
SKILL pcell template file
)
b.
HV/mem:
copied
fromthe
GFS40
3. ImplementInitial
Python
to parse
Excel template file to generate the pcell
)4. PEX: TBD
code files
)
Phase 2:
1) Users will fill out the upper case variables in the initial map <D_TLIB1>,
<D_TLIB2>, <D_CELL1>, etc. to create map M2
a.
If users
docompile
not update
all <D_CELLn>
listed, running
then popfeature
up a GUI to confirm
Update
pdk
command
to add DRC/LVS
and continue to run without stop. This has been discussed already.
2) Based
on the ring/PAD
update map
the tool willand
scan
the <src_sch_lib> and
Review
ESD/Seal
layoutM2,
in esf3-55umc
pdkumc55eflash
The tight checking approach for LVS deck by following the truth table:
<D_TLIB1>, <D_TLIB2> etc. and provide a more detail map M3
1. ONE marked layer have to be implemented as AND
a.
Internally, the tool will try to guess the type of each cell <D_CELLi>
2. ZERO marked layer have to be implemented as NOT
i. If a cell has 4 pins and one pin name is G or GATE it is a transistor
ii.
If a cell has 2
or 3to
pins,
onemissing
pin named
P or PLUS,
one pin named M
Implementing
code
check
parameters
in netlist
or
MINUS,
and
a
parameter
named
R
or
Rsheet
or
segR
it isPDK
a to
Implement a command-line script to port a database from a specified
resistor.
another: If not, it is a capacitor
iii. Migrate
Else, it is
1.
a generic_device.
layout/schematic database from PDK to PDK:
iv. 1.1
Cadence
category
file <lib>/*Cat
be used to detect device type
Build layermap/devicemap
filecould
automatically
ESF3
Compiler
b. Copy
Based
theReview:
type detected,
more details
for mapping
each device could
2.
aon
layout/schematic
database
follow Pixy's
requirements
Collect
all to
feedbacks
about the ESF3 compiler, all need to have features
be added
create M4:
which
already
unsupported,
then hold a meeting to review
i. Example:
forsupported
transistor or
(similarly
for res/cap)
that,
so
that
we
can
plan
to
implement
that
or
improve
flow
1.
Only
need
to
map
KEY
set
of
parameters
l, m} to
{fw,
nf=1,
fl, m} or
Review 28umc HKMG array and upgrade the{w,
compiler
toour
support
generating
the other
way around
HKMG
cells
2. w could be mapped to fw and set nf=1. And convert data type (e.g.
string <-> float) also
3. If pin names are different (e.g. G v.s. GATE) then add mapping for them
c. Special case: the instance parameter model should be deleted.
After phase 2, the map would be >95% correct and users can wrap it up for
Below is the PEX files for LV just downloaded:

/iplicense/cad/technology/pdkchrt40lp/opus61/designkit/foundry/EDA-CADAll_device
example is LVS/DRC clean (include
40N-EX006/V1.3_1.0_BASE
Refer to the following file to define full function to extract parameters for
PEX:
/iplicense/cad/technology/esf3-55gfs/ch55lpeUpdate
techfile to support LEF generation
a/designkit_r2.1a/run/pex/LVS/Include_SST/esf3-ch55lpea_pex_devices_hv.inc
Look at the function DMACRO SST_FET_PROPERTIES.
1. Build other spines based on Xian/Jinho's requests
Setup
PDKDIFF
withdummy
HV/Superflash
layers within 2.0um/side from HNWL(QZ),
- Exclude
fill generation
HPWL(QY) and MCEL(CW) and
-Convert
Prohibit55UMC
DIFF dummy
fill generation within 1.0um close to HV DIFF
and HV to
pfm_355u64kx144_v1a2/tc_355u64kx144_v1a2
database
well tap and
- Exclude POLY and metal dummy fill inside and within 1.0um outside of
MCEL(CW)
The dummy gen package was downloaded here:
/- Exclude metal1~4 dummy fill inside and within 1.0um outside of
MCEL(CW)
iplicense/cad/technology/pdkcmos28slp/opus61/designkit/foundry/download/
(All
numbers
are
shrink)
pdk-28SLP-V1.0_6.1_Calibre_FILL_gen.tar.gz
Update
pregen
tobefore
generate
layer in
MPW033C_Layer_List_SLPFEOL_6220_WB_FC_NVM_r04_SST
Update pdk ci command to update techfile.tf and display.drf files
Install the new version of foundry PDK DK1.2 and fix probecell issue
Upgrade lypgen tool to support generating layer-property file for Klayout
Update "Refresh CDF Instance Parameters" tool to support the order of parameters
Build Horizontal/Vertical Adjacent Tile Graphs
Implement a path path propagation for a multiple width net
Project.Code
PDK.Component
Status
Priority
Owner
PDK.Flow
PDK.Flow
In.Planning
Normal
Khoe
Emerald
DRC.Deck
In.Planning
Normal
Tri
Emerald
LVS.Deck
In.Planning
Normal
Tri
Emerald
Layout.Library
In.Planning
Normal
Tri
PDK.Flow
PDK.Flow
In.Planning
Low
Khoe
PDK.Flow
Layout.Compiler
Postponed
Normal
Khoe
PDK.Flow
Layout.Compiler
Postponed
Normal
Khoe
PDK.Flow
NA
In.Planning
Normal
Hoang
PDK.Flow
PDK.Flow
Postponed
Normal
Khoe
PDK.Flow
PDK.Flow
Postponed
Normal
Duong
ESF3-28GFD
SST.PDK
In.Planning
Normal
Duong
PDK.Flow
Layout.Compiler
In.Planning
Normal
Tri
PDK.Flow
Converted.Schematic
In.Planning
Normal
Tri
PDK.Flow
Layout.Compiler
Postponed
Normal
Tri
Jade
PDK.Flow
In.Planning
Normal
Khoe
Jade
LVS.Deck
In.Planning
Normal
Khoe
PDK.Flow
PDK.QA
In.Reviewing Normal
PDK.Flow
Converted.Schematic
Postponed
Normal
Hoang
PDK.Flow
Layout.Compiler
Postponed
Normal
Tri
PDK.Flow
Layout.Compiler
In.Planning
Normal
Duong
Thanh
Thanh
ESF3-40GFS
Layout.Library
Completed
Normal
ESF3-40GFS
PEX.Deck
In.Progress
Normal
ESF3-40GFS
Tech.Files
In.Planning
Normal
Thanh
ESF3-40GFS
Layout.Library
In.Planning
Normal
Thanh
ESF3-40GFS
Layout.Library
In.Planning
Normal
Thanh
PDK.Flow
PDK.Flow
In.Planning
Normal
Hoang
ESF3-28GFD
Layout.Compiler
Completed
Normal
Hoang
PDK.Flow
Schematic.Library
In.Progress
Normal
Duong
ESF3-28GFD
Layout.Compiler
In.Progress
Normal
Tri
In.Planning
Normal
Khoe
ESF3-40GFS
Converted.Schematic
Completed
Normal
Hoang
ESF3-28GFD
Pregen.Deck
Completed
Critical
Duong
ESF3-28GFD
Pregen.Deck
Completed
Critical
Duong
ESF3-28GFD
Pregen.Deck
Completed
Critical
Duong
PDK.Flow
PDK.Flow
In.Planning
Normal
Khoe
Jade
PDK.Flow
Completed
Normal
Khoe
PDK.Flow
PDK.Flow
Completed
Normal
Khoe
PDK.Flow
PDK.Flow
Completed
Normal
Khoe
WAT.Compiler
Layout.Router
Completed
Normal
Khoe
WAT.Compiler
Layout.Router
In.Progress
Normal
Khoe
ESF1-130CSMC SST.PDK
Thanh
Target
Actual
Comments
9/18/2015
10/30/2015
9/25/2015
10/30/2015
11/13/2015
10/23/2015

conversion
11/4/2015
11/15/2015
10/30/2015
10/30/2015
- Code SKILL to array bitcell

and do wire using predefined
cell: done
- Use informamation from
compiler-input-excel file to
generate schematic view:
verify-ing with the IP array
template --> not passed LVS
Review GFD array to
yet
understand
the difference
- Create schematic
symbol for
bitcell: not implemented yet
11/9/2015
11/5/2015
11/2/2015
11/2/2015
11/4/2015
10/31/2015
11/5/2015
11/4/2015
11/5/2015
11/9/2015
/home/data/shanghai/
pfm_355u64kx144_v1a2/
Task
pdk gen command
Build DRC deck
Build LVS deck
Implement HV MOS pcells by using MOS compiler
Implement Array_Straps_Design_Rule
Release PDK r1.0
HKMG cells
Implement Path Propagation for all nets simultaneously
Implement Path Construction for all nets simultaneously
Build a start point ESF3 template to generate A0 WAT

Install new spice model - esf340spicea3_2p5v
Implement a SKILL GUI for Verilog generation script
convert schematic from DK1.0 to DK1.1

Implement functions to process technology rules + via stack
Install new spice model - esf355spicea9
Upgrade Schematic conversion tool to keep all source properties (user-defined properti

Description
Hi Tri,
ii. Implement
python-based
functions
to parse
Calibredevice
rule desk
This
is the feedback
to speed
up the task
of creating
mapfiles.
files for
schematic conversion. This could be included in the Sch conversion tool, or
a
standalone
Implement
HVutility.
+ memory design rules
i.
Inputs:
array info
test-line size, cell placement info
Install
LV pad
deckcell,
andpad
implement
HV(X*Y),
LVS deck
(each cell will have pin info), cell DR tables (i.e. a table from MOS compiler),
Phase
1:
Create
cells
1) Users just provide the <src_sch_lib> to convert, nothing else.
from the tech file)
2) The tool scans through <src_sch_lib> and provide an initial map file M1 of
ii. Output:
the form:
Layout: cells are placed among the pads and routing is done between
(nil
map
Supporting
pinaobjects
objects
defined
bycould
Cadence
Space-Base
Router,
Schematic:
simple (pin
schedule
(cell
symbol
be from
a fixed library,
(should be a generic term of Cadence)
such as HV library)
(<tlib1>
<D_TLIB1>
Layout/schematic
aredatabases:
clean LVS SVS, LVL, LVS, cellname vs cellname
Compare
two
specified
<cell1>
<D_CELL1>
ii. PDK r1.0 (for TC1 and later)
<D_CELL2>
1.
SPICE
wait<cell2>
for Mandana
1.
Reviewmodel:
pcell
CDF
interfaces
--> create the best interface for our HV pcell
Implement
the flow
of
these commands
..
2.
DRC:
devices
a.
LV:
from) foundry:
2. Implement
(<tlib2>
<D_TLIB2>
b.
initial
copied
GFS40
3. HV:
Implement
Pythonfrom
to parse
the Excel template file to generate the pcell
<cell3>
c.
Mem
cell:HV
initial
from
UMC28
Implement
MOScopied
pcells
by using
MOS<D_CELL3>
compiler
code
files
<cell4>
<D_CELL4>
3. LVS:
a. LV: from foundry ..
Implement
) Array_Straps_Design_Rule
b. HV/mem:
Initial copied from GFS40
)4. PEX: TBD
)
Phase 2:
a.
If users
docompile
not update
all <D_CELLn>
listed, running
then popfeature
up a GUI to confirm
Update
pdk
command
to add DRC/LVS
2) Based
on the ring/PAD
update map
the tool willand
scan
Review
ESD/Seal
layoutM2,
in esf3-55umc
pdkumc55eflash
a.
ii.
If a cell has 2
or 3to
pins,
onemissing
pin named
P or PLUS,
one pin named M
Implementing
code
check
parameters
in netlist
or
MINUS,
and
a
parameter
named
R
or
Rsheet
or
segR
it isPDK
a to
resistor.
iii.
Else, it is
1. Migrate
a generic_device.
iv. 1.1
Cadence
category
file <lib>/*Cat
filecould
automatically
ESF3
Compiler
Review:
b.
Based
on
the
type
detected,
more
details
for mapping
each device could
2. Copy a layout/schematic database follow Pixy's
requirements
Collect
all to
feedbacks
about the ESF3 compiler, all need to have features
be added
create M4:
which
already
unsupported,
then hold a meeting to review
i. Example:
forsupported
transistor or
(similarly
for res/cap)
that,
so need
that we
can plan
to implement
that {w,
or improve
1. Only
to map
KEY set
of parameters
l, m} toour
{fw,flow
nf=1, fl, m} or
the other way around
HKMG is
cells
Below
the PEX files for LV just downloaded:
/iplicense/cad/technology/pdkchrt40lp/opus61/designkit/foundry/EDA-CADAll_device
example is LVS/DRC clean (include
40N-EX006/V1.3_1.0_BASE
PEX:
/iplicense/cad/technology/esf3-55gfs/ch55lpeUpdate
techfile to support LEF generation
a/designkit_r2.1a/run/pex/LVS/Include_SST/esf3-ch55lpea_pex_devices_hv.inc
Look at the function DMACRO SST_FET_PROPERTIES.
a. Review ESF3 layout compiler to understand how to use the compiler to

generate ESF3 WAT 3hours
Implement
Path the
Construction
for all nets
simultaneously
b. Understand
current template
from
40GFS:
/iplicense/cad/technology/esf3-40gfs/opus61/designkit_r2.0/mem_arrays/xls
i. try to re-generate the GFS40 values in GFD28 environment 3hours
c. Replace UMc28 values into the GFS40 templates (Review MTs email and
Build a start
point
ESF3
template to generate A0 WAT
Tapeout
layout
of T5)
10hours.
Install new spice model - esf340spicea3_2p5v
Implement a SKILL GUI for Verilog generation script
schpfm_355u64kx144_v1a2
schtc_355u64kx144_v1a2
dfdb_sim
dfdb_sim_tc
Implement functions to process technology rules + via stack

Install new spice model - esf355spicea9
Upgrade Schematic conversion tool to keep all source properties (user-defined prope
1. Build other spines based on Jinho's requests

2. Help Hoang on creating T5 spines
Project.Code
PDK.Component
Status
Priority
Owner
PDK.Flow
PDK.Flow
In.Planning
Normal
Khoe
Emerald
DRC.Deck
In.Planning
Normal
Tri
Emerald
LVS.Deck
In.Planning
Normal
Tri
Emerald
Layout.Library
In.Planning
Normal
Tri
PDK.Flow
PDK.Flow
In.Planning
Low
Khoe
PDK.Flow
Layout.Compiler
Postponed
Normal
Khoe
PDK.Flow
Layout.Compiler
Postponed
Normal
Khoe
PDK.Flow
NA
In.Planning
Normal
Hoang
PDK.Flow
PDK.Flow
Postponed
Normal
Khoe
PDK.Flow
PDK.Flow
Postponed
Normal
Duong
ESF3-28GFD
Layout.Compiler
Completed
Normal
Duong
Quartz
DRC.Deck
In.Progress
Normal
Duong
ESF3-28GFD
SST.PDK
In.Planning
Normal
Duong
PDK.Flow
Layout.Compiler
In.Planning
Normal
Tri
PDK.Flow
Converted.Schematic
In.Planning
Normal
Tri
PDK.Flow
Layout.Compiler
Postponed
Normal
Tri
Jade
PDK.Flow
In.Planning
Normal
Khoe
Jade
LVS.Deck
In.Planning
Normal
Khoe
PDK.Flow
PDK.QA
In.Reviewing Normal
PDK.Flow
Converted.Schematic
Postponed
Normal
Hoang
PDK.Flow
Layout.Compiler
Normal
Tri
Postponed
Thanh
PDK.Flow
Layout.Compiler
In.Planning
Normal
Duong
Thanh
ESF3-40GFS
Layout.Library
In.Planning
Normal
ESF3-40GFS
PEX.Deck
In.Planning
Normal
ESF3-40GFS
Tech.Files
In.Planning
Normal
Thanh
ESF3-40GFS
Layout.Library
In.Planning
Normal
Thanh
ESF3-40GFS
Layout.Library
In.Planning
Normal
Thanh
PDK.Flow
PDK.Flow
In.Planning
Normal
Hoang
WAT.Compiler
Layout.Router
In.Progress
Normal
Khoe
WAT.Compiler
Layout.Router
In.Planning
Normal
Khoe
ESF3-28GFD
Layout.Compiler
In.Progress
Normal
Hoang
ESF3-28GFD
Layout.Compiler
Completed
Normal
Tri
PDK.Flow
Schematic.Library
In.Planning
Normal
Duong
ESF3-40GFS
PDK.Install.Hspice
Completed
Critical
Thanh
PDK.Flow
PDK.Flow
In.Progress
Normal
Thanh
Jade
Converted.Schematic
Completed
Normal
Hoang
WAT.Compiler
Layout.Router
Completed
Normal
Khoe
Jade
PDK.Install.Hspice
Completed
Normal
Khoe
PDK.Flow
Converted.Schematic
Completed
Normal
Khoe
ESF3-28GFD
Layout.Compiler
In.Progress
Normal
Tri
In.Planning
Normal
Tri
ESF1-130CSMC SST.PDK
Thanh
Target
Actual
9/25/2015
9/18/2015
10/9/2015
10/12/2015
Comments
CDF params: done

Implement pcell for esf328sst:
in-progress
+ create callback: appear
param cdf in layout only: done
+ create callback: check
validation for value of params:
done
+ implement params in pcell
code: done
+ Create pcell template file +
implement filling params
function fill params into
template: done
+Fix bug in read inputfile +
contact instance: in-progress
10/16/2015
10/30/2015
9/25/2015
10/30/2015
10/16/2015
10/23/2015

conversion
10/20/2015
10/30/2015
10/30/2015
10/16/2015
10/23/2015
10/20/2015
10/9/2015
10/30/2015
10/15/2015
10/16/2015
10/12/2015
10/13/2015
10/13/2015
10/12/2015
10/23/2015
10/30/2015
Task
pdk gen command
Build DRC deck
Build LVS deck
Release PDK r1.0
Support drawing an array of VIAs in the ring

HKMG cells
Symbol lib setup verilog netlist of all device type, HVMOS, memory
cell,probecell,momcap and tranmos
Convert 7db from 40gfs + 1 db from 28umc
Implement functions to extract physical rules from techfile/predefined skill file
Implement Path Construction for all nets simultaneously

Description
Hi Tri,
ii. Implement
python-based
functions
to parse
Calibredevice
rule desk
This
is the feedback
to speed
up the task
of creating
mapfiles.
files for
a
standalone
Implement
HVutility.
+ memory design rules
i.
Inputs:
array info
Install
LV pad
deckcell,
andpad
implement
HV(X*Y),
LVS deck
Phase
1:
Create
cells
from the tech file)
ii. Output:
the form:
(nil
map
Supporting
pinaobjects
objects
defined
bycould
Cadence
Space-Base
Router,
Schematic:
simple (pin
schedule
(cell
symbol
be from
a fixed library,
(should be a generic term of Cadence)
such as HV library)
(<tlib1>
<D_TLIB1>
Layout/schematic
aredatabases:
Compare
two
specified
<cell1>
<D_CELL1>
ii. PDK r1.0 (for TC1 and later)
<D_CELL2>
1.
SPICE
wait<cell2>
for Mandana
1.
Reviewmodel:
pcell
CDF
interfaces
Implement
the flow
of
these commands
..
2.
DRC:
devices
a.
LV:
from) foundry:
2. Implement
(<tlib2>
<D_TLIB2>
b.
initial
copied
GFS40
3. HV:
Implement
Pythonfrom
to parse
the Excel template file to generate the pcell
<cell3>
c.
Mem
cell:HV
initial
from
UMC28
Implement
MOScopied
pcells
by using
MOS<D_CELL3>
compiler
code
files
<cell4>
<D_CELL4>
3. LVS:
a. LV: from foundry ..
Implement
) Array_Straps_Design_Rule
b. HV/mem:
Initial copied from GFS40
)4. PEX: TBD
)
Phase 2:
a.
If users
docompile
not update
all <D_CELLn>
listed, running
then popfeature
up a GUI to confirm
Update
pdk
command
to add DRC/LVS
2) Based
on the ring/PAD
update map
the tool willand
scan
Review
ESD/Seal
layoutM2,
in esf3-55umc
pdkumc55eflash
a.
ii.
If a cell has 2
or 3to
pins,
onemissing
pin named
P or PLUS,
one pin named M
Implementing
code
check
parameters
in netlist
or
MINUS,
and
a
parameter
named
R
or
Rsheet
or
segR
it isPDK
a to
resistor.
iii.
Else, it is
1. Migrate
a generic_device.
iv. 1.1
Cadence
category
file <lib>/*Cat
filecould
automatically
b.
Based
on
the
type
detected,
more
details
for mapping
each device could
requirements
be added to create M4:
i. Example: for transistor (similarly for res/cap)
1. Only need to map KEY set of parameters {w, l, m} to {fw, nf=1, fl, m} or
ESF3 Compiler Review:

Collect all feedbacks about the ESF3 compiler, all need to have features
which already supported or unsupported, then hold a meeting to review
that,
so 28umc
that weHKMG
can plan
to and
implement
improvetoour
flow generating
Review
array
upgradethat
theor
compiler
support
HKMG cells
1)
From
GFS40verilog
to GFD28.
Need
to device
resize all
CONT/VIAs.
The old sizes and
Symbol
lib setup
netlist
of all
type,
HVMOS, memory
new
sizes
could
be
found
in
tech
files
or
design
rule
manuals
or design rule
Below
is
the
PEX
files
for
LV
just
downloaded:
cell,probecell,momcap and tranmos
decks.
/iplicense/cad/technology/pdkchrt40lp/opus61/designkit/foundry/EDA-CAD/iplicense/cad/technology/esf340N-EX006/V1.3_1.0_BASE
40gfs/tapeout/TC0_WAT/20150918_2/from_Trang/ESF340GFS_TC1_WAT_HV_7
0DR_GF40.gds
/iplicense/cad/technology/esf3PEX:
40gfs/tapeout/TC0_WAT/20150917/from_Parviz/ESF340GFS_TC1_WAT_HV_CT
/iplicense/cad/technology/esf3-55gfs/ch55lpeUpdate techfile to support LEF generation
_rule.gds
a/designkit_r2.1a/run/pex/LVS/Include_SST/esf3-ch55lpeAdd
Bondpad/sealring/ip phantom/revid/iptag/esdpad layout example
/iplicense/cad/technology/esf3a_pex_devices_hv.inc
40gfs/tapeout/TC0_WAT/20150917/from_Parviz/ESF340GFS_TC1_WAT_HV_PB
Look
at the
function
DMACRO
Generate
Mini
array layout
withSST_FET_PROPERTIES.
LVS/DRC clean
M.gds
/iplicense/cad/technology/esf3Review and improve genLVS.pl tool
40gfs/tapeout/TC0_WAT/20150917/from_Parviz/ESF340GFS_TC1_WAT_HV_ST
D.gds
/iplicense/cad/technology/esf340gfs/tapeout/TC0_WAT/20150917/from_Parviz/ESF340GFS_TC1_WAT_HV_OP
T1.gds
/iplicense/cad/technology/esf3Implement functions to extract physical rules from techfile/predefined skill file
40gfs/tapeout/TC0_WAT/20150917/from_Parviz/ESF340GFS_TC1_WAT_HV_OP
T2.gds
a.
Review ESF3 layout compiler to understand how to use the compiler to
/iplicense/cad/technology/esf3generate
ESF3 WAT 3hours
40gfs/tapeout/TC0_WAT/20150918_2/from_Trang/HV_STD_GF_150917_GF40.
Implement
Path the
Construction
for all nets
simultaneously
b.
Understand
current template
from
40GFS:
gds
/iplicense/cad/technology/esf3-40gfs/opus61/designkit_r2.0/mem_arrays/xls
i. try to re-generate the GFS40 values in GFD28 environment 3hours
c.
into the GFS40 templates (Review MTs email and
2) Replace
From UMc28
UMC28values
to GFD28:
Build
a
start
point
ESF3
template
Tapeout
layout of T5) 10hours. to generate A0 WAT
/iplicense/cad/technology/esf328umc/tapeout/TC0_WAT/20150605/from_MT/TC0_WAT_raw_20150605/ESF3
28UMC_WAT_TC0_XLDD.gds
Project.Code
PDK.Component
Status
Priority
Owner
PDK.Flow
PDK.Flow
In.Planning
Normal
Khoe
Emerald
DRC.Deck
In.Planning
Normal
Tri
Emerald
LVS.Deck
In.Planning
Normal
Tri
Emerald
Layout.Library
In.Planning
Normal
Tri
PDK.Flow
PDK.Flow
In.Planning
Low
Khoe
PDK.Flow
Layout.Compiler
Postponed
Normal
Khoe
PDK.Flow
Layout.Compiler
Postponed
Normal
Khoe
PDK.Flow
NA
In.Planning
Normal
Hoang
PDK.Flow
PDK.Flow
Postponed
Normal
Khoe
PDK.Flow
PDK.Flow
Postponed
Normal
Duong
ESF3-28GFD
Layout.Compiler
In.Progress
Normal
Duong
Quartz
DRC.Deck
In.Progress
Normal
Duong
ESF3-28GFD
SST.PDK
In.Planning
Normal
Duong
PDK.Flow
Layout.Compiler
In.Planning
Normal
Tri
PDK.Flow
Converted.Schematic
In.Planning
Normal
Tri
PDK.Flow
Layout.Compiler
Postponed
Normal
Tri
Jade
PDK.Flow
In.Planning
Normal
Khoe
Jade
LVS.Deck
In.Planning
Normal
Khoe
PDK.Flow
PDK.QA
In.Progress
Normal
Thanh
PDK.Flow
Converted.Schematic
In.Progress
Normal
Hoang
PDK.Flow
Layout.Compiler
Normal
Duong
In.Planning
PDK.Flow
Layout.Compiler
Postponed
Normal
Tri
PDK.Flow
Layout.Compiler
In.Planning
Normal
Duong
Device.Library
Completed
Critical
ESF3-40GFS
ESF3-40GFS
Thanh
Thanh
Layout.Library
In.Planning
Normal
ESF3-40GFS
PEX.Deck
In.Planning
Normal
Thanh
ESF3-40GFS
Tech.Files
In.Planning
Normal
Thanh
ESF3-40GFS
Layout.Library
In.Planning
Normal
Thanh
ESF3-40GFS
Layout.Library
In.Planning
Normal
Thanh
PDK.Flow
PDK.Flow
In.Planning
Normal
Hoang
ESF3-28GFD
Converted.Layout.Li Completed
Normal
Hoang
WAT.Compiler
Layout.Router
Completed
Normal
Khoe
WAT.Compiler
Layout.Router
In.Progress
Normal
Khoe
WAT.Compiler
Layout.Router
In.Planning
Normal
Khoe
ESF3-28GFD
Layout.Compiler
In.Progress
Normal
Hoang
ESF3-28GFD
Layout.Compiler
In.Progress
Normal
Tri
Target
9/25/2015
9/18/2015
10/9/2015
Actual
Comments
CDF params: done

Implement pcell for esf328sst:
in-progress
+ create callback: appear
param cdf in layout only: done
+ create callback: check
validation for value of params:
done
+ implement params in pcell
code: done
+ Create pcell template file +
implement filling params
function fill params into
template: done
+Fix bug in read inputfile +
contact instance: in-progress
10/16/2015
10/30/2015
9/25/2015
10/9/2015
10/16/2015
70%
conversion
10/9/2015
10/9/2015
10/30/2015
10/5/2015
10/9/2015
10/16/2015
10/23/2015
10/9/2015
10/9/2015
Implementing utility functions
Task
Build DRC deck
Build LVS deck
<cell2>
..
<D_CELL2>
)
(<tlib2>
<D_TLIB2>
<cell3>
<D_CELL3>
Description
<cell4>
<D_CELL4>
..
Implement HV + memory
design rules
)
Install
LV deck and implement HV LVS deck
)
)Create Techprimitive_devices cells
Phase 2:
a.
If users
docompile
not update
all <D_CELLn>
listed, running
then popfeature
up a GUI to confirm
Update
pdk
command
to add DRC/LVS
ESF3
CompilertoReview:
and continue
run without stop. This has been discussed already.
Collect
allon
feedbacks
about
ESF3
all need
to have features
2) Based
the update
mapthe
M2,
the compiler,
tool will scan
the <src_sch_lib>
and
which
already
supported etc.
or unsupported,
hold
a meeting
<D_TLIB1>,
<D_TLIB2>
and provide athen
more
detail
map M3to review
that,
so that we
to implement
that
or of
improve
our<D_CELLi>
flow
a. Internally,
thecan
toolplan
will try
to guess the
type
each cell
ii. If a cell has 2 or 3 pins, one pin named P or PLUS, one pin named M
or MINUS, and a parameter named R or Rsheet or segR it is a
resistor. If not, it is a capacitor
iii. Else, it is generic_device.
iv. Cadence category file <lib>/*Cat could be used to detect device type
b. Based on the type detected, more details for mapping each device could
be added to create M4:
i. Example: for transistor (similarly for res/cap)
1. Only need to map KEY set of parameters {w, l, m} to {fw, nf=1, fl, m} or
c. Special case: the instance parameter model should be deleted.
After phase 2, the map would be >95% correct and users can wrap it up for
an official use.
Best Regards,
-Binh
Project.Code
PDK.Component
Status
Priority
Owner
Emerald
DRC.Deck
In.Planning
Normal
Tri
Emerald
LVS.Deck
In.Planning
Normal
Tri
Emerald
Layout.Library
In.Planning
Normal
Tri
PDK.Flow
Layout.Compiler
In.Planning
Normal
Tri
PDK.Flow
Converted.Schematic
In.Planning
Normal
Tri
PDK.Flow
Layout.Compiler
Postponed
Normal
Tri
PDK.Flow
Layout.Compiler
In.Progress
Normal
Tri
Target
9/25/2015
10/9/2015
Actual
Comments
Task
Create WAT DRC ruledeck
Description
Create WAT DRC ruledeck
Project.Code
PDK.Component
Status
Priority
Owner
PDK.Flow
PDK.QA
In.Progress
Normal
Thanh
ESF3-28GFD
SST.PDK
Completed
Normal
Thanh
Target
9/28/2015
9/24/2015
Actual
Comments
70%
Task
pdk gen command
Build DRC deck
Build LVS deck
Implement PDK db2db command - phase1 Layout Conversion

HKMG cells
Implement HV MOS pcells by using MOS compiler by using pccompile
command
Implement a flow to migrate Layout database from a specified PDK to another one.
Support generating DTC/WAT arrays


Review WAT routing algorithms and plan to implement
Update ESD rule deck to ignore HV areas
Release PDK package to UMC
Run tapeout for 7-DTCs and review the results
Help to debug LVS problem of pfm_340u512kx32_v1a0
Run tapeout for ESF340UMC_TC1_WAT and prepare the SO package
Review rules on generated WAT layouts
Replace pad for esf440 wat
Run tapeout flow for 7DTC and prepare the SO package
Upgrade some pdk commands to support python 2.4.3
Run tapeout flow for 11 WATs
Review Cadence Xscale to understand why 0.07x0.07 via1 shrank 90% -->
0.064x0.064
Description
Implement HV + memory design rules
i.
Inputs:
array info
Install
LV pad
deckcell,
andpad
implement
HV(X*Y),
LVS deck
Create
cells
from
the
tech
file)
Hi Tri,
ii. Output:
Layout:
are placed
among
thetask
pads
routing
is done
between
This
is the cells
feedback
to speed
up the
ofand
creating
device
map
files for
pads and cell
pins using
Space-Base
Router. in the Sch conversion tool, or
schematic
conversion.
This
could be included
Supporting
pin
objects
defined
bycould
Cadence
Space-Base
Router,
Schematic:
aobjects
simple (pin
schedule
(cell
symbol
be from
a fixed library,
a standalone
utility.
should
such asbe
HVa library)
Layout/schematic
aredatabases:
Compare
two specified
Phase 1:
Implement
a provide
command-line
script to port
database
from aelse.
specified PDK to
1) Users just
the <src_sch_lib>
toaconvert,
nothing
another:
1.
theMigrate
form: a layout/schematic database from PDK to PDK:
2.
Copy
database follow Pixy's requirements
(nil
mapa layout/schematic
1.
Review
pcell
CDF of
interfaces
Implement
the flow
these commands
(devices
(<tlib1>
<D_TLIB1>
2. Implement
<cell1>
<D_CELL1>
3. Implement Python to parse the Excel template file to generate the pcell
Support
drawing an <cell2>
array of VIAs in the <D_CELL2>
ring
code files
..
)
HKMG cells
(<tlib2>
<D_TLIB2>
Implement HV MOS pcells
by using MOS<D_CELL3>
compiler by using pccompile
<cell3>
command
<cell4>
<D_CELL4>
..
1.
Work with me
to clear the
requirement
and define
the user-interface.
Understand
ESF1/ESF3
compiler
and create
the detail
userguide document
)
2. Understand the current Cadence migration flow. Reference document: /pkg/ic)6.1.6.500.11/doc/migrate/migrate.pdf
)3. Implement SKILL + Python scripts to simplify the migration flow.
Phase 2:
a.
If users
docompile
not update
all <D_CELLn>
listed, running
then popfeature
up a GUI to confirm
Update
pdk
command
to add DRC/LVS
2) Based
on the ring/PAD
update map
the tool willand
scan
Review
ESD/Seal
layoutM2,
in esf3-55umc
pdkumc55eflash
a.
iii. Else, it is generic_device.
iv. Cadence category file <lib>/*Cat could be used to detect device type

another:
Run tapeout for ESF340UMC_TC1_WAT and prepare the SO package
Run tapeout flow for 7DTC and prepare the SO package
Upgrade some pdk commands to support python 2.4.3
Run tapeout flow for 11 WATs
Review Cadence Xscale to understand why 0.07x0.07 via1 shrank 90% -->
0.064x0.064
Project.Code
PDK.Component
Status
Priority
Owner
PDK.Flow
PDK.Flow
In.Planning
Normal
Khoe
Emerald
DRC.Deck
In.Planning
Normal
Tri
Emerald
LVS.Deck
In.Planning
Normal
Tri
Emerald
Layout.Library
In.Planning
Normal
Tri
PDK.Flow
PDK.Flow
In.Planning
Low
Khoe
PDK.Flow
Layout.Compiler
Postponed
Normal
Khoe
PDK.Flow
Layout.Compiler
Postponed
Normal
Khoe
PDK.Flow
NA
In.Planning
Normal
Hoang
PDK.Flow
Normal
Hoang
PDK.Flow
PDK.Flow
Postponed
Normal
Khoe
PDK.Flow
PDK.Flow
Postponed
Normal
Duong
PDK.Flow
Layout.Compiler
In.Planning
Normal
Duong
PDK.Flow
Layout.Compiler
In.Planning
Normal
Duong
ESF3-40GFS
Layout.Compiler
In.Planning
Normal
Duong
PDK.Flow
Layout.Compiler
In.Planning
Normal
Tri
PDK.Flow
PDK.Flow
In.Reviewing Normal
Hoang
ESF3-40GFS
Layout.Compiler
In.Progress
Normal
Tri
PDK.Flow
Converted.Schematic
In.Planning
Normal
Tri
PDK.Flow
Layout.Compiler
Postponed
Normal
Tri
Jade
PDK.Flow
In.Planning
Normal
Khoe
Jade
LVS.Deck
In.Planning
Normal
Khoe
PDK.Flow
PDK.QA
In.Progress
Normal
Thanh
PDK.Flow
Converted.Schematic
In.Progress
Normal
Hoang
PDK.Flow
Layout.Compiler
In.Progress
Normal
Khoe
Quartz
DRC.Deck
Completed
Normal
Duong
Quartz
SST.PDK
Completed
Normal
Duong
ESF3-40GFS
SST.PDK
In.Planning
Normal
Thanh
Quartz
NA
Completed
Normal
Thanh
Quartz
Tape.Out
Completed
Normal
Duong
Quartz
DRC.Deck
In.Progress
Normal
Duong
ESF3-40GFS
Tape.Out
Completed
Normal
Thanh
ESF3-40GFS
Layout.Library
Completed
Normal
Thanh
ESF3-40GFS
PDK.Flow
ESF3-40GFS
Tape.Out
PDK.Flow
Tape.Out
Completed
Completed
Completed
Normal
Normal
Normal
Khoe
Khoe
Khoe
PDK.Flow
PDK.Flow
In.Progress
Normal
Khoe
Target
Actual
Comments
9/25/2015
9/7/2015
9/18/2015
7/24/2015
9/18/2015
9/25/2015
Implemented script request for

lib management :
copy lib or top cell
add prefix
9/18/2015
file, but it needs to update

because I changed the format
of device list.
b. Write code to create
schematic- netlist from a
device list
9/18/2015
9/25/2015
9/11/2015
9/11/2015
9/11/2015
9/11/2015
9/15/2015
9/18/2015
9/17/2015
9/17/2015
9/12/2015
9/17/2015
9/17/2015
9/18/2015
Ask Jenny Peng to send GDS/netlist to us to help debugging
help debugging
Task
pdk gen command
Build DRC deck
Build LVS deck
Implement PDK db2db command - phase1 Layout Conversion

HKMG cells
command

Regenerate 7-DTC arrays
Update the pregen to support both DTC and Macro TC1 tapeout
Review V1.S7 and V2.S7 rules for pfm-340u512kx32_v10a database, to make sur
Review the updated layermap from Xian and update if any
Install and verify new package of dummy-fill code
converted 7 DTCs which is DTCs layout from designer on the 25/Aug tapeouts from esf3-40gf
Description
i.
Inputs:
array info
Install
LV pad
deckcell,
andpad
implement
HV(X*Y),
LVS deck
Create
cells
from the tech file)
ii. Output:
cells are placed among the pads and routing is done between
Hi Layout:
Tri,
Supporting
pinaobjects
(pin
objects
defined
bycould
Cadence
Space-Base
Router,
Schematic:
simple
schedule
symbol
bedevice
from
amap
fixed
library,
This
is the feedback
to speed
up (cell
the task
of creating
files
for
should
be
a library)
such
as
HV
Layout/schematic
aredatabases:
a
standalone
Compare
two utility.
specified
another:
Phase 1:
the
form: pcell
1.
Review
CDF of
interfaces
Implement
the flow
these commands
devices
(nil
map
2. Implement
(3. Implement Python to parse the Excel template file to generate the pcell
Support
drawing
an array of VIAs in the ring
(<tlib1>
<D_TLIB1>
code files
<cell1>
<D_CELL1>
Review 28umc HKMG
array and upgrade
the compiler to support generating
<cell2>
<D_CELL2>
HKMG cells
..
Implement) HV MOS pcells by using MOS compiler by using pccompile
command (<tlib2>
<D_TLIB2>
<cell3>
<D_CELL3>
1.
Work with me
to clear
the
requirement
and
define
the user-interface.
Understand
ESF1/ESF3
compiler
and create
the detail
userguide document
<cell4>
<D_CELL4>
2. Understand the current Cadence migration
flow. Reference document: /pkg/ic..
6.1.6.500.11/doc/migrate/migrate.pdf
)
3. Implement SKILL + Python scripts to simplify the migration flow.
)
Support
generating DTC/WAT arrays
)
Regenerate 7-DTC arrays
Phase 2:
a.
If users
docompile
not update
all <D_CELLn>
listed, running
then popfeature
up a GUI to confirm
Update
pdk
command
to add DRC/LVS
2)
Based
on the ring/PAD
update map
the tool willand
scan
Review
ESD/Seal
layoutM2,
in esf3-55umc
pdkumc55eflash
a. Internally, the tool will try to guess the type of each cell <D_CELLi>

another:
Update
theapregen
to support both
DTC and
TC1
tapeout:
1. Migrate
layout/schematic
database
fromMacro
PDK to
PDK:
1. 1.1
DTC:Build
convert
ZNLV in HWPEL tofile
ZNHV
and then run PRE-GEN for old array
layermap/devicemap
automatically
layout
to
remove
un-wanted
CONT/DIFF
and
generate
MO11
requirements
2. Macro: run PRE-GEN to generate MOSN/MOSP/SBLK from HVPB
Review V1.S7 and V2.S7 rules for pfm-340u512kx32_v10a database, to make

Review the updated layermap from Xian and update if any
Install and verify new package of dummy-fill code
converted 7 DTCs which is DTCs layout from designer on the 25/Aug
tapeouts from esf3-40gfs to esf3-55gfs
Project.Code
PDK.Component
Status
Priority
Owner
PDK.Flow
PDK.Flow
In.Planning
Normal
Khoe
Emerald
DRC.Deck
In.Planning
Normal
Tri
Emerald
LVS.Deck
In.Planning
Normal
Tri
Emerald
Layout.Library
In.Planning
Normal
Tri
PDK.Flow
PDK.Flow
In.Planning
Low
Khoe
PDK.Flow
Layout.Compiler
Postponed
Normal
Khoe
PDK.Flow
Layout.Compiler
Postponed
Normal
Khoe
PDK.Flow
NA
In.Planning
Normal
Hoang
PDK.Flow
Converted.Layout.Li In.Reviewing Normal
Hoang
PDK.Flow
PDK.Flow
Postponed
Normal
Khoe
PDK.Flow
PDK.Flow
Postponed
Normal
Duong
PDK.Flow
Layout.Compiler
In.Planning
Normal
Duong
PDK.Flow
Layout.Compiler
In.Planning
Normal
Duong
ESF3-40GFS
Layout.Compiler
In.Planning
Normal
Duong
PDK.Flow
Layout.Compiler
In.Planning
Normal
Tri
PDK.Flow
PDK.Flow
In.Reviewing Normal
Hoang
ESF3-40GFS
Layout.Compiler
In.Progress
Normal
Tri
ESF3-40GFS
Layout.Compiler
Completed
Normal
Tri
PDK.Flow
Converted.Schematic
In.Planning
Normal
Tri
PDK.Flow
Layout.Compiler
Postponed
Normal
Tri
Jade
PDK.Flow
In.Planning
Normal
Khoe
Jade
LVS.Deck
In.Planning
Normal
Khoe
PDK.Flow
PDK.QA
In.Progress
Normal
Thanh
PDK.Flow
Converted.Schematic
In.Progress
Normal
Hoang
Quartz
Pregen.Deck
Completed
Normal
Duong
Quartz
DRC.Deck
Completed
Normal
Duong
ESF3-40GFS
SST.PDK
Completed
Normal
Thanh
PDK.Flow
Layout.Compiler
In.Progress
Normal
Khoe
Quartz
DRC.Deck
In.Progress
Normal
Duong
Quartz
DRC.Deck
In.Planning
Normal
Duong
Quartz
DRC.Deck
Completed
Normal
Duong
ESF3-40GFS
SST.PDK
In.Planning
Normal
Thanh
Quartz
NA
In.Planning
Normal
Thanh
ESF3-40GFS
Layout.Library
Completed
Normal
Hoang
Target
Actual
Comments
9/25/2015
9/7/2015
9/18/2015
7/24/2015
9/18/2015
9/10/2015
9/15/2015

lib management :
add prefix
9/18/2015
a. Wrote code to parse xlsx

file, but it needs to update
because I changed the format
of device list.
b. Write code to create
schematic- netlist from a
device list
9/18/2015
9/7/2015
9/7/2015
9/4/2015
9/11/2015
9/11/2015
9/11/2015
9/10/2015
9/11/2015
9/11/2015
9/7/2015
Ask Jenny Peng to send GDS/netlist to us to help debugging
help debugging
Task
pdk gen command
Build DRC deck
Build LVS deck
Implement PDK db2db command

HKMG cells
command
Implement programmable DR Evaluator
PDK QA flow
ESF3-40 UMC schematic libraries to ESF3-110 LF schematic libraries

dryrun tape-out flow
Re-tapeout 28UMC ESF328UMC_WAT_TC0_CELL_HKMG/ ESF328UMC_WAT_TC0_CELL_HK
Install the new version of Dummy Filling Rule deck

Verify the tapeout flow
Update the PDK to support users to run with metal stack option = 1P7M1T0H0A, f
Install foundry PDK ver 7 for esf1-180slt
Fix DRC violations for the bonding pad, probe pad and antenna diodes
Implement REST, DFXF, RSNW, DIFF rules
Work with Andy to verify the released databases
Update DRC deck to waive rules some logic rules
Update the pregen deck and verify the tapeout flow
convert schtc_355u256kx32_v1a0_cnvrt_2_LibESF340UMC from esf3-55esfash to esf3Convert layout databases (ESF3-40UMC_WAT_HV_OPT1, ESF3-40UMC_WAT_HV_OPT2,
Update the ESF3 compiler to support many rfiller x-placement, multiple DUT placement
Work with our outsource vendor about the PDK installation issues
Description
i.
Inputs:
array info
Install
LV pad
deckcell,
andpad
implement
HV(X*Y),
LVS deck
Create
cells
from the tech file)
ii. Output:
Supporting
pinaobjects
objects
defined
bycould
Cadence
Space-Base
Router,
Hi
Tri,
Schematic:
simple (pin
schedule
(cell
symbol
be from
a fixed library,
should
such asbe
HVa library)
This
is
the
feedback
to
the task of creating device map files for
Layout/schematic
arespeed
cleanup
LVS
Compare
two
specified
databases:
SVS,
LVL, LVS,
cellname
vs cellname
schematic conversion. This could be
included
in the
Sch conversion
tool, or
Implement
a command-line
script to port a database from a specified PDK to
a
standalone
utility.
another:
1.1 Build
layermap/devicemap file automatically
Phase
1:
2.
Copy
a
layout/schematic
database follow
Pixy's requirements
1) Users just provide the <src_sch_lib>
to convert,
nothing else.
1.
Review
pcell
CDF
interfaces
-->
create
the
best interface
formap
our HV
Implement
the
flow
of
these
commands
2) The tool scans through <src_sch_lib> and provide
an initial
file pcell
M1 of
devices
the form:
2. Implement SKILL pcell template file
3.
Python to parse the Excel template file to generate the pcell
(nilImplement
map
Support
drawing
an array of VIAs in the ring
code
files
(
Review 28umc
HKMG array and upgrade the compiler
to support generating
(<tlib1>
<D_TLIB1>
HKMG cells
<cell1>
<D_CELL1>
<cell2>
by using MOS<D_CELL2>
compiler by using pccompile
..
command
)
Understand
ESF1/ESF3 compiler and create the detail
userguide document
(<tlib2>
<D_TLIB2>
<cell3>
<D_CELL3>
1. Work with me to clear
the requirement and
define the user-interface.
Implement programmable
DR Evaluator<D_CELL4>
<cell4>
2. Understand the current Cadence migration flow. Reference document: /pkg/ic..
6.1.6.500.11/doc/migrate/migrate.pdf
)
3. Implement SKILL + Python scripts to simplify the migration flow.
)1. Build PDK QA check list, communicate with Pixy/Binh/Khoe
)2. Review the current flow and implement the new features
Phase 2:
DEFINE
schprm_340u128kx32_v1a0
/home/data/prm_r3110lf32kx32_v1a0/opus/dfdb_sch_umc340
DEFINE
schtcprm_340u128kx32_v1a0
<D_TLIB2>,
<D_CELL1>, etc. to create map M2
/home/data/prm_r3110lf32kx32_v1a0/opus/dfdb_tcsch_umc340
a. If users do not update all <D_CELLn> listed, then pop up a GUI to confirm
2) Based on the update map M2, the tool will scan the <src_sch_lib> and
Sample tape-out run:

/iplicense/cad/technology/esf328umc/tapeout/dtc_328u256kx16_v3a0/20150601/run_dtc4m_328u_v3a0.cs
h
The tape-out DRC/LVS result should be similar to the result from DE team.
In the past tape-out runs were normally located at:

Re-tapeout
28UMC ESF328UMC_WAT_TC0_CELL_HKMG/ ESF328UMC_WAT_TC0_CELL_
/iplicense/proj/<tech>/<test_chip>/tapeout/
But
we changed
the organization
so that theasresult
2. ZERO
marked layer
have to be implemented
NOT can be sync to all sites to
review:
/iplicense/cad/technology/<tech>/tapeout/<db_name>
Update the PDK to support users to run with metal stack option = 1P7M1T0H0A
Install the new version of FDK
Fix DRC violations for the bonding pad, probe pad and antenna diodes
Implement REST, DFXF, RSNW, DIFF rules
Work with Andy to verify the released databases
Update DRC deck to waive rules some logic rules
Update the pregen deck and verify the tapeout flow
convert schtc_355u256kx32_v1a0_cnvrt_2_LibESF340UMC from esf3-55esfash to es
Convert layout databases (ESF3-40UMC_WAT_HV_OPT1, ESF3-40UMC_WAT_HV_OPT
Update the ESF3 compiler to support many rfiller x-placement, multiple DUT placem
Work with our outsource vendor about the PDK installation issues
Project.Code
PDK.Component
Status
Priority
Owner
PDK.Flow
PDK.Flow
In.Planning
Normal
Khoe
Emerald
DRC.Deck
In.Planning
Normal
Tri
Emerald
LVS.Deck
In.Planning
Normal
Tri
Emerald
Layout.Library
In.Planning
Normal
Tri
PDK.Flow
PDK.Flow
In.Planning
Low
Khoe
PDK.Flow
Layout.Compiler
Postponed
Normal
Khoe
PDK.Flow
Layout.Compiler
Postponed
Normal
Khoe
PDK.Flow
NA
In.Planning
Normal
Hoang
PDK.Flow
Converted.Layout.Li In.Progress
Normal
Hoang
PDK.Flow
PDK.Flow
Postponed
Normal
Khoe
PDK.Flow
PDK.Flow
Postponed
Normal
Duong
PDK.Flow
Layout.Compiler
In.Planning
Normal
Duong
PDK.Flow
Layout.Compiler
In.Planning
Normal
Duong
ESF3-40GFS
Layout.Compiler
In.Planning
Normal
Duong
PDK.Flow
Layout.Compiler
In.Planning
Normal
Tri
PDK.Flow
Layout.Compiler
In.Reviewing Normal
Khoe
PDK.Flow
PDK.Flow
In.Reviewing Normal
Hoang
PDK.Flow
PDK.QA
Postponed
Normal
Thanh
ESF3-40GFS
Layout.Compiler
In.Progress
Normal
Tri
PDK.Flow
Converted.Schematic
In.Planning
Normal
Tri
Amber
Converted.Schematic
Completed
Normal
Hoang
PDK.Flow
Layout.Compiler
Postponed
Normal
Tri
PDK.Flow
Layout.Compiler
Completed
Critical
Tri
Jade
PDK.Flow
In.Planning
Normal
Khoe
ESF3-28UMC
Tape.Out
Completed
Normal
Khoe
Jade
LVS.Deck
In.Planning
Normal
Khoe
Quartz
DRC.Deck
Completed
Normal
Duong
Quartz
Tape.Out
In.Progress
Normal
Duong
Quartz
PDK.Flow
Completed
Normal
Duong
Pearl
Foundry.PDK
In.Planning
Normal
Thanh
PDK.Flow
PDK.QA
Postponed
Normal
Thanh
Quartz
Layout.Library
In.Planning
Normal
Duong
Quartz
DRC.Deck
Completed
Normal
Duong
Pearl
Layout.Library
Completed
Normal
Thanh
Pearl
DRC.Deck
In.Progress
Normal
Thanh
Pearl
Tape.Out
In.Progress
Normal
Thanh
Quartz
Converted.Schematic
Completed
Normal
Hoang
ESF3-40GFS
Converted.Schematic
Completed
Normal
Hoang
PDK.Flow
Layout.Compiler
Completed
Normal
Khoe
Quartz
NA
Completed
Normal
Khoe
Target
Actual
Comments
8/31/2015
8/31/2015
8/31/2015
8/14/2015
8/21/2015
8/21/2015
8/14/2015
8/31/2015
8/21/2015
7/31/2015
8/7/2015
7/24/2015
8/14/2015
8/14/2015
9/15/2015
8/7/2015

lib management :
add prefix
8/31/2015
7/27/2015
8/13/2015
8/7/2015
8/14/2015
8/10/2015
8/14/2015
8/18/2015
8/13/2015
8/11/2015
8/14/2015
8/14/2015
8/12/2015
8/13/2015
8/12/2015
8/12/2015
Task
pdk gen command
Build DRC deck
Build LVS deck
Implement PDK db2db command

HKMG cells
command
Fix bug of MOS Compiler: drawing of multiple gate and contact are incorrect
PDK QA flow
ESF3-40 UMC schematic libraries to ESF3-110 LF schematic libraries

dryrun tape-out flow
Fix ESF3-110A LF Hspice sim issue
Re-tapeout 28UMC two WATs: ESF328UMC_WAT_TC0_HV_PBM, ESF328UMC_WAT_TC0_H
Compare the device layer list between 55umc SST and foundry PDKs
Implement pdk gds2xlm command, a tool to convert gds files to layermap files and do
Add layers CGPO:FLGT and CGPO:LVS into layermap file

Update the PDK to support users to run with metal stack option = 1P7M1T0H0A, f
Map UMC's layermap and internal layermap
Install foundry PDK ver 7 for esf1-180slt
Description
i.
Inputs:
array info
Install
LV pad
deckcell,
andpad
implement
HV(X*Y),
LVS deck
Create
cells
from the tech file)
ii. Output:
Supporting
pinaobjects
objects
defined
bycould
Cadence
Space-Base
Router,
Schematic:
simple (pin
schedule
(cell
symbol
be from
a fixed library,
should
such asbe
HVa library)
Hi
Tri,
Layout/schematic
aredatabases:
Compare
two specified
Implement
a command-line
script
to port
from a map
specified
This is the feedback
to speed
up the
task a
ofdatabase
creating device
files PDK
for to
another:
1.
Migrate a layout/schematic
database from PDK to PDK:
a standalone
utility.
1.
Review pcell CDF interfaces --> create the best interface for our HV pcell
Implement
Phase 1: the flow of these commands
devices
2. Implement SKILL pcell template file
3. Implement Python to parse the Excel template file to generate the pcell
the
form:drawing an array of VIAs in the ring
Support
code files
Review
(nil map28umc HKMG array and upgrade the compiler to support generating
HKMG
cells
(
Implement(<tlib1>
HV MOS pcells by using MOS compiler<D_TLIB1>
by using pccompile
<cell1>
<D_CELL1>
command
<cell2>
<D_CELL2>
Understand ESF1/ESF3
compiler
and
create
the detail userguide document
..
) me to clear the requirement and define the user-interface.
1. Work with
Implement programmable
DR Evaluator
(<tlib2>
<D_TLIB2>
2. Understand
the current Cadence migration flow. Reference
document: /pkg/ic6.1.6.500.11/doc/migrate/migrate.pdf
<cell3>
<D_CELL3>
3. Implement SKILL + <cell4>
Python scripts to simplify
the migration flow.
<D_CELL4>
..
Fix bug of )MOS Compiler: drawing of multiple gate and contact are incorrect
)1. Build PDK QA check list, communicate with Pixy/Binh/Khoe
)2. Review the current flow and implement the new features
Phase 2:
a. If users do not update all <D_CELLn> listed, then pop up a GUI to confirm
2) Based on the update map M2, the tool will scan the <src_sch_lib> and
The target is to send that GDS to GFS asap to test the flow (to check any
missingschprm_340u128kx32_v1a0
layers, any problems with SST GDS etc.)
DEFINE
/home/data/prm_r3110lf32kx32_v1a0/opus/dfdb_sch_umc340
DEFINE
Sampleschtcprm_340u128kx32_v1a0
tape-out run:
/home/data/prm_r3110lf32kx32_v1a0/opus/dfdb_tcsch_umc340
/iplicense/cad/technology/esf3-
28umc/tapeout/dtc_328u256kx16_v3a0/20150601/run_dtc4m_328u_v3a0.cs
h
The tape-out DRC/LVS result should be similar to the result from DE team.
1. Missing
including
files normally located at:
In
the pastrequired
tape-out
runs were
2.
Missing
required
variable
definitions
/iplicense/proj/<tech>/<test_chip>/tapeout/
Re-tapeout 28UMC two WATs: ESF328UMC_WAT_TC0_HV_PBM, ESF328UMC_WAT_TC0
The
checkingthe
approach
for LVS deck
by the
following
truth
table:to all sites to
But tight
we changed
organization
so that
resultthe
can
be sync
1.
ONE
marked
layer
have
to
be
implemented
as
AND
review:
2.
ZERO marked layer have to be implemented as NOT
/iplicense/cad/technology/<tech>/tapeout/<db_name>
Compare the device layer list between 55umc SST and foundry PDKs
Implement pdk gds2xlm command, a tool to convert gds files to layermap files and
Add layers CGPO:FLGT and CGPO:LVS into layermap file

Update the PDK to support users to run with metal stack option = 1P7M1T0H0A
Map UMC's layermap and internal layermap to find mismatching layers
Install the new version of FDK
Project.Code
PDK.Component
Status
Priority
Owner
PDK.Flow
PDK.Flow
In.Planning
Normal
Khoe
Emerald
DRC.Deck
In.Planning
Normal
Tri
Emerald
LVS.Deck
In.Planning
Normal
Tri
Emerald
Layout.Library
In.Planning
Normal
Tri
PDK.Flow
PDK.Flow
In.Planning
Low
Khoe
PDK.Flow
Layout.Compiler
Postponed
Normal
Khoe
PDK.Flow
Layout.Compiler
Postponed
Normal
Khoe
PDK.Flow
NA
In.Planning
Normal
Hoang
PDK.Flow
Normal
Hoang
PDK.Flow
PDK.Flow
Postponed
Normal
Khoe
PDK.Flow
PDK.Flow
Postponed
Normal
Duong
PDK.Flow
Layout.Compiler
In.Planning
Normal
Duong
PDK.Flow
Layout.Compiler
In.Planning
Normal
Duong
ESF3-40GFS
Layout.Compiler
In.Planning
Normal
Duong
PDK.Flow
Layout.Compiler
In.Planning
Normal
Tri
PDK.Flow
Layout.Compiler
In.Progress
Normal
Khoe
PDK.Flow
PDK.Flow
In.Reviewing Normal
Hoang
PDK.Flow
Layout.Compiler
Completed
Normal
Duong
PDK.Flow
PDK.QA
In.Progress
Normal
Thanh
ESF3-40GFS
Layout.Compiler
In.Progress
Normal
Tri
PDK.Flow
Converted.Schematic
In.Planning
Normal
Tri
Amber
Converted.Schematic
In.Progress
Normal
Hoang
PDK.Flow
Layout.Compiler
Postponed
Normal
Tri
PDK.Flow
Layout.Compiler
Completed
Critical
Tri
Jade
PDK.Flow
In.Planning
Normal
Khoe
Amber
PDK.Flow
Completed
Normal
Khoe
ESF3-28UMC
Tape.Out
Completed
Normal
Khoe
Jade
LVS.Deck
In.Planning
Normal
Khoe
Jade
LVS.Deck
Completed
Normal
Khoe
PDK.Flow
PDK.Flow
Completed
Normal
Khoe
Quartz
Tech.Files
Completed
Normal
Duong
Quartz
DRC.Deck
In.Progress
Normal
Duong
Quartz
Tape.Out
In.Progress
Normal
Duong
Quartz
PDK.Flow
In.Planning
Normal
Duong
Jade
Tech.Files
Completed
Normal
Duong
Pearl
Foundry.PDK
In.Planning
Normal
Thanh
PDK.Flow
PDK.QA
In.Progress
Normal
Thanh
Target
Actual
Comments
8/31/2015
8/31/2015
8/31/2015
8/14/2015
8/21/2015
8/14/2015
8/14/2015
8/31/2015
8/14/2015
7/31/2015
8/7/2015
7/24/2015
7/31/2015
8/14/2015
8/14/2015
9/15/2015

lib management :
add prefix
8/7/2015
8/31/2015
7/27/2015
8/3/2015
8/4/2015
8/6/2015
8/5/2015
7/31/2015
8/7/2015
8/7/2015
8/10/2015
8/3/2015
8/14/2015
Working on a.Thuan's feedback
Task
Update Python PDK development system
DRC: implement and verify HV and memory rules

Fully verify the tapeout flow + Implement all manual steps
Review LV MOS pcells interface and apply for HV MOS pcells
Update primitive_devices to verify DRC/LVS
tapeout pfm_v1a3 and fix bug IPTAG for tapeout flow
Description
PDK QA command: Thanh/Khoe
Support unchecked status.
Review and fix bugs if any
Generate Test-patterns for DRC
Fully verify the tapeout flow + Implement all manual steps
Review LV MOS pcells interface and apply for HV MOS pcells
tapeout pfm_v1a3 and fix bug IPTAG for tapeout flow
Project.Code
PDK.Component
Status
Priority
Owner
PDK.Flow
PDK.QA
In.Planning
Normal
Thanh
Pearl
SST.PDK
In.Progress
Normal
Thanh
Pearl
SST.PDK
In.Planning
Normal
Thanh
PDK.Flow
Layout.Compiler
In.Planning
Normal
Thanh
ESF3-40GFS
Layout.Compiler
Postponed
Normal
Thanh
ESF3-40GFS
PDK.QA
In.Planning
Normal
Thanh
PDK.Flow
Layout.Compiler
In.Planning
Normal
Thanh
Pearl
Tape.Out
Completed
Normal
Thanh
Target
6/30/2015
7/10/2015
7/24/2015
7/24/2015
6/26/2015
7/10/2015
7/2/2015
Actual
Comments
Task
pdk gen command
Build DRC deck
Build LVS deck
Implement PDK port_db command
Add nhm, phm, nhm1 devices for 28umc
Cadence SKILL Language

Work with Parviz to generate ESF3-40GFS DTC (7*3) arrays for
Install the new version of Foundry Process Design Kit
HKMG cells
Work with Parviz to generate ESF3-40GFS WAT arrays for
Run the tapeout flow for pfm_355u16kx64_v1a2
Implement a SKILL function mchpEvaluateXLayoutPattern(d_CellView o_XLayoutPatternInf) to evaluate

Create a SKILL script to check size of NHZ
Virtuoso Design Environment SKILL
Python 2.7 Programming Language
Prepare PDK package to send out to the vendor

Update ESF3 to support generating rfiller cell
Released dtc_340gf256kx16_v1a0_ary, dtc_340gf256kx16_v2a0_ary, dtc_340gf2
Implement mchpAdjustWideMetal script
Convert ESF340GFS_WAT_TC0_CELL database
Implement programmable DR parser
Description
i.
Inputs:
array info
Install
LV pad
deckcell,
andpad
implement
HV(X*Y),
LVS deck
Create
cells
from the tech file)
ii. Output:
Supporting
pinaobjects
objects
defined
bycould
Cadence
Space-Base
Router,
Schematic:
simple (pin
schedule
(cell
symbol
be from
a fixed library,
should
such asbe
HVa library)
Layout/schematic
are clean
LVS MOS compiler
Implement
HV MOS pcells
by using
another
Implement the flow of these commands
- Understand Superflash PDK: DRC/LVS decks

- Update DRC/LVS deck to recognize the devices - done
- Add these device cells for the esf328sst - done
- Change HVUD to VLTM layer - inprogress
0)
Language
- Refer
40umcCharacteristics
internal design kit document
1) Creating Functions in SKILL
2) Data Structures
3) Arithmetic and Logical Expressions
4) Control Structures
5) I/O and File Handling
6) Advanced List Operations

HKMG cells

Understand
ESF1/ESF3
compiler
andtransistor
create the
userguide
document
When the Source
or Drain
of a NHZ
is detail
connected
to Vdd,
it is
defined as a pull-up. Could LVS find the NHZ pull-up and flag it if the NHZ
width is less than 5um?
It would be possible to check (recursively top-down) maintaining a list of
nets that are mapped to Vdd.
0) Install Eclipse, python 2.7, PyDev package.
1) Variables, Types and Declarations
2) Data Structures: list, tuple, dictionary, sequence, set, References
3) Flow controls: if/then, for/while, break
Database
Access
4) Functions
5) Regular Expression
6) File I/O
7) Modules and Packages
8) Classes and OOP
9) Standard Library: sys, os, subprocess
Prepare PDK package to send out to the vendor

Update ESF3 to support generating rfiller cell
Released dtc_340gf256kx16_v1a0_ary, dtc_340gf256kx16_v2a0_ary, dtc_340
Adjust/split two adjacent wide metal rectangle shapes into multiple rectangle shape
Convert ESF340GFS_WAT_TC0_CELL database
Implement programmable DR parser
Project.Code
PDK.Component
Status
Priority
Owner
PDK.Flow
PDK.Flow
In.Planning
Normal
Khoe
Emerald
DRC.Deck
In.Planning
Normal
Tri
Emerald
LVS.Deck
Postponed
Normal
Tri
Emerald
Layout.Library
In.Planning
Normal
Tri
PDK.Flow
PDK.Flow
In.Planning
Low
Khoe
PDK.Flow
Layout.Compiler
Postponed
Normal
Khoe
PDK.Flow
Layout.Compiler
Postponed
Normal
Khoe
PDK.Flow
Layout.Compiler
Completed
Normal
Duong
PDK.Flow
NA
In.Planning
Normal
Khoe
PDK.Flow
Converted.Layout.Li In.Planning
Normal
Khoe
PDK.Flow
PDK.Flow
Postponed
Normal
Khoe
PDK.Flow
PDK.Flow
In.Planning
Normal
Duong
PDK.Flow
Layout.Compiler
In.Planning
Normal
Duong
PDK.Flow
PDK.QA
In.Planning
Normal
Thanh
ESF3-28UMC
SST.PDK
In.Progress
Normal
Hoang
Training
Programming
In.Planning
Normal
Hoang
Pearl
SST.PDK
In.Progress
Normal
Thanh
ESF3-40GFS
Layout.Compiler
In.Progress
Normal
Tri
Pearl
SST.PDK
In.Planning
Normal
Thanh
Quartz
DRC.Deck
In.Planning
Normal
Duong
ESF3-40GFS
Layout.Compiler
In.Planning
Normal
Tri
Jade
Tape.Out
In.Planning
Normal
Khoe
PDK.Flow
Layout.Compiler
Completed
Normal
Khoe
ESF3-40GFS
Layout.Compiler
In.Planning
Normal
Tri
Pearl
SST.PDK
In.Planning
Normal
Thanh
ESF3-40GFS
Layout.Compiler
In.Progress
Normal
Thanh
ESF3-40GFS
PDK.QA
In.Planning
Normal
Thanh
PDK.Flow
Layout.Compiler
In.Planning
Normal
Thanh
Garnet
Converted.Schematic
In.Planning
Normal
Duong
Training
Programming
In.Planning
Normal
Hoang
Training
Programming
In.Planning
Normal
Hoang
Quartz
SST.PDK
Completed
Normal
Duong
ESF3-40GFS
Layout.Compiler
Completed
Normal
Tri
ESF3-40GFS
Layout.Compiler
Completed
Normal
Tri
PDK.Flow
Layout.Compiler
Completed
Normal
Khoe
ESF3-40GFS
Normal
Khoe
PDK.Flow
Layout.Compiler
Completed
Normal
Khoe
PDK.Flow
Layout.Compiler
In.Progress
Normal
Khoe
Target
Actual
6/12/2015
6/25/2015
Comments
6/26/2015
7/15/2015
6/26/2015
Updated LVS deck to recognize the devices
7/1/2015
6/30/2015
6/19/2015
6/19/2015
7/30/2015
7/3/2015
7/3/2015
6/19/2015
7/3/2015
6/19/2015
6/24/2015
6/26/2015
7/10/2015
7/3/2015
7/3/2015
6/25/2015
6/25/2015
6/24/2015
6/25/2015
6/24/2015
6/25/2015
6/29/2015
Task
pdk gen command
Build DRC deck
Build LVS deck
Update LVS deck for probecell device
Implement the latest internal designkit document from Jinho
Add nhm, phm, nhm1 devices for 28umc

create test-pattern for memory array rules

HKMG cells
Reconvert laydtc_340gf1024kx16_v0a0 database
Install the latest DRC deck (Ver.A.B_PK_AB)
Prepare SO package for 3 new WATs
Upgrade to support parsing layout pattern data

Create a clean DRC/LVS ESF3 template for all DTC arrays
Create a SKILL script to check size of NHZ
Description
i.
Inputs:
array info
Install
LV pad
deckcell,
andpad
implement
HV(X*Y),
LVS deck
Create
cells
from the tech file)
ii. Output:
Supporting
pinaobjects
objects
defined
bycould
Cadence
Space-Base
Router,
Schematic:
simple (pin
schedule
(cell
symbol
be from
a fixed library,
should
such asbe
HVa library)
Layout/schematic
are clean
LVS MOS compiler
Implement
HV MOS pcells
by using
another
Update LVS deck for probecell device
Implement the latest internal designkit document from Jinho
0) Install Eclipse, python 2.7, PyDev package.
-1)Understand
Superflash
PDK: DRC/LVS decks
Variables, Types
and Declarations
-2)Update
DRC/LVS
deck
to
recognize
the devices
Data Structures: list, tuple,
dictionary,
sequence, set, References
-3)Add
these
device
cells
for
the
esf328sst
Flow controls: if/then, for/while, break
-4)Change
HVUD to VLTM layer
Functions
-5)Refer
40umc
internal design kit document
Regular Expression
6) File I/O
8) Classes and OOP

create test-pattern for memory array rules

HKMG cells
Reconvert laydtc_340gf1024kx16_v0a0 database
Install the latest DRC deck (Ver.A.B_PK_AB)
Prepare SO package for 3 new WATs
Upgrade to support parsing layout pattern data

Create a clean DRC/LVS ESF3 template for all DTC arrays
Understand
ESF1/ESF3
compiler
andtransistor
create the
userguide
document
When the Source
or Drain
of a NHZ
is detail
connected
to Vdd,
it is
defined as a pull-up. Could LVS find the NHZ pull-up and flag it if the NHZ
width is less than 5um?
It would be possible to check (recursively top-down) maintaining a list of
nets that are mapped to Vdd.
Project.Code
PDK.Component
Status
Priority
Owner
PDK.Flow
PDK.Flow
In.Planning
Normal
Khoe
Emerald
DRC.Deck
In.Planning
Normal
Tri
Emerald
LVS.Deck
Postponed
Normal
Tri
Emerald
Layout.Library
In.Planning
Normal
Tri
PDK.Flow
PDK.Flow
In.Planning
Low
Khoe
PDK.Flow
Layout.Compiler
Postponed
Normal
Khoe
PDK.Flow
Layout.Compiler
Postponed
Normal
Khoe
PDK.Flow
Layout.Compiler
In.Progress
Normal
Duong
PDK.Flow
NA
In.Planning
Normal
Khoe
PDK.Flow
Normal
Khoe
PDK.Flow
PDK.Flow
In.Progress
Normal
Khoe
Quartz
Layout.Compiler
Completed
Normal
Duong
Quartz
Layout.Compiler
Completed
Normal
Duong
PDK.Flow
PDK.Flow
In.Planning
Normal
Duong
PDK.Flow
Layout.Compiler
Postponed
Normal
Duong
PDK.Flow
PDK.QA
In.Planning
Normal
Thanh
ESF3-28UMC
SST.PDK
In.Progress
Normal
Hoang
Training
Programming
In.Planning
Normal
Hoang
Pearl
SST.PDK
In.Progress
Normal
Thanh
ESF3-40GFS
Layout.Compiler
In.Progress
Normal
Tri
Pearl
SST.PDK
Completed
Normal
Thanh
Pearl
SST.PDK
In.Planning
Normal
Thanh
Quartz
DRC.Deck
In.Planning
Normal
Duong
ESF3-40GFS
Layout.Compiler
In.Planning
Normal
Tri
ESF3-40GFS
Normal
Khoe
Jade
DRC.Deck
Completed
Normal
Khoe
Jade
Tape.Out
In.Planning
Normal
Khoe
ESF3-28UMC
Tape.Out
Completed
Normal
Khoe
ESF3-28UMC
Tape.Out
Completed
Normal
Khoe
PDK.Flow
Layout.Compiler
In.Planning
Normal
Khoe
ESF3-40GFS
Layout.Compiler
In.Planning
Normal
Tri
ESF3-40GFS
Layout.Compiler
Completed
Normal
Tri
Pearl
SST.PDK
In.Planning
Normal
Thanh
ESF3-40GFS
Layout.Compiler
In.Planning
Normal
Thanh
ESF3-40GFS
PDK.QA
In.Planning
Normal
Thanh
PDK.Flow
Layout.Compiler
In.Planning
Normal
Thanh
Garnet
Converted.Schematic
In.Planning
Normal
Duong
Target
Actual
Comments
6/12/2015
6/26/2015
6/17/2015
6/18/2015
6/30/2015
6/30/2015
Updated LVS deck to recognize the devices
6/12/2015
6/19/2015
6/18/2015
6/19/2015
7/15/2015
6/19/2015
6/17/2015
6/16/2015
6/26/2015
6/17/2015
6/18/2015
6/19/2015
6/19/2015
6/18/2015
6/19/2015
6/24/2015
6/24/2015
6/30/2015
6/30/2015
Task
pdk gen command
pdk create/update/install commands
Run the tapeout flow for WAT Superflash and OTP
Implement a script to:
1) To reduce L: shrink POLY to center. The sample script was able to shrink
POLY.
2) To reduce W: shrink DIFF to center. Need to recognize the DIFF
intersecting the POLY being shrunk.
i. Inputs: pad cell, pad array infoDescription

(X*Y), test-line size, cell placement info
i.
Implement
HV
LVS
rule
deck
template.
ii. Implement
python-based
functions to parse
Calibre
ruleenter
deskthen
files.get
routing
info (i.e.
min metal width/spacing,
if users
do not
from the tech file)
ii. Output:
Supporting
pinaobjects
objects
defined
bycould
Cadence
Space-Base
Router,
Schematic:
simple (pin
schedule
(cell
symbol
be from
a fixed library,
should
be
a
generic
term
of
Cadence)
such as HV library)
Layout/schematic
aredatabases:
Compare
two specified
another
Run the tapeout flow for WAT Superflash and OTP
Implement a script to:
1) To reduce L: shrink POLY to center. The sample script was able to
shrink POLY.
2) To reduce W: shrink DIFF to center. Need to recognize the DIFF
intersecting the POLY being shrunk.
Project.Code
PDK.Component
Status
Priority
Owner
PDK.Flow
PDK.Flow
In.Planning
Normal
Khoe
PDK.Flow
PDK.Flow
In.Planning
Low
Khoe
PDK.Flow
Layout.Compiler
Postponed
Normal
Khoe
PDK.Flow
Layout.Compiler
Postponed
Normal
Khoe
PDK.Flow
NA
In.Planning
Normal
Khoe
PDK.Flow
Normal
Khoe
PDK.Flow
PDK.Flow
In.Progress
Normal
Khoe
ESF3-28UMC
PDK.Flow
In.Progress
Normal
Khoe
ESF3-40GFS
PDK.Flow
In.Planning
Normal
Khoe
Target
6/19/2015
6/5/2015
6/8/2015
Actual
Comments
Task
pdk gen command
Build DRC deck
Build LVS deck
verify for the following test case:
Study Cadence VSR router
1) LVS clean for the starting DTC DB
2) Remove the filler to create a smaller array in Y
3) Remove the old routing from XDEC to the array
4) Move the XDEC block far away from the array
5) Do space routing
6) Run LVS again for the update DTC, has to be clean.
Install the latest DRC foundry deck

Convert Schematic database of ESF3-40GFS
Review DRC errors of dtc4m_340gf_v1a0_corelvs_temp
Install the latest LVS foundry deck
Add nhm, nhm1, phm devices
Review HVD_*** rules catch MOSN,MOSP logic violation
Update HV Metal/Via Spacing Rule

HKMG cells
re-generated the arrays with the updated routing from TD
Run tapeout flow for dtc_328u256kx16_v1a0, dtc_328u256kx16_v2a0,
dtc_328u256kx16_v3a0, WAT
Review dtc4m_340u_v3a2_corelvs_temp.drc violations
Description
i.
Inputs:
array info
Install
LV pad
deckcell,
andpad
implement
HV(X*Y),
LVS deck
Create
cells
from the tech file)
ii. Output:
Supporting
pinaobjects
objects
defined
bycould
Cadence
Space-Base
Router,
Schematic:
simple (pin
schedule
(cell
symbol
be from
a fixed library,
should
such asbe
HVa library)
Layout/schematic
are clean LVS
Implement
HV MOS pcells
another
PDK
QA command:
Support
drawing anThanh/Khoe
array of VIAs in the ring
Generate
Test-patterns
forcase:
DRC
verify
for the
following test
Study
Cadence
router
0)
Install
Eclipse, VSR
python
2.7, PyDev package.
1) Variables,
and
Declarations
LVS cleanTypes
for the
starting
DTC DB
2) Data
Structures:
list,
dictionary,
sequence,
Remove
the filler
totuple,
create
a smaller
array in set,
Y References
3)
Flow
controls:
if/then,
for/while,
break
3) Remove the old routing from XDEC to the array
4)
4) Functions
Move the XDEC block far away from the array
5)
Regular
Expression
5) Do space
routing
6) File I/O
6) Run LVS again for the update DTC, has to be clean.
8) Classes and OOP
Install the latest DRC foundry deck

Convert Schematic database of ESF3-40GFS
Review DRC errors of dtc4m_340gf_v1a0_corelvs_temp
Install the latest LVS foundry deck
Add nhm, nhm1, phm devices
Review HVD_*** rules catch MOSN,MOSP logic violation
Update HV Metal/Via Spacing Rule

HKMG cells
re-generated the arrays with the updated routing from TD
Run tapeout flow for dtc_328u256kx16_v1a0, dtc_328u256kx16_v2a0,
dtc_328u256kx16_v3a0, WAT
Review dtc4m_340u_v3a2_corelvs_temp.drc violations
Project.Code
PDK.Component
Status
Priority
Owner
PDK.Flow
PDK.Flow
In.Planning
Normal
Khoe
Emerald
DRC.Deck
In.Planning
Normal
Tri
Emerald
LVS.Deck
Postponed
Normal
Tri
Emerald
Layout.Library
In.Planning
Normal
Tri
PDK.Flow
PDK.Flow
In.Planning
Low
Khoe
PDK.Flow
Layout.Compiler
Postponed
Normal
Khoe
PDK.Flow
Layout.Compiler
Postponed
Normal
Khoe
PDK.Flow
Layout.Compiler
Postponed
Normal
Khoe
PDK.Flow
NA
In.Planning
Normal
Khoe
PDK.Flow
Normal
Khoe
PDK.Flow
PDK.Flow
Postponed
Normal
Khoe
PDK.Flow
Layout.Compiler
Postponed
Normal
Duong
PDK.Flow
PDK.QA
In.Planning
Normal
Thanh
Training
NA
Completed
Normal
Hoang
DTC.Compiler
Layout.Compiler
In.Progress
Normal
Hoang
Training
Programming
In.Planning
Normal
Hoang
Quartz
DRC.Deck
Completed
Normal
Duong
Pearl
SST.PDK
In.Progress
Normal
Thanh
ESF3-40GFS
Layout.Compiler
In.Progress
Normal
Tri
ESF3-40GFS
Schematic.Library
Completed
Normal
Tri
Pearl
SST.PDK
In.Planning
Normal
Thanh
Quartz
SST.PDK
Completed
Normal
Thanh
Quartz
DRC.Deck
In.Progress
Normal
Duong
Quartz
DRC.Deck
Completed
Normal
Duong
Quartz
DRC.Deck
Completed
Normal
Duong
Quartz
DRC.Deck
Completed
Normal
Duong
Quartz
DRC.Deck
In.Planning
Normal
Duong
Quartz
Layout.Compiler
Completed
Normal
Khoe
ESF3-28UMC
Tape.Out
Completed
Normal
Khoe
ESF3-40GFS
Layout.Library
Completed
Normal
Khoe
Target
Actual
Comments
5/22/2015
5/15/2015
5/15/2015
5/15/2015
5/15/2015
5/29/2015
-Apply tool auto route net in

esf3_28umc database
- Solving practical issues
6/3/2015
-Apply tool auto route net in

esf3_28umc database
- Solving practical issues
5/29/2015
6/5/2015
6/5/2015
5/25/2015
6/10/2015
5/27/2015
6/2/2015
5/28/2015
5/27/2015
5/26/2015
6/12/2015
5/25/2015
5/28/2015
5/27/2015
Task
pdk gen command
Create DK r2.0
Genrate ESF3-40UMC arrays
Generate HKMG arrays and check LVS
Description
ii.
Implement
python-based
parse Calibre
ruleplacement
desk files.info
i. Inputs:
pad cell,
pad array functions
info (X*Y),totest-line
size, cell
Using the
routing
infonew
(i.e.approach:
min metal width/spacing, if users do not enter then get
a) LV the
Cadence
library from foundry
from
tech file)
b)
HV Cadence library from SST
ii. Output:
Supporting
pinaobjects
objects
defined
bycould
Cadence
Space-Base
Router,
Schematic:
simple (pin
schedule
(cell
symbol
be from
a fixed library,
should
such asbe
HVa library)
Layout/schematic
are clean LVS
Implement
HV MOS pcells
another
Project.Code
PDK.Component
Status
Priority
Owner
PDK.Flow
PDK.Flow
In.Planning
Normal
Khoe
PDK.Flow
PDK.Flow
In.Planning
Low
Khoe
Quartz
SST.PDK
Completed
Critical
Khoe
PDK.Flow
Layout.Compiler
Postponed
Normal
Khoe
PDK.Flow
Layout.Compiler
Postponed
Normal
Khoe
PDK.Flow
Layout.Compiler
Postponed
Normal
Khoe
PDK.Flow
NA
In.Planning
Normal
Khoe
PDK.Flow
Normal
Khoe
PDK.Flow
PDK.Flow
Postponed
Normal
Khoe
Quartz
DRC.Deck
Completed
Normal
Khoe
ESF3-28UMC
Layout.Library
Completed
Critical
Khoe
Target
5/21/2015
5/15/2015
5/15/2015
5/18/2015
5/15/2015
Actual
Comments
Task
pdk gen command
Build DRC deck
Build LVS deck
Create DK r2.0
Use VSR router to route Array-->XDEC nets
Release DK r5.0.1 to DE teams
Update device lib, DRC/LVS/PEX for the DK r3.4 and r5.x using the latest PDK
Implement Voltage-Aware DRC: HV metal/via spacing rules
Implement Voltage Extraction DRC for HV metal/Via spacing rule check
Install the latest DRC/LVS foundry deck
Update coversheet about pregen difference between r3.4 and r5.0.1
Install new version of PDK (spice model + ruledeck) from foundry directory
Run LVS for the rest tapeout database by Interactive, no need command line afte
Convert dtc_340u1024kx16_v3a2, dtc_340gf1024kx16_v0a0 to 40GFS
ESF3-40GFS DTC arrays
Review metal2 dummy missing in pfm_1180sl136kx8_v1a1
Create 3templates to generate ESF3-40GFS DTC arrays
Implement DRC/LVS deck
Install hspice models - esf345spicea2
Update pregen to support High-K Metal Gate Process
Update ESF3 to support HKMG array
Description
Install LV deck and implement HV LVS deck
Create
Techprimitive_devices
cells
i. Inputs:
pad cell, pad array info
Using the
routing
infonew
(i.e.approach:
a) LV the
Cadence
from
tech file)
b)
ii. Output:
Supporting
pinaobjects
objects
defined
bycould
Cadence
Space-Base
Router,
Schematic:
simple (pin
schedule
(cell
symbol
be from
a fixed library,
should
such asbe
HVa library)
Layout/schematic
are clean LVS
Implement
HV MOS pcells
another
PDK QA command:
Support
1) DRC: implement missing rules (array rules etc.)
2)
Pregen:
add pregen
0)
Install
Eclipse,
python step:
2.7,
Generate
Test-patterns
forPyDev
DRC package.
a) Include
MTL3
dummy
filling
1) Variables,
Types
and
Declarations
b) Should
not include
NNII
(Nselect),
LV18 (Thickox),
ZNVT (Native), REST
2) Data
Structures:
list, tuple,
dictionary,
sequence,
set, References
(Nwel_res),
NVT_HVT
theybreak
are now drawn layers
3)
Flow controls:
if/then,since
for/while,
3) Functions
Verification:
4)
5) Regular
Expression pfm_1180sl64kx32_v1a1 as a QA database, remove
a) Use after-pregen
6)
File
I/O
the MTL3 dummy fill, then stream in
7) Modules
and
Packages
b) Pregen
should
be run before DRC/LVS (similar ESF340UMC, consult
8)
Classes
and
OOP
Khoe). DRC/LVS should be done on after-pregen DB
1.
Detect HV
and LV
nets
the following rules: (basically LV override HV)
9) Standard
Library:
os,as
subprocess
c) Run LVL
of thissys,
pfm_1180sl64kx32_v1a1
v.s. the DBs sent to eWave
a.
For aPDK
transistor:
Latest
was downloaded at
i.
If a net connected to only terminals of HV transistors, then it would have 2
/iplicense/cad/technology/esf1-180slt/opus61/designkit_r5.0.1/foundry
voltage levels: GND and HV -> it detect the net voltage depend on the mos
Voltage-Aware
type it connectDRC:
to ? HV metal/via spacing rules
ii. If a net connected to at least 1 terminal of LV transistors, then it would
have
voltage
levels:
GNDfoundry
and LV deck
Install2the
latest
DRC/LVS
b. For a resistor, if one end has LV level, then the other end will have 2
voltage
levels also: about
GND and
LV. Otherwise
of them
GND and HV
Update coversheet
pregen
differenceboth
between
r3.4have
and r5.0.1
c. For a cap, the voltage level is not propagated
Run LVS for the rest tapeout database by Interactive, no need command line a
Generate array and Fix LVS check
Review metal2 dummy missing in pfm_1180sl136kx8_v1a1
Create 3templates to generate ESF3-40GFS DTC arrays
Implement DRC/LVS deck
Install hspice models - esf345spicea2
Update pregen to support High-K Metal Gate Process
Update ESF3 to support HKMG array
Project.Code
PDK.Component
Status
Priority
Owner
PDK.Flow
PDK.Flow
In.Planning
Normal
Khoe
Emerald
DRC.Deck
In.Planning
Normal
Tri
Emerald
LVS.Deck
Postponed
Normal
Tri
Emerald
Layout.Library
In.Planning
Normal
Tri
PDK.Flow
PDK.Flow
In.Planning
Low
Khoe
Quartz
SST.PDK
In.Planning
Low
Tri
PDK.Flow
Layout.Compiler
Postponed
Normal
Khoe
PDK.Flow
Layout.Compiler
Postponed
Normal
Khoe
PDK.Flow
Layout.Compiler
Postponed
Normal
Khoe
PDK.Flow
NA
In.Planning
Normal
Khoe
PDK.Flow
Normal
Khoe
PDK.Flow
PDK.Flow
Postponed
Normal
Khoe
PDK.Flow
Layout.Compiler
Postponed
Normal
Duong
PDK.Flow
PDK.QA
In.Planning
Normal
Thanh
DTC.Compiler
Layout.Compiler
In.Progress
Normal
Hoang
Pearl
DRC.Deck
Postponed
Normal
Thanh
Training
Programming
In.Planning
Normal
Hoang
Pearl
SST.PDK
In.Progress
Normal
Thanh
Quartz
DRC.Deck
Completed
Critical
Duong
Quartz
DRC.Deck
In.Progress
Critical
Duong
Quartz
DRC.Deck
In.Planning
Normal
Duong
Pearl
SST.PDK
In.Progress
Normal
Thanh
Pearl
SST.PDK
Completed
Normal
Thanh
Pearl
SST.PDK
Completed
Normal
Thanh
ESF3-40GFS
Converted.Schematic
Completed
Critical
Tri
ESF3-40GFS
Layout.Library
Completed
Critical
Khoe
Quartz
DRC.Deck
In.Planning
Normal
Tri
Pearl
SST.PDK
Completed
Normal
Thanh
Quartz
DRC.Deck
In.Progress
Normal
Tri
ESF3-40GFS
SST.PDK
Completed
Critical
Khoe
ESF3-40GFS
PDK.Install.Hspice
Completed
Critical
Khoe
ESF3-28UMC
Pregen.Deck
Completed
Critical
Khoe
PDK.Flow
Layout.Compiler
Completed
Critical
Khoe
ESF3-28UMC
Layout.Library
In.Progress
Critical
Khoe
Target
Actual
Comments
5/22/2015
5/15/2015
5/15/2015
5/15/2015
5/15/2015
5/29/2015
-running the VSR on the real

database
-Used ESF3 compiler to
generate DTC arrays for
testing
-Verified that VSR can work
well to route two different
vertical pitch of arrays of bins
5/22/2015
5/18/2015
5/14/2015
5/20/2015
5/29/2015
5/18/2015
5/13/2015
Need to confirm the number of NHWLs terminal in HV LVS rule?
5/13/2015
5/8/2015
5/8/2015
5/18/2015
5/14/2015
5/15/2015
5/12/2015
5/13/2015
5/13/2015
5/14/2015
5/15/2015
minal in HV LVS rule?
Task
pdk gen command
Build DRC deck
Build LVS deck
Create DK r2.0
Update HV VPP cell by replacing N+ DIFF resistor by N+ Poly resistor

Cadence Virtuoso Custom IC - IC6.1_Front_to_Back_Overview
ESF3-28 DTC arrays

Implement Voltage-Aware DRC: HV metal/via spacing rules
Install the latest DRC/LVS foundry deck
Add 2 devices nl11cap, nl25cap into the library LibESF340UMC
Update antenna script to report antenna gate area.
Update pretrigger to convert cdl format from opus 5 to opus6

Run LVS for the rest tapeout database by Interactive, no need command line afte
ESF3-40GFS DTC arrays
Update pregen deck to support XMT[1,2,3], XCNT, XPOL to support 28OTP
Update techfile/display/layermap
Description
Create
Techprimitive_devices
cells
i. Inputs:
pad cell, pad array info
Using the
routing
infonew
(i.e.approach:
a) LV the
Cadence
from
tech file)
b)
ii. Output:
Supporting
pinaobjects
objects
defined
bycould
Cadence
Space-Base
Router,
Schematic:
simple (pin
schedule
(cell
symbol
be from
a fixed library,
should
such asbe
HVa library)
Layout/schematic
are clean LVS
Implement
HV MOS pcells
1.
Cadence aApplication
Infrastructure
1day
Implement
command-line
script to port
a database from a specified PDK to
a.
Cadence Library Structure
another
b.
Cadence the
Library
File
Implement
flowDefinition
of these commands
c. TechFile
PDK
QA command:
Support
drawing
anThanh/Khoe
array
VIAs (array
in the ring
d.
Ref:
0)
Install
Eclipse, python
2.7,ofPyDev
package.
1)
DRC: implement
missing
rules
rules etc.)
Support
unchecked
status.
1)
Variables,
Types
and Declarations
i.
/pkg/ic-6.1.6.500.9/doc/caiuser/caiuser.pdf
2)
Pregen:
add
pregen
step:
and fix bugs

if anydictionary, sequence, set, References
2)
Data
Structures:
tuple,
ii. Review
/pkg/ic-6.1.6.500.9/doc/techfileuser/techfileuser.pdf
a) Include
MTL3list,
dummy
Generate
Test-patterns
forfilling
DRC
3)
controls:
if/then,
for/while,
break
2. Flow
Layout
Design:
- 1day
b) Should
not include
NNII (Nselect), LV18 (Thickox), ZNVT (Native), REST
4)
Functions
a.
Ref: /pkg/ic-6.1.6.500.9/doc/vxlhelp/vxlhelp.pdf
(Nwel_res),
NVT_HVT since they are now drawn layers
5) Regular Expression
b.
Lab:
/iplicense/tdcad/training/Virtuoso_Custom_IC_and_Sign3)
Verification:
6) File I/O
off_Flow/IC6.1_Front_to_Back_Overview
a) Use after-pregen
7) Modules
and Packagespfm_1180sl64kx32_v1a1 as a QA database, remove
3.
Schematic
1daystream in
the
MTL3
dummy
8) Classes and Design
OOP fill, then
a.
Ref:
/pkg/ic-6.1.6.500.9/doc/comphelp/comphelp.pdf
b) PregenLibrary:
shouldsys,
be os,
runsubprocess
before DRC/LVS (similar ESF340UMC, consult
9) Standard
b.
Lab: DRC/LVS
/iplicense/tdcad/training/Virtuoso_Custom_IC_and_SignKhoe).
should
be
done
after-pregen DB
To reduce the leakge of N+ DIFFon
resistors
c) Run LVL of this pfm_1180sl64kx32_v1a1 v.s. the DBs sent to eWave
Latest
PDK wasDescription
downloaded
at
4. Component
Format
1day
/iplicense/cad/technology/esf1-180slt/opus61/designkit_r5.0.1/foundry
a.
Ref: /pkg/ic-6.1.6.500.9/doc/cdfuser/cdfuser.pdf
5. Virtuoso Analog Design Environment 1day
a. Choosing the Design - Open the Schematic
b.
Displaying
the
Simulation
Window
Generate
array
and
Fix LVS check
c. Choosing a Simulator
Voltage-Aware
DRC: HV
metal/via spacing rules
d. Setting the Model
Path
e.
Setting
Environment
Options
Install
the Simulation
latest DRC/LVS
foundry deck
f. Setting Design Variables
Add
2 devices
nl11cap,
nl25cap into the library LibESF340UMC
g. Setting
Up your
Analysis
h.
Selecting
Datascript
to Save
and Plot
Update
antenna
to report
antenna gate area.
i. Running a Simulation
j. Plotting the Results
k. Ref: /pkg/ic-6.1.6.500.9/doc/adexl/adexl.pdf
6. Stream In/Out Verilog/Cdl/auCdl/hspiceD netlisting 1day
a. How the Netlister Works
b. How to run Verilog/Cdl/auCdl/hspiceD netlisters
Update pretrigger to convert cdl format from opus 5 to opus6

Run LVS for the rest tapeout database by Interactive, no need command line a
Generate array and Fix LVS check
Update pregen deck to support XMT[1,2,3], XCNT, XPOL to support 28OTP
Update techfile/display/layermap
Project.Code
PDK.Component
Status
Priority
Owner
PDK.Flow
PDK.Flow
In.Planning
Normal
Khoe
Emerald
DRC.Deck
In.Planning
Normal
Tri
Emerald
LVS.Deck
Postponed
Normal
Tri
Emerald
Layout.Library
In.Planning
Normal
Tri
PDK.Flow
PDK.Flow
In.Planning
Low
Khoe
Quartz
SST.PDK
In.Planning
Low
Tri
PDK.Flow
Layout.Compiler
In.Progress
Normal
Khoe
PDK.Flow
Layout.Compiler
In.Progress
Normal
Khoe
PDK.Flow
Layout.Compiler
In.Reviewing Normal
Khoe
PDK.Flow
NA
In.Planning
Normal
Khoe
PDK.Flow
Normal
Khoe
PDK.Flow
PDK.Flow
Postponed
Normal
Khoe
PDK.Flow
Layout.Compiler
Postponed
Normal
Duong
PDK.Flow
PDK.QA
In.Planning
Normal
Thanh
DTC.Compiler
Layout.Compiler
In.Progress
Normal
Hoang
Pearl
DRC.Deck
Postponed
Normal
Thanh
Training
Programming
In.Planning
Normal
Hoang
Pearl
Schematic.Library
Completed
Critical
Thanh
Pearl
SST.PDK
In.Planning
Normal
Thanh
Training
NA
Completed
Normal
Hoang
ESF3-28UMC
Layout.Library
Completed
Critical
Khoe
Quartz
DRC.Deck
In.Progress
Critical
Duong
Quartz
DRC.Deck
In.Planning
Normal
Duong
Quartz
DRC.Deck
Completed
Normal
Duong
Pearl
SST.PDK
Completed
Normal
Thanh
Pearl
SST.PDK
Completed
Normal
Thanh
Pearl
SST.PDK
In.Planning
Normal
Thanh
Pearl
SST.PDK
In.Planning
Normal
Thanh
Pearl
SST.PDK
In.Planning
Normal
Thanh
ESF3-40GFS
Converted.Schematic
In.Progress
Critical
Tri
ESF3-40GFS
Layout.Library
In.Progress
Critical
Khoe
Quartz
DRC.Deck
In.Planning
Normal
Duong
ESF3-28UMC
Pregen.Deck
Completed
Normal
Khoe
ESF3-40GFS
SST.PDK
Completed
Normal
Khoe
Target
Actual
Comments
5/22/2015
5/15/2015
5/15/2015
5/15/2015
5/15/2015
5/15/2015
5/29/2015
5/22/2015
4/23/2015
Low priority than updating the HV deck
5/7/2015
5/11/2015
5/15/2015
5/22/2015
5/5/2015
5/6/2015
5/7/2015
5/8/2015
5/13/2015
5/13/2015
5/8/2015
5/8/2015
5/15/2015
5/5/2015
5/5/2015

Task
pdk gen command
Build DRC deck
Build LVS deck
Create DK r2.0
Develop a simple placement compiler
Update Schematic Convert tool to support SVS check
Update Semiconductor Training Program
Run tapeout flow for tc_1180sl64kx32_v1a2
Upgrade CONT_OPT_MOS compiler to support more requirements
Fundamentals of Electronic Design Automation
Update HV VPP cell by replacing N+ DIFF resistor by N+ Poly resistor

Update SPICE library for both r3.4 and r5.x
Fundamentals of Flash Memory Technology
Cadence Virtuoso Custom IC - IC6.1_Front_to_Back_Overview
ESF3-28 DTC arrays

ESF3 array complier
Description
Create Techprimitive_devices cells
thepad
new
approach:
i.Using
Inputs:
cell,
pad array info (X*Y), test-line size, cell placement info
a)
LV
Cadence
library
foundry
(each cell will have pinfrom
info),
cell DR tables (i.e. a table from MOS compiler),
b)
HV
Cadence
library
from
SST
routing
info
(i.e.
min
metal
width/spacing,
if users
not enter
then
To place many test lines together. This seems
to bedosimilar
to the
topget
from
the tech
file)array compiler now.
floorplan
of ESF3
ii. Output:
Supporting
pinaobjects
objects
defined
bycould
Cadence
Space-Base
Router,
Schematic:
simple (pin
schedule
(cell
symbol
be from
a fixed library,
should
be
a
generic
term
of
Cadence)
such as HV library)
Layout/schematic
are clean LVS
Implement
HV MOS pcells
another
PDK
QA command:
Support
1)
DRC: implement
missing
Generate
Test-patterns
forrules
DRC (array rules etc.)
2)
addafter
pregen
step:
DoPregen:
SVS check
converting
a) Include MTL3 dummy filling
b) Should not include NNII (Nselect), LV18 (Thickox), ZNVT (Native), REST
(Nwel_res), NVT_HVT since they are now drawn layers
To be familiar with basic concepts in Electronic Design Automation:
3) Verification:
1. Logic design automation
a) Use
after-pregen
as a QA database, remove
0) Install
pythonpfm_1180sl64kx32_v1a1
2.7, PyDev package.
1.1.Eclipse,
Modeling
Update
Semiconductor
Training
Program
the
MTL3
dummy
fill,
then
stream
in
1) Variables,
Typesverification
and Declarations
1.2. Design
b) Pregen
should
betuple,
run before
DRC/LVS
(similar
2) Data
Structures:
list,
dictionary,
sequence,
set,ESF340UMC,
References consult
1.3.
Logic
synthesis
Run
tapeout
flow
for
tc_1180sl64kx32_v1a2
Khoe).
DRC/LVS
should
be
done
on
after-pregen
DB
3)
Flow
controls:
if/then,
for/while,
break
2. Physical design automation
4) Functions
c) Run
of this pfm_1180sl64kx32_v1a1 v.s. the DBs sent to eWave
2.1. LVL
Floorplanning
5)
Regular
Expression
2.2.CONT_OPT_MOS
Placement
Upgrade
compiler to support more requirements
6) File 2.3.
I/O Routing
7) Modules
and Packages
2.4. Physical
verification
8) Classes and OOP
To reduce the leakge of N+ DIFF resistors

To use the latest SPICE models, including nvhp
a. Ref: /pkg/ic-6.1.6.500.9/doc/vxlhelp/vxlhelp.pdf
b. Lab: /iplicense/tdcad/training/Virtuoso_Custom_IC_and_Signoff_Flow/IC6.1_Front_to_Back_Overview
3. Schematic Design 1day
a. Ref: /pkg/ic-6.1.6.500.9/doc/comphelp/comphelp.pdf
Latest
PDK
was
downloaded
at
To Lab:
be familiar
with
basic concepts
in Flash Memory Technology:
b.
/iplicense/tdcad/training/Virtuoso_Custom_IC_and_Sign/iplicense/cad/technology/esf1-180slt/opus61/designkit_r5.0.1/foundry
1.
Floating
gate
transistor
2. Cross-point
memory array
4. Component
Description
Format 1day
3.
Flash
Cell
Basic
Operation:
Read/Erase/Program
a. Ref: /pkg/ic-6.1.6.500.9/doc/cdfuser/cdfuser.pdf
4. Flash Analog
MemoryDesign
Architecture
5. Virtuoso
Environment 1day
5.
Three
generations
of
Embedded
SuperFlash split gate cell
a. Choosing the Design - Open
the Schematic
b.
Displaying
the
Simulation
Window
Generate
array
and
Fix LVS check
c. Choosing a Simulator
Support
routing
offset
in X, fix bugs of creating routing cell
d. Setting
the Model
Path
e. Setting Simulation Environment Options
f. Setting Design Variables
g. Setting Up your Analysis
h. Selecting Data to Save and Plot
i. Running a Simulation
j. Plotting the Results
k. Ref: /pkg/ic-6.1.6.500.9/doc/adexl/adexl.pdf
6. Stream In/Out Verilog/Cdl/auCdl/hspiceD netlisting 1day
a. How the Netlister Works
b. How to run Verilog/Cdl/auCdl/hspiceD netlisters
c. Ref:
i. /pkg/ic-6.1.6.500.9/doc/ossref/ossref.pdf
ii. /pkg/ic-6.1.6.500.9/doc/transrefOA/transrefOA.pdf
Project.Code
PDK.Component
Status
Priority
Owner
PDK.Flow
PDK.Flow
In.Planning
Normal
Khoe
Emerald
DRC.Deck
In.Planning
Normal
Tri
Emerald
LVS.Deck
In.Progress
Normal
Tri
Emerald
Layout.Library
In.Planning
Normal
Tri
PDK.Flow
PDK.Flow
In.Planning
Low
Khoe
Quartz
SST.PDK
In.Planning
Low
Tri
PDK.Flow
Layout.Compiler
In.Planning
Low
Duong
PDK.Flow
Layout.Compiler
Postponed
Normal
Duong
PDK.Flow
Layout.Compiler
Postponed
Normal
Duong
PDK.Flow
Layout.Compiler
In.Reviewing Normal
Duong
PDK.Flow
NA
In.Planning
Normal
Khoe
PDK.Flow
Normal
Khoe
PDK.Flow
PDK.Flow
Postponed
Normal
Khoe
PDK.Flow
Layout.Compiler
In.Progress
Normal
Duong
PDK.Flow
PDK.QA
In.Planning
Normal
Thanh
PDK.Flow
Converted.Schematic
Completed
Normal
Tri
DTC.Compiler
Layout.Compiler
In.Planning
Normal
Hoang
Pearl
DRC.Deck
Postponed
Normal
Thanh
NA
NA
In.Planning
Normal
Thanh
Pearl
Tape.Out
Completed
Critical
Thanh
ESF3-28UMC
Layout.Compiler
Completed
Normal
Duong
Training
Semi.Tech
Completed
Normal
Hoang
Training
Programming
In.Planning
Normal
Hoang
Pearl
Schematic.Library
In.Progress
Critical
Thanh
Pearl
SPICE.Library
In.Planning
Normal
Thanh
Pearl
SST.PDK
In.Planning
Normal
Thanh
Training
NA
Completed
Normal
Hoang
Training
NA
In.Progress
Normal
Hoang
ESF3-28UMC
Layout.Library
In.Progress
Normal
Khoe
NA
Layout.Compiler
Completed
Normal
Khoe
Target
4/9/2015
5/4/2015
4/17/2015
4/17/2015
4/20/2015
4/13/2015
4/17/2015
4/17/2015
5/8/2015
4/22/2015
5/29/2015
5/15/2015
4/20/2015
4/17/2015
4/23/2015
4/22/2015
5/4/2015
4/23/2015
Actual
Comments

4/23/2015
5/6/2015
4/29/2015
4/22/2015
Task
Update DesignKit and coversheet document
Convert Schematic schdtc_328u256kx16_v2a0 from 40umc to 28umc
Install the new SPICE model
Update DK 3.4 to support Calibre DRC/LVS interactive, Fix CDL netlisting
Debug LVS problem
Build template for 28nm DTC array configuration
Linux Operating System
To be familiar with:
1. What Is Linux?
Description
2. Linux Directory Structure
3. Linux File Permissions
Update
DesignKit
coversheet
document
4. Wildcards
andand
Regular
Expressions
5. I/O Redirection
Convert
Schematic schdtc_328u256kx16_v2a0 from 40umc to 28umc
6. Environment Variables and Configuration: .cshrc, setenv
Install
the new
SPICE about:
model:
7. Basic
commands
uss/process/spice/splib/umc/ESF3-40/esf340spicea4
7.1 Command Handling: where, whereis, which, man, history, alias...
7.1 File Handling: mkdir, ls, cd, pwd, cp, mv, rm, find,vim,...
Update7.2
DKText
3.4Processing:
to supportcat,
Calibre
echo,DRC/LVS
grep, wc,interactive,
sort, sed... Fix CDL netlisting
7.3 System Administration: chmod, chown, su, passwd, who,...
Debug7.4
LVSProcess
problem
Management: ps, kill, top,...
7.5 Archival: tar, zip, unzip,...
Build template
for 28nm
DTC array configuration
7.6 Network:
ssh, scp,...
7.7 File Systems: du, df, quota,...
7.8 Version Management: cvs add/checkout/checkin/export/remove/import...
Project.Code
PDK.Component
Status
Priority
Owner
Quartz
DRC.Deck
Completed
Critical
Khoe
ESF3-28UMC
Converted.Schematic
Completed
Critical
Tri
Quartz
SPICE.Library
Completed
Critical
Duong
Pearl
SST.PDK
Completed
Critical
Khoe
Pearl
LVS.Deck
Completed
Critical
Thanh
ESF3-28UMC
Layout.Compiler
Completed
Critical
Duong
Training
Unix
Completed
Normal
Hoang
Target
4/13/2015
4/10/2015
4/9/2015
4/16/2015
4/16/2015
4/16/2015
4/18/2015
Actual
Comments
Task
Provide HV spines
Create Design Environment using PDK components from Foundry
Update PDK to follow current flow / structure (to transfer tapeout to design
team)
Create tapeout flow document so that design team can do tapeout
Update basic library for DIFF CD as per GFS requirement
pdk gen command
Add rule to check each chip pin has antenna diode
Build DRC deck
Build LVS deck
Create DK r2.0
Implement DK r1.0
VNDC new Req interview
Create LEF-able tech file
Add PTCH layer into the sample layout pfm_1180sl64kx32_v1a1

designkit_r3.4_calibredrcdeck_r1.1.0: Update DRC deck to ensure a 5um distan
Implement a pregen for TC0 ATZ/Mikron
Port Schematic databases for 40umc from 55UMC
Implement a Skill script to port 40umc to 28umc layout database
Fix bug of ESF1
Implement 40umc HV DRC deck
designkit_r3.4: Support running Calibre DRC/LVS deck in batch mode
Update "pdk run" command
"pdk install" spice model
ESF3-55UMC SST PDK - update DRC deck flow
Description

Install LV deck and implement HV + memory design rules
thepad
new
approach:
i.Using
Inputs:
cell,
a)
LV
Cadence
library
foundry
info),
b) HV Cadence
library
from width/spacing,
SST
routing
info
(i.e.
min
metal
if users
not enter
then
to bedosimilar
to the
topget
from
the tech
floorplan
of ESF3
ii. Output:
Supporting
pinaobjects
objects
defined
bycould
Cadence
Space-Base
Router,
Schematic:
simple (pin
schedule
(cell
symbol
be from
a fixed library,
should
be
a
generic
term
of
Cadence)
such as HV library)
Layout/schematic
are clean LVS
Implement
HV MOS pcells
ESF3-28UMC Full, the new approach
another
PDK
QA command:
Support
Do SVS check after converting
Use leftechgen.py.
3) Re-run
the tape-out
flow to after
generate
a newTo
GDS
formetal space violation,
Metal
dummy
space violation
IP merge:
avoid
pfm_1180sl64kx32_v1a1:
can SST make sure there is a 5um distance from the edge of IP merge ring? I
a) discussed
Copy /iplicense/users/bnguyen/proj/esf1have
this situation with our TDCAD team. It should not be a
180slt_eWave_bk/tapeout/03062015
to <your_wd>
problem to implement this spacing rule.
1) DRC:
implement
missing
rules
(array
rules etc.)
b) Edit run_pfm_1180sl64kx32_v1a1.csh
2)
Pregen:
add
c) at
Run
run_pfm_1180sl64kx32_v1a1.csh
to generate the after-pregen
Look
the
file:pregen step:
a)
Include
MTL3
dummy
filling
pfm_1180sl64kx32_v1a1.gds (located in
/iplicense/cad/technology/esf1b) Should not include NNII (Nselect), LV18 (Thickox), ZNVT (Native), REST
pfm_1180sl64kx32_v1a1/released/pfm_1180sl64kx32_v1a1_pregen_<date>
180slt/designkit_r3.4_calibredrcdeck_r1.1.0/esf1(Nwel_res),
NVT_HVT since they(check
are now
drawn
layers
.gds
180slt_sst_pregen_header.cal
layer
BULK_EXTENT_FILL)
3)
Verification:
4)
Run LVS between the new GDS in step #3 and the schematic DB
/iplicense/cad/technology/esf1a)
Use after-pregen pfm_1180sl64kx32_v1a1
asafter
a QAre-run
database,
remove
(included in your cds.lib
project
setup
180slt/designkit_r3.4_calibredrcdeck_r1.1.0/./esf1Implement
a
pregen
for
TC0
ATZ/Mikron
the
MTL3
dummy
fill,
then
stream
in
esf1-180slt DK r5.0.1) --> LVS should
clean using the standard LVS runset
180slt_sst_fill_cal_layer_ops.inc
(linesbe
354-357)
b)
Pregen
betorun
beforethe
DRC/LVS (similar ESF340UMC, consult
5)
Stream
in should
the GDS
replace
schpfm_355u256kx32_v1a0,schpfm_355u40kx36_v2a0
Khoe).
DRC/LVS should be done on after-pregen DB
$PDK_HOME/converted_lib/laypfm_1180sl64kx32_v1a1
Implement
a Skill
script
to size CONT, VIAx layers
and
drawsent
HVPB,
MOSN,
c)
Run LVL
ofwhole
this
v.s.
the
DBs
toofeWave
6)
Release
the
PDK
r5.0.1
again
to
Allen
(see
the
package
previous
MOSP, SBLK for 28umc layout database
release
/iplicense/cad/technology/esf1-180slt/release/20150308
Handle errors when no FG OPC
Implement HV DRC rule deck for 40umc
designkit_r3.4: Support running Calibre DRC/LVS deck in batch mode
Support extracting and comparing input and output GDS layer numbers
Support install spice model and extract device list from Mandan's excel file
Support running the latest DRC deck from pdkumc55eflash
Project.Code
PDK.Component
Status
Priority
Owner
ESF1-110LMC
NA
In.Planning
Normal
Nitya
Sapphire
SST.PDK
In.Planning
Critical
Nitya
Garnet
SST.PDK
In.Progress
Normal
Nitya
Garnet
Tape.Out
In.Progress
Normal
Nitya
Onyx
SST.PDK
In.Planning
Low
Nitya
PDK.Flow
PDK.Flow
In.Planning
Normal
Khoe
Pearl
DRC.Deck
In.Progress
Normal
Thanh
Emerald
DRC.Deck
In.Planning
Normal
Tri
Emerald
LVS.Deck
In.Planning
Normal
Tri
Emerald
Layout.Library
In.Planning
Normal
Tri
PDK.Flow
PDK.Flow
In.Planning
Low
Khoe
Quartz
SST.PDK
In.Planning
Low
Tri
PDK.Flow
Layout.Compiler
In.Planning
Low
Duong
PDK.Flow
Layout.Compiler
In.Progress
Normal
Duong
PDK.Flow
Layout.Compiler
In.Planning
Normal
Duong
PDK.Flow
Layout.Compiler
In.Progress
Normal
Duong
NA
SST.PDK
In.Progress
Critical
Khoe
PDK.Flow
NA
In.Planning
Normal
Khoe
PDK.Flow
Normal
Khoe
PDK.Flow
PDK.Flow
In.Progress
Normal
Khoe
PDK.Flow
Layout.Compiler
In.Planning
Normal
Khoe
PDK.Flow
PDK.QA
In.Planning
Normal
Thanh
PDK.Flow
Converted.Schematic
In.Progress
Critical
Tri
DTC.Compiler
Layout.Compiler
In.Progress
Normal
Khoe
NA
NA
Completed
Normal
Binh
Sapphire
LEF
In.Planning
Normal
Nitya
Pearl
SST.PDK
Completed
Normal
Thanh
Pearl
DRC.Deck
In.Planning
Normal
Thanh
Pearl
DRC.Deck
In.Planning
Normal
Thanh
Diamond
Pregen.Deck
Completed
Normal
Khoe
Quartz
Converted.Schematic
Completed
Normal
Tri
NA
Normal
Tri
NA
Layout.Compiler
Completed
Normal
Duong
Quartz
DRC.Deck
In.Progress
Normal
Duong
Pearl
DRC.Deck
Completed
Normal
Thanh
PDK.Flow
PDK.Flow
Completed
Normal
Khoe
PDK.Flow
PDK.Flow
Completed
Normal
Khoe
Jade
DRC.Deck
Completed
Normal
Khoe
Target
Actual
Comments
4/3/2015
4/5/2015
4/5/2015
4/5/2015
4/10/2015
4/10/2015
4/20/2015
4/3/2015
3/30/2015
Implement new DRC deck
4/15/2015
4/15/2015
4/3/2015
Built the interface
4/31/2015
4/3/2015
4/10/2015
3/31/2015
Khoe/Tri/Binh attended
4/30/2015
Consult Khoe if needed
3/20/2015
4/20/2015
3/20/2015
3/23/2015
3/28/2015
3/25/2015
3/30/2015
3/26/2015
3/20/2015
3/27/2015
3/23/2015
Task
pdk gen command
Build DRC deck
Build LVS deck
Create DK r2.0
Implement DK r0.1
Implement DK r1.0
Implement DK r1.7.2
Implement DK r2.0
Implement LVS running script
Review the code
Upgrade the tape-out flow to support QA checklist pass/fail report

Implement a pregen for TC0 ATZ/Mikron
Port Schematic databases for 28umc
Port Schematic databases for 40umc from 55UMC
Description
thepad
new
approach:
i.Using
Inputs:
cell,
a)
LV
Cadence
library
foundry
info),
b)
HV
Cadence
library
from
SST
routing
info
(i.e.
min
metal
width/spacing,
if users
not enter
then
to bedosimilar
to the
topget
from
the tech
floorplan
of ESF3
ii. Output:
Supporting
pinaobjects
objects
defined
bycould
Cadence
Space-Base
Router,
Schematic:
simple (pin
schedule
(cell
symbol
be from
a fixed library,
should
be
a
generic
term
of
Cadence)
such as HV library)
Layout/schematic
are clean LVS
Implement
HV MOS pcells
ESF3-28UMC Front-End, the new approach
ESF3-40UMC
devices
ESF3-28UMC Full,
Full, 4pullback
the new approach
1) Use old approach, simple directory structure, customization DRC/LVS/PEX
2) Cadence lib: add 4 HV pull back devices: cellName = modelName =
{n,p}hpb{a,}sy. Update CDF
3) Update DRC/LVS
1) Use new approach, support PEX
4) Update SPICE per Mandana's email
2) Based on DK r1.8
Write a script to run LVS flow
another
1) Add PTCH to display, techfile, and layermap of DK r5.0.1
Hold a meeting to review the code
2)
Add
to the
2array
tape-out
layer
mapring
files and check in
PDK
QAPTCH
command:
Support
drawing
anThanh/Khoe
of VIAs
in the
/iplicense/cad/technology/esf1-180slt/designkit_r3.4_calibredrcdeck_r1.1.0/
esf1-180slt_to_masklayers_ip_r3.4.2_opus61_2014-12-02.sout
esf1-180slt_to_masklayers_tc_r3.4.2_opus61_2014-10-16.sout
Do SVS check after converting
3) Re-run the tape-out flow to generate a new GDS for
a) Copy /iplicense/users/bnguyen/proj/esf1180slt_eWave_bk/tapeout/03062015 to <your_wd>
b) Edit run_pfm_1180sl64kx32_v1a1.csh
c) Run run_pfm_1180sl64kx32_v1a1.csh to generate the after-pregen
pfm_1180sl64kx32_v1a1.gds (located in
pfm_1180sl64kx32_v1a1/released/pfm_1180sl64kx32_v1a1_pregen_<date>
.gds
4) Run LVS between the new GDS in step #3 and the schematic DB
have discussed this situation with our TDCAD team. It should not be a
problem to implement this spacing rule.
1) DRC: implement missing rules (array rules etc.)
2)
Pregen:
Look
at theadd
file:pregen step:
a)
Include
MTL3 dummy filling
/iplicense/cad/technology/esf1b) Should not include NNII (Nselect), LV18 (Thickox), ZNVT (Native), REST
180slt/designkit_r3.4_calibredrcdeck_r1.1.0/esf1(Nwel_res),
NVT_HVT since they(check
are now
drawn
layers
layer
BULK_EXTENT_FILL)
3)
Verification:
/iplicense/cad/technology/esf1a)
Use after-pregen pfm_1180sl64kx32_v1a1 as a QA database, remove
180slt/designkit_r3.4_calibredrcdeck_r1.1.0/./esf1Implement
a pregen
TC0
ATZ/Mikron
the
MTL3 dummy
fill,for
then
stream
in 354-357)
(lines
b)
Pregen
should
be
run
before
DRC/LVS
(similar ESF340UMC, consult
schdtc_328u256kx16_v2a0,schdtc_328u256kx16_v1a0
Khoe). DRC/LVS should be done on after-pregen DB
schpfm_355u256kx32_v1a0,schpfm_355u40kx36_v2a0
c) Run LVL of this pfm_1180sl64kx32_v1a1 v.s. the DBs sent to eWave
Project.Code PDK.Component
Status
Priority
Owner
PDK.Flow
PDK.Flow
In.Planning
Normal
Khoe
Pearl
DRC.Deck
In.Planning
Normal
Khoe
Emerald
DRC.Deck
In.Planning
Normal
Tri
Emerald
LVS.Deck
In.Planning
Normal
Tri
Emerald
Layout.Library
In.Planning
Normal
Tri
PDK.Flow
PDK.Flow
In.Planning
Low
Khoe
Quartz
SST.PDK
In.Planning
Low
Tri
PDK.Flow
Layout.Compiler
In.Planning
Low
Duong
PDK.Flow
Layout.Compiler
In.Progress
Normal
Duong
PDK.Flow
Layout.Compiler
In.Planning
Normal
Duong
PDK.Flow
Layout.Compiler
In.Progress
Normal
Duong
NA
SST.PDK
Completed
Critical
Khoe
NA
SST.PDK
In.Progress
Critical
Khoe
Quartz
SST.PDK
Completed
Critical
Thanh
Quartz
SST.PDK
In.Planning
Normal
Khoe
Pearl
LVS.Deck
Completed
Critical
Khoe
PDK.Flow
NA
In.Planning
Normal
Khoe
PDK.Flow
Normal
Khoe
PDK.Flow
PDK.Flow
In.Progress
Normal
Khoe
PDK.Flow
PDK.Install.Hspice
Completed
Normal
Khoe
PDK.Flow
Layout.Compiler
In.Planning
Normal
Khoe
PDK.Flow
PDK.QA
In.Planning
Normal
Thanh
PDK.Flow
Converted.Schematic
In.Progress
Critical
Tri
PDK.Flow
Tape.Out
In.Planning
Normal
Khoe
DTC.Compiler Layout.Compiler
In.Progress
Normal
Khoe
Pearl
In.Progress
Normal
Thanh
SST.PDK
Pearl
DRC.Deck
In.Planning
Normal
Khoe
Pearl
DRC.Deck
In.Planning
Normal
Khoe
Diamond
Pregen.Deck
In.Planning
Normal
Khoe
NA
Converted.Schematic
Completed
Normal
Tri
Quartz
Converted.Schematic
In.Progress
Normal
Tri
Target
Actual
Comments
4/10/2015
4/5/2015
4/5/2015
4/5/2015
4/10/2015
4/10/2015
4/20/2015
3/27/2015
3/13/2015
3/17/2015
3/25/2015
3/16/2015
Implement new DRC deck

3/18/2015
3/31/2015
3/16/2015
Done the script already, need to update coversheet and release. /
4/5/2015
4/5/2015
3/31/2015
3/16/2015
3/31/2015
3/20/2015
4/10/2015
3/31/2015
3/20/2015
Built the interface
3/20/2015
3/18/2015
3/20/2015
ersheet and release. /iplicense/cad/bin/esf1180slt_rdeck_runner.pl
Task
Provide HV spines
Create Design Environment using PDK components from Foundry
Update basic library for DIFF CD as per GFS requirement
pdk gen command
Build DRC deck
Build LVS deck
Create DK r2.0
Implement DK r1.0
Implement DK r2.0
Install Foundry PDK
Review the code
Create LEF-able tech file
Description

Using the new approach:
a) LV Cadence library from foundry
To
place
many test
lines
together.
b) HV
Cadence
library
from
SST This seems to be similar to the top
floorplan
of pin
ESF3
array (pin
compiler
now.
Supporting
objects
objects
defined by Cadence Space-Base Router,
should be a generic term of Cadence)
ESF3-28UMC Full, the new approach
1) Use new approach, support PEX
2) Based on DK r1.8
1)
Add PTCH
display, databases:
techfile, and
layermap
of DK
r5.0.1 vs cellname
Compare
twoto
specified
SVS,
LVL, LVS,
cellname
ESF3-28. Create pdk_config.py, runset files.
2) Add PTCH to the 2 tape-out layer map files and check in
/iplicense/cad/technology/esf1-180slt/designkit_r3.4_calibredrcdeck_r1.1.0/
esf1-180slt_to_masklayers_ip_r3.4.2_opus61_2014-12-02.sout
Hold a meeting to review the code
esf1-180slt_to_masklayers_tc_r3.4.2_opus61_2014-10-16.sout
Support
drawing
an array
of VIAs in the ring
Support
unchecked
status.
Metal
dummy
space violation
after IP merge: To avoid metal space violation,
3)
Re-run
the
tape-out
flow
to
generate
a new
GDS
Review
and
fix
bugs
if
any
can SST make sure there is a 5um
distance
from
thefor
edge of IP merge ring? I
Generate
Test-patterns
for DRC
have
discussed
this
situation
with
our
TDCAD
team.
It
should
not be a
Upgrade
the/iplicense/users/bnguyen/proj/esf1tape-out flow to support QA checklist pass/fail
report
a)
Copy
1)
DRC: implement
missing
rules (array
problem
to implement
this spacing
rule.rules etc.)
180slt_eWave_bk/tapeout/03062015
to <your_wd>
Use
leftechgen.py.
2) Pregen:
add pregen step:
b)
Edit
a) at
Include
MTL3 dummy filling
Look
the file:
c)
generate ZNVT
the after-pregen
b) Run
Should
not include NNII (Nselect), LV18to(Thickox),
(Native), REST
/iplicense/cad/technology/esf1pfm_1180sl64kx32_v1a1.gds
(located
in
(Nwel_res),
NVT_HVT since they are now drawn layers
180slt/designkit_r3.4_calibredrcdeck_r1.1.0/esf1pfm_1180sl64kx32_v1a1/released/pfm_1180sl64kx32_v1a1_pregen_<date>
3)
Verification:
(check layer BULK_EXTENT_FILL)
.gds
a) Use after-pregen pfm_1180sl64kx32_v1a1 as a QA database, remove
/iplicense/cad/technology/esf14)
Run
LVSdummy
between
new
GDS in
the
MTL3
fill,the
then
stream
in step #3 and the schematic DB
180slt/designkit_r3.4_calibredrcdeck_r1.1.0/./esf1pfm_1180sl64kx32_v1a1
(included
in your cds.lib
re-run project
setup
b) Pregen should be run before(lines
DRC/LVS
(similarafter
ESF340UMC,
consult
354-357)
esf1-180slt
DK r5.0.1)
should
be clean using
Khoe). DRC/LVS
should-->
be LVS
done
on after-pregen
DB the standard LVS runset
5) c)
Stream
in the
GDSpfm_1180sl64kx32_v1a1
to replace the
Run LVL
of this
v.s. the DBs sent to eWave
$PDK_HOME/converted_lib/laypfm_1180sl64kx32_v1a1
6) Release the whole PDK r5.0.1 again to Allen (see the package of previous
release
/iplicense/cad/technology/esf1-180slt/release/20150308
Project.Code PDK.Component
Status
Priority
Owner
ESF1-110LMC NA
In.Planning
Normal
Nitya
Sapphire
SST.PDK
In.Planning
Critical
Nitya
Onyx
SST.PDK
In.Planning
Low
Nitya
PDK.Flow
PDK.Flow
In.Planning
Normal
Khoe
Pearl
DRC.Deck
In.Planning
Normal
Khoe
Emerald
DRC.Deck
In.Planning
Normal
Tri
Emerald
LVS.Deck
In.Planning
Normal
Tri
Emerald
Layout.Library
In.Planning
Normal
Tri
PDK.Flow
PDK.Flow
In.Planning
Low
Khoe
Quartz
SST.PDK
In.Planning
Low
Tri
PDK.Flow
Layout.Compiler
In.Planning
Low
Duong
PDK.Flow
Layout.Compiler
In.Planning
Normal
Duong
NA
SST.PDK
In.Planning
Critical
Khoe
Quartz
SST.PDK
In.Planning
Normal
Khoe
PDK.Flow
NA
In.Planning
Normal
Khoe
NA
Foundry.PDK
In.Planning
Normal
Khoe
PDK.Flow
PDK.Flow
In.Planning
Normal
Khoe
PDK.Flow
PDK.Install.Hspice
In.Planning
Normal
Khoe
PDK.Flow
Layout.Compiler
In.Planning
Normal
Khoe
PDK.Flow
PDK.QA
In.Planning
Normal
Thanh
PDK.Flow
Tape.Out
In.Planning
Normal
Khoe
Sapphire
LEF
In.Planning
Normal
Nitya
Pearl
SST.PDK
In.Planning
Normal
Thanh
Pearl
DRC.Deck
In.Planning
Normal
Khoe
Pearl
DRC.Deck
In.Planning
Normal
Khoe
Target
Actual
Comments
4/10/2015
3/20/2015
3/20/2015
3/20/2015
4/10/2015
4/10/2015
3/13/2015
3/31/2015
3/20/2015
3/13/2015
3/31/2015
3/16/2015
3/31/2015
4/10/2015
4/30/2015
3/20/2015
Consult Khoe if needed
Task
Review/update tape-out deliverables and flow
Description
Project.Code
NA
PDK.Component
NA
Status
In.Planning
Priority
Normal
Owner
Binh
Target
4/1/2015
Actual
Comments
Binh will work with TD/DE
Task
Provide Test Chip Pad ring layout
Provide SealRing layout
Debug and fix layout drawing problem
Install LV PEX deck
Update LVS deck to change RESM behavior
Introduce ESF3 layout compiler to TD team
Install a new version of probecell
Build DRC deck
Writing the user-guide and presentation document
Provide ESD layout
Build LVS deck
Build the layout example for each supported primitive device
Update DRC deck
Build unit-test and implement SPICE parser function
Implement scanner function for spice syntax
Create bond pad layout
Write the coversheet and designkit document
Debug and fix Schematic porting problem
Parse spice model files
Release the initial version
Update probepad to include MTL5
Tapeout KTM IPs
Help Vipin interview AE candidates
Convert WAT layout
Help Hieu to calculate DNWL area
Description
Project.Code
Coral
User can't create shapes in a layout view of a library with Coral
attached techfile
Coral
Support runset + customization file
Coral
RESM will only be used to mark MET4 resistor
Coral
Hold a meeting to introduce the ESF3 layout compiler
PDK.Flow
Import new layout GDS and change properties of probecell Coral
Implement HV + menory design rules
Diamond
Write ESF3 layout compiler user-guide document
PDK.Flow
Coral
Diamond
Diamond
Onyx
Build testcases and test parser function
PDK.Flow
PDK.Flow
Coral
Write a document to guide user
Diamond
Short circuit after porting 55GFS to pdkumc55eflash
PDK.Flow
Implement a parser function and return spice statements PDK.Flow
Wrap up data and send to Jack
Diamond
Sapphire
Garnet
NA
Pearl
Quartz
PDK.Component
Status
Layout.Library
Completed
Layout.Library
Completed
Device.Library
Completed
PEX.Deck
Completed
LVS.Deck
Completed
NA
Completed
Device.Library
Completed
DRC.Deck
Completed
Layout.Compiler
Completed
Layout.Library
Completed
LVS.Deck
Completed
Device.Library
Completed
DRC.Deck
Completed
PDK.Install.Hspice
Completed
PDK.Flow
Completed
Layout.Library
Completed
Cover.Sheet
Completed
Converted.Schematic.LCompleted
PDK.Install.Hspice
Completed
NA
Completed
Device.Library
Completed
Tape.Out
Completed
NA
Completed
Converted.Layout.Lib Completed
NA
Completed
Priority
Normal
Normal
Critical
Critical
Critical
Normal
Critical
Critical
Normal
Normal
Critical
Normal
Normal
Normal
Normal
Normal
Normal
Critical
Normal
Normal
Normal
Critical
Normal
Normal
Normal
Owner
Nitya
Nitya
Khoe
Khoe
Khoe
Duong
Khoe
Tri
Duong
Nitya
Tri
Tri
Nitya
Thanh
Thanh
Nitya
Tri
Tri
Thanh
Tri
Nitya
Nitya
Binh
Binh
Binh
Target
1/9/2015
1/15/2015
1/12/2015
1/9/2015
1/7/2015
1/7/2015
1/14/2015
1/7/2015
1/13/2015
1/14/2015
Actual
1/15/2015
1/15/2015
1/15/2015
1/15/2015
1/14/2015
1/12/2015
1/12/2015
1/11/2015
1/9/2015
1/7/2015
1/5/2015
1/7/2015
1/7/2015
1/14/2015
1/7/2015
1/15/2015
1/14/2015
1/15/2015
1/14/2015
1/14/2015
1/14/2015
1/14/2015
1/16/2015
1/16/2015
1/8/2015
Comments
Task
Build the layout example for each supported primitive device
Build LVS deck
Debug pcell problem in SHDC site
Update display.drf, techfile.tf, layermap files to add SST layers
Port schpfm_355gf512kx32_v1a0, schtc_355gf512kx32_v1a0
Write the coversheet and designkit document
Implement HV rules
Build LVS deck
Implement HV DRC deck
Provide the list of parameters HV Pcells
Description
Project.Code
Diamond
Diamond
Amber
Emerald
Quartz
Emerald
Diamond
Diamond
Emerald
Emerald
PDK.Component
Status
Device.Library
Completed
LVS.Deck
Completed
Device.Library
Completed
Tech.Files
Completed
Converted.Schematic.LCompleted
Device.Library
In.Planning
Cover.Sheet
In.Planning
DRC.Deck
In.Progress
LVS.Deck
In.Progress
DRC.Deck
In.Planning
Priority
Normal
Critical
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Normal
Owner
Tri
Tri
Tri
Tri
Tri
Tri
Tri
Tri
Tri
Tri
Tri
Target
1/7/2015
1/16/2015
1/13/2015
1/9/2015
1/16/2015
1/16/2015
Actual
1/7/2015
1/5/2015
12/25/2014
12/18/2014
12/11/2014
Comments
Customer
Tech
PM
Code
Prio
PDK
340 ND
GFS
SLT
UMC
355 YH
Garnet
1130 LC
1180 LC
340 ND
355 WY
Onyx
Pearl
Quartz
355PDK WY
328
Jade
i. Installed the New early
LF11A-PDK Release
(Version 0.0.15) Tri Le
LFR, LFA
3110 XL
ATZ
TI
390 JS
365 JH
Diamond
Zircon
Mikron
NationZ
SMIC
390 JS
KL
Emerald
Amber
Creating PDK [Tri Le
12/19]
Creating PDK [Tri Le
12/12]
XMC
355 XL
Coral
Sapphire
Opal
Ruby
Toshiba
Lapis
Renesas
365 YH
2130 LC
3110 YH
PDK QA
Sent the report for
verifying the
correctness of all
listed PDKs.
Wrote/Updated the
development
document
Generic
Flow
Misc
Color code
Critical
Normal
Low priority
In-progress
Done
MISCELLANEOUS
HR training for VN team (Khoe, Tri, Thanh, Duong)
TD-CAD Methodology
PDK flow: pregen first, then DRC [Khoe]
QA and Release flow [Khoe/Binh]
Device construction should be fixed, foundry interface should be done by pregen
Foundry PDK utilization
Calibre LVS setup: path to CDL file (Look at TI65)
PERC high voltage metal rule (Jinho's request)
Support SDL
CVS instruction to import a project

CVS write permission
Data organization
WAT generators (sch/lay)
Mini array generators
when hspiceD netlisting, the libraies are included in the output netlist automatically
required TechDevices_primitives in DRC/LVS development
EM flow
micro pad placement
Ask foundry to adop LVSS, STRP
Scripts
Tech files
Device lib
Updated
symbol library
to add new
cell
cell2t25_leti[
Nitya]
i. Reviewed the purpose of

SUBSTRATE layer and
answered Jennys concerned
[Tri 12/04]
ii. Fixed multiple
manufacturing GRIDs issues
[Tri 12/04]
iii. Generating collateral
control files for IPGEN [Thanh
12/12]
i. Generating LEFable techfile

and collateral control files for
IPGEN. - Thanh
Reviewed
Discrepancy
between
umc55eflash/
N_12_LPNVT
and design
rule of
NT.W1 [Tri
11/28]
Gate lib
Creating collateral control

files for IPGEN - Thanh
[12/12]
Create new PDK based on new approach {LV library from foundry
SST} [Nitya]
Sche Lib
Lay Lib
SPICE lib
Pregen deck
Update basic
library for
Update basic library for DIFF
DIFF CD as
CD as per GFS
per GFS
requirement[Nitya]
requirement[
Nitya]
i. Released version 1.6 [Tri/Binh]

ii. Supported auto-loading DRC/LVS/PEX runset
Reviewing and generating

WAT memory array [Khoe
12/12]
To provide example IP
merging ring[Nitya]
Re-sent the clean DRC
vncap layout to Pixy [Khoe
11/28]
Create new decks

based on new
approach {LV
ased on new approach {LV library from foundry and HV library from Update spice
layers from
SST} [Nitya]
library[Nitya]
foundry and HV
layers from SST}
[Nitya]
Delete Notes a SKILL

GUI tool to delete notes in
schematic: Khoe
Released the initial
version
Support delete Note
Shapes, Note Texts
Support pattern
matching.
1) ESF3 layout compiler:

Duong/Khoe 12/05
Checked the new
version of the code to
support Termwl and
MCELL generation.
Developing functions to
generate strap cells.
Adding the description
and data validation for
the input Excel file: Khoe
2) Basic MOS layout
Generator: Tri Le 11/28
Improved the template
and fixed setup errors.
Review IP merging ring and

LEF requirement document
from Pixy[Nitya]
DRC deck
Tri/Binh]
ng DRC/LVS/PEX runset
ii. Implementing a pregen to
automatically fix the
following DRC violations:
Thanh/Khoe [11/28]
LVS deck
PEX deck
Csdoc
Created DRC deck for

TC2(without waivers) [Nitya
11/20]
Creating new decks based
on new approach {LV layers
from foundry and HV layers
from SST} [Nitya]
Release
updated
coversheet
for TC2
Creating a prototype for

Flash LVS integration
[Khoe/Binh 11/24]
Dkdoc
Tapeout
Converted Converted
layout
schematic
Foundry
PDK
Misc
Tapeout
Updated
Scaleochip[Ni
tya - 11/14 Done]
Tapeout
Updated
Scaleochip IPs
[Nitya 12/05]
Provide
DRC/LVS
environment
information[Ni
tya]
Tapeout
Testchip after
addition of CG
ring to the
array[Nitya]
Provide Ip
Merging
procedure to
Xian to be
sent to
XMC[Nitya]
Release
updated DK
document for
TC2[Nitya]
Re-Tapeout
TC1 WAT
databases[Nit
ya 11/07]
AI
Customer
Tech
PM
Code
Prio
340 ND
355 YH
Garnet
GFS
1130 LC
Onyx
SLT
1180 LC
Pearl
340 ND
355 WY
UMC
LFR, LFA
ATZ
TI
Mikron
NationZ
SMIC
355PDK WY
328
3110 XL
390 XL
365 JH
390 JS
KL
Quartz
Jade
Amber
Diamond
Zircon
Emerald
XMC
355 XL
Coral
Sapphire
Opal
Ruby
Toshiba
Lapis
Renesas
365 YH
2130 LC
3110 YH
Generic Flow
Color code
Critical
Normal
Low priority
In-progress
Done
MISCELLANEOUS
TD-CAD Methodology
Support SDL

Data organization
/iplicense/users/bnguyen/pdk_dev/tdcad/scripts/perl/replaceLayerInTechFile.pl --- update display file a
EM flow
micro pad placement
PDK
Verified
netlisting/simulation/DRC
[Thanh/Duong/Khoe 11/06]
Create DK r.16: added 3
devices 2.5V overide to 3.3V
[Tri 11/06]
Created PDK r1.1 [Tri/Binh
11/07]
Completed phase 1
including 9 functions
[Thanh/Duong 10/31]
Applying PDK QA for 10
technologies [Thanh 11/31]
Scripts
Updated to work for both

Cadence 5.1/6.1 [Binh 11/06]
Tech files
e.pl --- update display file also
Device lib
Update to include 3.3V

underdrive devices[Nitya]
Evaluate new approach{LV
library from foundry and HV
library from SST}[Nitya]
Gate lib
Sche Lib
Lay Lib
Update basic library for DIFF CD as per GFS

requirement[Nitya]
Create example IP merging ring and seal ring[Nitya - 10/31]
Released 4 arrays for pfm_355x128kx39_v1 [Khoe 11/06]
Released the initial version of pdk compile to compile

Excel-based Module Specification (XMS) files to
generate layout/schematic databases [Khoe 10/31]
Developing WL terminal cell compiler [Duong 11/24]
SPICE lib
Update basic library for DIFF

CD as per GFS
requirement[Nitya]
Pregen deck
DRC deck
Added layers translation from

foundry to SST [Khoe 11/06]
Reviewed Cornells feedbacks

about XMCs DRC/LVS deck
[Khoe 11/06]
Update Pregen deck to create
Create DRC deck for
new layers-TSB request
TC2(without waivers)[Nitya]
Nitya[11/05]
Creating a prototype for Flash

LVS integration [Khoe/Binh
11/15]
LVS deck
PEX deck
Csdoc
Release updated coversheet

for TC2
Dkdoc
Release updated DK document

for TC2[Nitya]
Tapeout
Converted layout
Converted schematic
Tapeout Updated
Scaleochip[Nitya - 11/14]
Converted a DB for Thuan

[Tri/Binh 11/06]
Tapeout TC1 DTC and WAT

databases[Nitya 11/05]
Send DTC and WAT preliminary
databases to TSB[Nitya 10/24]
Released Schematic Map

and Wire tool ver.2.01 [Tri
11/06]
Foundry PDK
Misc
DRC Violation waiver

discussion[Nitya]
Send preliminary documents to
DE Team[Nitya - 11/04]
Create new REVID

scheme[Nitya-11/05]
AI
Customer
Tech
PM
Code
Prio
340 ND
355 YH
Garnet
GFS
1130 LC
Onyx
SLT
1180 LC
Pearl
340 ND
355 WY
UMC
355PDK WY
328
LFR, LFA
ATZ
TI
Mikron
NationZ
SMIC
3110 XL
390 XL
365 JH
390 JS
KL
Quartz
Jade
Amber
Diamond
Zircon
Emerald
XMC
355 XL
Coral
Sapphire
Opal
Ruby
Toshiba
365 YH
2130 LC
3110 YH
Lapis
Renesas
Generic Flow
Color code
Critical
Normal
Low priority
In-progress
Done
MISCELLANEOUS
TD-CAD Methodology
Support SDL

Data organization
EM flow
micro pad placement
PDK
Installed LF11A PDK rev

0_0_12 [Tri 10/24]
Working on PDK QA
[Thanh/Duong 10/23]
Scripts
Tech files
Device lib
Gate lib
Sche Lib
Create new schematic library

based on new DIFF CD[Nitya10/09]
Corrected hspiceD netlisting

for ndio*, *mos devices:
Missing l/w parameters [Khoe
10/24]
Debugged the LVS problem

corresponding to Cornells
feedback [Khoe 10/24]
Lay Lib
SPICE lib
Pregen deck
Create new layout library

Create example IP merging

ring and seal ring[Nitya 10/31]
Generating the array for

pfm_355x128kx39_v1 [Khoe
10/31]
Worked with Yueh-Hsin to

release 6 arrays for TC1 [Tri
10/24]
Update Pregen deck to create

new layers-TSB request
Nitya[10/22]
DRC deck
LVS deck
Update LVS deck based on new

version from GFS[Nitya- 10/10]

LVS integration [Binh 10/31]
Remove TAPH related rules

[Khoe 10/24]
Update DRC deck based on

Update LVS Deck based on
latest release from TSB[Nitya - new pregen - TSB
10/22]
request[Nitya - 10/22]

LVS integration [Khoe/Binh
11/15]
PEX deck
Csdoc
Dkdoc
Tapeout
Updated the coversheet

document to add Element
Name (LVS) for each primitive
device [Khoe 10/17]
Send DTC and WAT preliminary
databases to TSB[Nitya 10/24]
Send preliminary HV WAT gds
to TSB{Nitya - 10/10]
Converted layout
Convert HV WAT spines from

ESF3-65TI[Nitya - 10/20]
Converted schematic
Foundry PDK
Misc
Communicate with GFS on how
to check missing DRC rule and
discuss about gaps in LVS
deck[Nitya - 10/20]
Send LVS deck discrepancies
summary and gds to GFS
[Nitya - 10/17]
Create new ESD VPP pad
package to send to
SilTerra[Nitya - 10/20]
DRC Violation waiver

discussion[Nitya]
Create WAT 22 pad structure
and release to layout
team[Nitya10/13]
Create new REVID

scheme[Nitya]
AI
Customer
Tech
PM
Code
Prio
340 ND
355 YH
Garnet
GFS
1130 LC
Onyx
SLT
1180 LC
340 ND
Pearl
Quartz
355 WY
UMC
LFR, LFA
ATZ
TI
Mikron
NationZ
SMIC
XMC
355PDK WY
328
3110 XL
390 XL
365 JH
390 JS
KL
355 XL
Jade
Amber
Diamond
Zircon
Emerald
Coral
Sapphire
Opal
Ruby
Toshiba
Lapis
Renesas
365 YH
2130 LC
3110 YH
Generic Flow
Color code
Critical
Normal
Low priority
In-progress
Done
MISCELLANEOUS
Training for Duong (SKILL), Thanh (Python)
TD-CAD Methodology
Support SDL

Data organization
EM flow
micro pad placement
PDK
Sent DRC/LVS integration

approach to XMC [Binh 10/10]
Working on PDK QA
[Thanh/Duong 10/23]
Scripts
Tech files
Device lib
Gate lib
Sche Lib
Create new schematic library

Added memory cells [Binh

10/03]
Converted Tech_Primitives test

case [Binh 10/09]
Schematic porting: added

more WARNING messages
to output [Tri 10/10]
Lay Lib
SPICE lib
Pregen deck
Update sincgle cell layout for

DIFF CD change[Nitya - 09/25]
Create new layout library
Update IP Merging ring
example[Nitya - 10/07] Done
Sent pregen formulas to MT
[Khoe 10/03]
Generating the array for

pfm_355x128kx39_v1 [Khoe
10/15]
Working with Yueh-Hsin to
Install spice library
generate 6 arrays for TC1 [Tri
Nitya[10/02]
10/15]
Create Pregen deck

Nitya[10/07]
DRC deck
LVS deck

new version and add WL25
rule[Nitya-09/25]

version from GFS[Nitya- 10/10]
Released test patterns and

report to Henry [Duong/Thanh
10/03]
Added a rule to flag ODMK not

inside TG [Binh 10/09]
Create Complete DRC

deck[Nitya]
Create LVS Deck[Nitya]
PEX deck
Csdoc
Dkdoc
Tapeout
Re-Tapeout Bias and PFM
databases for 32kx72 [Nitya 09/29]
Generated 7 GDSs (TC2) and 2

GDSs(TC3) [Khoe 10/03]
Converted TSB layers to SST

layers [Binh 10/10]
Converted layout
Converted schematic
Fixed model names of

resistors/probecell [Tri 10/03]
Nitya - 10/01
Built a script to size gates
[Binh 10/03]
Built a script to size gates in

SPICE netlist for simulation
[Binh 10/10]
Foundry PDK
Misc
Send reports and testcases to
GFS to support analysis of
DRC/LVS deck issue[Nitya 10/09]
Send DRC violation waiver list

to TSB[Nitya -Done]
AI
Customer
Tech
PM
Code
Prio
340 ND
355 YH
Garnet
GFS
1130 LC
Onyx
SLT
1180 LC
Pearl
340 ND
355 WY
355PDK WY
UMC
LFR, LFA
ATZ
TI
Mikron
NationZ
Quartz
Jade
328
3110 XL
390 XL
365 JH
390 JS
Amber
Diamond
Zircon
Emerald
KL
SMIC
XMC
355 XL
Coral
Toshiba
365 YH
2130 LC
3110 YH
Lapis
Renesas
Sapphire
Opal
Ruby
Generic Flow
Color code
Critical
Normal
Low priority
In-progress
Done
MISCELLANEOUS
Training VNDC TD-CAD new hire
TD-CAD Methodology
Support SDL

Data organization
EM flow
micro pad placement
PDK
Shipped DK r1.0 to XMC [Khoe

08/25]
Scripts
Tech files
Completed 1st version of

project plan and detail
design document for PDKQA [Khoe 09/25]
Reviewing Python Logging
[Khoe]
Device lib
Gate lib
Fixed open errors [Binh 10/03]
Fixed Pixys feedbacks on

analogLib, cell2t25s EP
parameter [08/28]
Sche Lib
Nitya - TBD
Nitya -Done [09/21]
Lay Lib
SPICE lib
Pregen deck
Update example IP merging

ring to support LEF
generation[Nitya - 09/24]
Update single cell layout for
DIFF CD change[Nitya - 09/25]
Generating mini array [Khoe/Tri

08/25]
To remove X* layers in the
memory gen [Tri 10/03]
Upgrade to DK r1.1: remove

pregen, [Tri 10/03]
Generate mini array [Tri 10/03]
To demo the new scripts to DE [Nitya - TBD]

Completed project plan for rule deck auto-gen p
Building HV LVS template [Khoe 10/03]
Reviewed LVS connectivities [Khoe 09/11]
DRC deck
LVS deck
PEX deck

new version and add WL25
rule[Nitya-09/25]

new verison form GFS[nitya 09/18]

verison form GFS[nitya - 10/03]
Completed updating DRC deck

for Resistor value [Nitya
-09/19]
Building DRC templates to
verify the new Calibre DRC
deck [Thanh/Duong 09/26]
Corrected and verified
PSUB/HPWL connection
[Khoe/Binh 09/11]
Added PEX for HV [Binh 10/03]
Reviewed PSUB/HPWL
connection
Create PEX deck [Khoe 10/03]
Create Complete DRC

deck[Nitya]
Create LVS Deck[Nitya - TBD]
pts to DE [Nitya - TBD]

an for rule deck auto-gen plan [Khoe 09/18]
late [Khoe 10/03]
tivities [Khoe 09/11]
Csdoc
Dkdoc
Tapeout
Tapeout Bias and PFM
databases for 32kx72 [Nitya 09/24]
Create IP Tapeout Layer map
file[Nitya - 08/27]
Add cell capacitance structure

to WAT for September Tapeout
[Nitya]
Taped-out block_a (WAT) and

dtc4m_340u_v3a2 (TC) and
extracted modified back-end
layers [Khoe/Binh 09/11]
Create and release doc for

Rev1.0 [Nitya - 09/21]
Tapeout TC0[Nitya - 09/05]
Demo to DE[Nitya - TBD]
Converted layout
Converted schematic
Foundry PDK
Install GFS PDK [Tri 08/29]
Fixed poly resistor and probe

cell model names [Tri 09/25]
Fixed converted schematic as
Lu's feedback [Tri 09/11]
Ported 3 DBs from old techs
[Tri 09/04]
Nitya - 09/26
Nitya -Done [09/24]
Released v1.0, v2.0 of

schematic conversion [Tri
09/25]
Fixing bugs of rounding up of
param values [Tri 10/03]
Misc
Provide VPP pad package[Nitya

- 08/29]
Nhan: 28nm PDK Likely

from UMC first. I am going
to see them in 2 weeks. If
things move smoothly, I can
get access to their PDK
sometimes in August.
Add tsmcN90emf to the

system
AI
Provide layout team with wat

frame of correct size[Nitya 08/26]
Provide layout team with script
to change grid to 0.005[Nitya08/26]
Customer
Tech
PM
Code
340 ND
355 YH
Garnet
GFS
1130 LC
Onyx
SLT
1180 LC
Pearl
340 ND
355 WY
355PDK WY
UMC
LFR, LFA
Quartz
Jade
328
3110 XL
Amber
ATZ
TI
390 XL
365 JH
Diamond
Zircon
Mikron
NationZ
SMIC
390 JS
KL
Emerald
Prio
XMC
355 XL
Coral
365 YH
Sapphire
Toshiba
Lapis
Renesas
2130 LC
3110 YH
Opal
Ruby
Generic Flow
Color code
Critical
Normal
Low priority
In-progress
Done
MISCELLANEOUS
Interviewed candidates for TD-CAD
Training VNDC TD-CAD new hire
TD-CAD Methodology
Support SDL

Data organization
EM flow
micro pad placement
PDK
Released PDK r1.0 [Tri Le

08/14]
Scripts
Tech files
Device lib
Upgraded callback
invocation [Tri Le
08/14]
Gate lib
Cleaning up the
PDK r1.0 to ship
to XMC [Khoe
08/08]
Deliver front end DK r1.0 to
XMC [Khoe 08/14]
uld be done by pregen
Nitya - TBD
Nitya - TBD
ceLayerInTechFile.pl --- update display file also

utput netlist automatically
Sche Lib
Lay Lib
Released clean LVS array

[Tri 08/21]
Update and release IP

Merging Ring according
to Tiempo request [Nitya
- 08/11]
Update and release IP
Merging Ring DRC deck
to accommodate above
update{Nitya - 08/11]
SPICE lib
Pregen deck
Fixed
netlisting
issue of *mos
[Khoe 08/14]
Generating mini array
Verified
[Khoe/Tri 08/25]
verilog
netlisting for
diode [Khoe
08/14]
Nitya - TBD
Initial version
ready and used in
DRC verification
[ Nitya 08/15]
Demo to DE[Nitya - T
DRC deck
Install new DRC deck from

GFS [ Nitya - 08/29]
LVS deck
PEX deck
Csdoc
Install new LVS deck

from GFS [ Nitya
08/29]
Update
procedure for
unix
system[Nitya 08/04]
Done PEX for LV
[Khoe/Binh 07/23]
Added PEX for HV
[Binh 08/29]
Installed new LVS

deck [Tri Le 08/21]
Fixed CDL netlisting
due to Cadence
version [Khoe 08/21]
Install new DRC deck from

foundry [Khoe Tran 08/21]
Create PEX deck

[Khoe 08/15]
Create DRC deck that invokes

pregen deck and modify
Create LVS
foundry deck(when
Deck[Nitya - TBD]
necessary) - Released to
Design Team [Nitya 08/15]
Create and
release doc for
Rev1.0 [Nitya 08/15]
Dkdoc
Tapeout
Converted
layout
Converted
schematic
Add cell capacitance structure

to WAT for September Tapeout
[Nitya]
Ported 2 TC
layout DBs
[Khoe Tran
08/14]
Ported 2 TC
schematic DBs
[Tri Le 08/14]
Tapeout WAT spines for OPC

experiment[DONE - Nitya 07/09]
Tapeout DTC and WAT TOII
[Nitya -08/04]
Nitya - TBD
Nitya - TBD
Foundry PDK
Misc
Install GFS PDK [Tri

08/29]
Resolve netlisting issue reported by Henry N.
[Nitya - Done 08/20]
Look into issue reported by Pixy regarding
resistor netlist[Nitya - Done 08/20]
Nhan: 28nm PDK Likely from UMC first. I

am going to see them in 2 weeks. If things
move smoothly, I can get access to their
PDK sometimes in August.
a. Fab is not ready

b. Logic development begins in Q4 2014 may
involve us
ESF3-90 Mikron (Russia) agreement signed

this week 06/26
a. Logic development is on-going
b. Kick-off ~ May 2014
c. TC0 T/O ~ June
d. TC1 T/O Oct
Add tsmcN90emf to the system
AI
Pregen and send miniarray to Sapphire for

OPC[Nitya - 08/06]
Sapphire DTC layout time evaluation[Nitya 08/13]
Customer
Tech
PM
Code
Prio
PDK
Scripts
340 ND
GFS
355 YH
1130 LC
Garnet
Onyx
SLT
1180 LC
Pearl
340 ND
355 WY
355PDK WY
UMC
LFR, LFA
Quartz
Jade
328
3110 XL
Amber
ATZ
TI
390 XL
365 JH
Diamond
Zircon
Mikron
NationZ
SMIC
390 JS
KL
Emerald
XMC
355 XL
Toshiba
Lapis
Renesas
365 YH
2130 LC
3110 YH
Coral
Sapphire
Opal
Ruby
Cleaning up the
PDK r1.0 to ship
to XMC [Khoe
08/08]
Generic Flow
Color code
Critical
Normal
Low priority
In-progress
Done
MISCELLANEOUS
Interviewed candidates for TD-CAD
TD-CAD Methodology
Support SDL

Data organization
EM flow
micro pad placement
Tech files
Device lib
Gate lib
Sche Lib
Lay Lib
Done verifying DRC,

working on LVS for the
mini array [Tri 08/07]
Add fgcelro [Binh
08/08]
Update IP Merging Ring

according to Tiempo
request [Nitya]

[Tri 08/08]
update display file also
SPICE lib
Pregen deck
DRC deck
LVS deck
Rev up spicea3 [Binh

08/08]
Debugging MC simulation
with Mandana [Binh 08/07]
Installed new SPICE lib [Tri
08/07]
Create Pregen
Create DRC Deck[Nitya
Deck[Nitya 08/08] 08/08]
Create LVS
Deck[Nitya 08/22]
Demo new
scripts of
pregen/DRC/LVS/
Tapeout to DE
team [Nitya
TBD]
pdk gen: create HV

LVS template
[Khoe 08/08]
PEX deck
Csdoc
Dkdoc
Tapeout
Update
procedure for
unix
system[Nitya]
Done PEX for LV
[Khoe/Binh 07/23]
Added PEX for HV
[Binh 08/08]
Create PEX deck

[Khoe 08/15]

experiment[DONE - Nitya 07/09]
Tapeout[Nitya -08/01]
Converted
layout
Converted
schematic
Foundry PDK
08/15]
Misc
Added foundry documents to DK [binh

08/07]
a. Fab is not ready

involve us

this week 06/26
c. TC0 T/O ~ June
d. TC1 T/O Oct
Sapphire DTC layout time evaluation[Nitya]
AI
Customer
Tech
PM
Code
340 ND
GFS
355 YH
1130 LC
Garnet
Onyx
SLT
1180 LC
Pearl
340 ND
355 WY
355PDK WY
UMC
LFR, LFA
Quartz
Jade
328
3110 XL
Amber
ATZ
TI
390 XL
365 JH
Diamond
Zircon
Mikron
390 JS
Emerald
Prio
PDK
Scripts
NationZ
SMIC
KL
XMC
355 XL
Coral
Sapphire
Opal
Ruby
Cleaning up the
PDK r1.0 to ship
to XMC [Khoe
08/08]
Toshiba
Lapis
Renesas
365 YH
2130 LC
3110 YH
Generic Flow
Color code
Critical
Normal
Low priority
In-progress
Done
MISCELLANEOUS
Hired 1 VN TD-CAD
TD-CAD Methodology
Support SDL

Data organization
EM flow
micro pad placement
Tech files
Device lib
Gate lib
Sche Lib
Lay Lib
Updated the array

generators [Tri 07/10]
Verifying DRC/LVS for
generated mini array [Tri
8/8]
Supported via
object [Khoe
07/17]
Add fgcelro [Binh

08/08]

according to Tiempo
request [Nitya]
Sent layermap
and GDS to
Jack [Tri 07/10]
Ported layout DB from

Jade [Tri 07/10]

[Tri 08/08]
SPICE lib
Pregen deck
DRC deck
Install updated
spice library[Nitya07/15]
Update DRC deck[Nitya 07/11]
Rev up spicea3
[Binh 08/08]
Updated per Jenny's

feedback
Correct the rule code
DNW.R.01 [Khoe 07/30]
Debugging MC
simulation with
Mandana [Binh
TBD]
Installed new DRC deck [Tri

07/24]
LVS deck
Review to check for

issue complained by
DE[Nitya - 07/14] No issue with LVS
deck
Corrected
configuration per
Cornell's feedback
[Tri 07/30]
Release DK 1.0, use 2 steps of Calibre [Khoe 07/17]
Create Pregen
Create DRC Deck[Nitya
Deck[Nitya 08/08] 08/08]
Create LVS
Deck[Nitya 08/22]
Demo new
scripts of
pdk gen: completed HV
pregen/DRC/LVS/
DRC template [Khoe
Tapeout to DE
07/30]
team [Nitya
TBD]
pdk gen: create HV

LVS template
[Khoe 08/08]
PEX deck
Csdoc
Dkdoc
Tapeout
Tapeout Linear Tech IP[Nitya 07/22]

Re-run DRC on earlier tapedout
Ips using the latest DRC deck
from GFS and sent reeports and
revision document to
GFS[Nitya-07/22]
Update
procedure for
unix
system[Nitya]
Update DK
Document[Nity
a - 07/11]
Released the tape-out data of
dtc4m_340u_v4a1,
dtc4m_340u_v5a1, and
dtc4m_340u_v6a1, verified with
LVL [Khoe]
Done PEX for LV

[Khoe/Binh 07/23]
Added PEX for HV
[Binh 08/08]
Added HSPICE
flow [Tri 07/24]

Release dkdoc experiment[DONE - Nitya [Khoe/Binh
07/09]
07/30]
Tapeout[Nitya -08/01]
Create PEX deck

[Khoe 08/15]
Created and
released initial
version[Nitya 07/09]
pdk run: support LVL

comparision for tapeout
[Khoe 07/30]
Converted
layout
Converted
schematic
Foundry PDK

08/15]
Removed
redudant user
param simM
[Khoe/Binh
078/01]
Installed hot fix [Tri

07/24]
Review and request

missing
information[Nitya]
Implemented
"Rename
Reference
Library" [Khoe
07/24]
Misc
Provide vpp pad packgae to SilTerra / Nordic

Semi[Nitya-07/09]
Reviewed and fixed issues with design
environment[Nitya-07/30]

a. Fab is not ready

involve us

this week 06/26
c. TC0 T/O ~ June
d. TC1 T/O Oct
AI
Sapphire DTC layout time evaluation[Nitya]
Fixed bug of SST Tool on Cadence IC5.1 [Khoe

07/30]
Customer
Tech
PM
Prio
Scripts
340 ND
355 YH
GFS
1130 LC
SLT
1180 LC
340 ND
355 WY
355PDK
UMC
LFR, LFA
AST
TI
Mikron
NationZ
SMIC
328
3110 XL
390 XL
365 JH
390
KL
Tech files
XMC
Saphire
365
Generic Flow
Completed
"pdk map"
and update
"pdk add",
"pdk commit"
[Khoe 07/03]
Misc
Color code
Critical
Normal
Low priority
In-progress
Done
TD-CAD Methodology
Support LEF generation
markNet
Support SDL

Data organization

EM flow
micro pad placement
Device lib
Gate lib
Sche Lib
Lay Lib
SPICE lib
Update spice
library based on a9
version from
Mandana[Nitya 06/13]
Create mini array

generator for ESF1180STL [Tri 06/27]

according to Tiempo
request [Nitya]
done by pregen
Created a
script to port
55GFS
schematic
DBs to
55XMC [Khoe
Install and verify

a1 version of spice
library from
Mandana[Nitya
-07/02]
TechFile.pl --- update display file also

st automatically
Pregen deck
DRC deck
LVS deck
PEX deck
Involved in
discussion between
DE Team and GFS
regarding LVS
verification of
DNWL(extra terminal
for DNWL) - [Nitya]
Update DRC deck[Nitya 07/11]
Add PEX, after
UMC40 tape-out
[Binh]
Create pregen
deck [Tri TDB]
Created pregen
decks for TC0 WAT
Create LVS deck that Create PEX deck, use
and DTC[Nitya Create DRC deck that invokes
invokes pre-gen
the share pre-gen
06/30]
pre-gen [Khoe 07/07]
[Khoe 07/14]
[Nitya - TBD]
Created pregen
deck [Khoe 07/02]
Batch mode
script to run
Pregen
Review with
Binh &
Henry[Nitya
06/19]
Demo to
DE[Nitya 07/11]
Batch mode script

Batch mode script to run to run LVS
DRC
Review with Binh &
Review with Binh &
Henry[Nitya
Henry[Nitya 06/19]
06/19]
Demo to DE[Nitya - 07/11] Demo to DE[Nitya 07/11]
Csdoc
Dkdoc
Tapeout
Sent requested physical

verification reports to
GFS[Nitya -06/29]
Update DK
Document[Nity
a - 07/11]
Taped out TC1 [Khoe/Binh
06/30]
Create streamout layer

map for TC0 [Tri TDB]
Converted Converted
layout
schematic
Binh 07/14
Tapeout TC0 WAT and

DTC Databases[Nitya 06/30]
Batch mode script to

prepare and verify TO
DB
Review with Binh &
Henry[Nitya 06/19]
Demo to DE[Nitya 07/11]
Foundry PDK
Misc

06/27]
Provide vpp pad packgae to SilTerra / Nordic

Semi[Nitya-07/07]
Provided ESF3-55UMC DK r2.0 with hspiceD

28nm
PDK
Likely
from UMC first. I am
netlist to
Invia
[Binh 07/01]
going to see them in 2 weeks. If things

a. Fab is not ready

involve us

this week 06/26
c. TC0 T/O ~ June
d. TC1 T/O Oct
AI
Review Device construction table and

technology layers - Request from
Xian[Nitya - 06/13]
Send TC0 padring and probepad layout to
Xian - To be sent to XMC for review and
approval[Nitya - 06/25]
Provide all DTC and WAT starting databases
for TC0 layout modification[Nitya-0625]
ESF3-65 Sapphire (code name for company in
Japan I just visited yesterday) likely to be
signed late July/early August
- Sapphire will have the first T/O in Sept/Oct
time frame with WAT and DTC. This will be in
65nm, not 55nm like GFS, UMC, or XMC.

b. Kick-off June 2014
c. TC0 T/O ~ July
d. TC1 T/O ~ November
Customer
Tech
PM
Prio
Scripts
340 ND
GFS
355 YH
1130 LC
SLT
1180 LC
340 ND
355 WY
355PDK
UMC
LFR, LFA
AST
TI
Mikron
NationZ
SMIC
328
3110 XL
390 XL
365 JH
390
KL
XMC
Saphire
365
Tech files
Generic Flow
Misc
Color code
Critical
Normal
Low priority
In-progress
Done
TD-CAD Methodology
markNet
Support SDL

Data organization
EM flow
micro pad placement
Device lib
Gate lib
Sche Lib
Lay Lib
Generate sample array

[Tri 06/27]
Convert SST layout DBs

to umc55eflash [Tri/Binh]

according to Tiempo
request [Nitya]
SPICE lib
Created GUI
utility to copy
symbol/verilog
views [Tri 06/26]
done by pregen

st automatically
Pregen deck
DRC deck
LVS deck
PEX deck
Add PEX, after

UMC40 tape-out
[Binh]
Create pregen
deck [Khoe/Binh
07/07]

invokes pre-gen [Tri the share pre-gen
pre-gen [Khoe 07/07]
07/07]
[Nitya - TBD]
Csdoc
Dkdoc
Tapeout
Tape out TC1 [Khoe/Binh]
Binh 06/30
Tape-out TC0 [Nitya 06/30
Converted Converted
layout
schematic
Added "pdk run" [Khoe

06/24]
Foundry PDK
Misc

06/27]
Install SLT PDK [Binh
06/20]
28nm PDK Likely from UMC first. I am

going to see them in 2 weeks. If things
a. Fab is not ready

involve us

this week 06/26
c. TC0 T/O ~ June
d. TC1 T/O Oct
ESF3-65 Sapphire (code name for company in

Japan I just visited yesterday) likely to be
signed late July/early August
- Sapphire will have the first T/O in Sept/Oct
time frame with WAT and DTC. This will be in
65nm, not 55nm like GFS, UMC, or XMC.
AI

c. TC0 T/O ~ July
Customer
Tech
PM
Prio
Scripts
Tech files
340 ND
GFS
355 YH
1130 LC
SLT
1180 LC
340 ND
355 WY
UMC
LFR, LFA
AST
TI
Mikron
NationZ
SMIC
355PDK
3110 XL
390 XL
365 JH
390
KL
XMC
Copy from
Generic Flow
Misc
Color code
Critical
Normal
Low priority
In-progress
Done
TD-CAD Methodology
markNet
Support SDL

Data organization
EM flow
micro pad placement
Device lib
Gate lib
Sche Lib
Lay Lib
Re-generate 2.5V array

to fix misalighment issue
[Tri 6/16]

according to Tiempo
request [Nitya]
Copy from ESF3-55GFS [Khoe/Binh 06/18]
SPICE lib
done by pregen

st automatically
Pregen deck
DRC deck
LVS deck
Updated TG rule description

[Khoe 6/17]
PEX deck
Add PEX, after

UMC40 tape-out
[Binh]
Release PEX deck

[Tri 06/20]

Create pregen
deck [Khoe 07/07] pre-gen [Khoe 07/07]
07/07]
[Nitya - TBD]
Update, demo and review Pregen/DRC/LVS batch mode scripts

with TDCAD [Nitya 06/19]
Csdoc
Dkdoc
Tapeout
Converted Converted
layout
schematic
Convert TC
DB and mini
array [Tri
06/17]
Khoe/Binh
06/18
Binh 06/30
Update, demo and

review tape-out batch
mode scripts with
TDCAD [Nitya 06/19]
Foundry PDK
Misc

06/27]
Install SLT PDK [Binh
06/20]
a. Fab is not ready

involve us

c. TC0 T/O ~ June
d. TC1 T/O Oct
Python pdk add/checkout/commit/install

[Khoe 06/19]
AI

c. TC0 T/O ~ July
Customer
Tech
PM
Prio
Scripts
Tech files
340 ND
GFS
355 YH
1130 LC
SLT
1180 LC
340 ND
355 WY
UMC
355PDK
LFR, LFA
AST
TI
Mikron
NationZ
SMIC
3110 XL
390 XL
365 JH
390
KL
XMC
Copy from
Generic Flow
Misc
Color code
Critical
Normal
Low priority
In-progress
Done
TD-CAD Methodology

markNet
Support SDL

Data organization
EM flow
micro pad placement
Device lib
Gate lib
Sche Lib
Lay Lib
Re-generate 2.5V array

[Tri]

according to Tiempo
request [Nitya]
SPICE lib
done by pregen

st automatically
Pregen deck
DRC deck
Updated TG rule description

[Khoe]
LVS deck
PEX deck
Add PEX, after

UMC40 tape-out
[Nitya]
Verify PEX deck [Tri

06/18]

Create pregen
deck [Khoe 07/07] pre-gen [Khoe 07/07]
07/07]
[Nitya - TBD]
Csdoc
Dkdoc
Tapeout
Converted Converted
layout
schematic
Convert TC
DB and mini
array [Tri
06/17]
Binh 06/15
Binh 06/30
Foundry PDK
Misc

06/27]
Install SLT PDK [Tri 06/27]
a. Fab is not ready

involve us

c. TC0 T/O ~ June
d. TC1 T/O Oct
Python pdk add/checkout/commit/install

[Khoe 06/19]
AI

c. TC0 T/O ~ July
Customer
Tech
PM
Prio
Scripts
Tech files
340 ND
GFS
355 YH
1130 LC
SLT
1180 LC
340 ND
355 WY
UMC
LFR, LFA
AST
TI
Mikron
NationZ
SMIC
355PDK
3110 XL
390 XL
365 JH
390
KL
XMC
Copy from
Script to
generate
layermap for
Calibredrv
[Khoe 06/09]
Generic Flow
Misc
Color code
Critical
Normal
Low priority
In-progress
Done
TD-CAD Methodology
markNet
Support SDL

Data organization
EM flow
micro pad placement
Device lib
Gate lib
Sche Lib
Lay Lib
Re-generate 9 arrays to
updated base cells [Tri
06/11]
Release device lib

from FDK A03 [Tri
06/12]

according to Tiempo
request [Nitya]
SPICE lib
done by pregen

st automatically
Pregen deck
Updated layers
[Khoe 06/11]
DRC deck
LVS deck
Add PEX, after

UMC40 tape-out
[Nitya]
Added 4 new DRC rule for HV

BEOL [Khoe 06/11]
Release DRC deck from

FDK A03 [Tri 06/12]
PEX deck
Release LVS deck

from FDK A03 [Tri
06/12]
Verify PEX deck [Tri

06/18]

Create pregen
deck [Nitya 07/07] pre-gen [Nitya 07/07]
07/07]
[Nitya - TBD]
Script to run
Pregen [Nitya
06/03]
Script to run DRC [Nitya

06/03]
Script to run LVS

[Nitya 06/03]
Csdoc
Dkdoc
Tapeout
Converted Converted
layout
schematic
Convert TC
DB and mini
array [Tri
06/17]
Binh 06/15
Binh 06/30
Script to prepare and

verify TO DB [Nitya
06/03]
Script for dry-run [Khoe
05/30]
Foundry PDK
Misc

06/27]
Install SLT PDK [Tri 06/27]
a. Fab is not ready

involve us

c. TC0 T/O ~ June
d. TC1 T/O Oct
Provide LEF-able tech files for SFC70 [Khoe/

06/04]
AI

c. TC0 T/O ~ July
Customer
Tech
PM
Prio
Scripts
Tech files
340 ND
355 YH
GFS
SLT
1130 LC
1180 LC
340 ND
UMC
LFR, LFA
AST
TI
Mikron
NationZ
SMIC
XMC
Generic Flow
Misc
355 WY
3110 XL
390 XL
365 JH
390
KL
Copy from
Color code
Critical
Normal
Low priority
In-progress
Done
TD-CAD Methodology
markNet
Support SDL

Data organization
EM flow
micro pad placement
Device lib
Gate lib
Sche Lib
Lay Lib
SPICE lib
Provide array layout to

GFS [Nitya 05/30]
Re-generate 6 arrays to
fix right WL termination
[Tri 06/06]
Added
RNPPO_LR_EF_UCF
N to DK r0.2 [Binh
06/04]
Added 2T cell
model and
sstlib.00 [Binh
05/22]
according to Tiempo
request [Nitya]
done by pregen

st automatically
Pregen deck
DRC deck
LVS deck
PEX deck
Check APMOM
extraction[Nitya
05/30]
[Khoe/Binh 06/04]
1) Dummy filling
2) Antenna
3) ESD
4) Die Seal
5) Pregen
6) Dryrun
Add PEX, after

UMC40 tape-out
[Nitya]

Create pregen
invokes pre-gen
the share pre-gen
deck [Khoe 07/07] pre-gen [Nitya 07/07]
[Nitya 07/07]
[Nitya - TBD]
Script to run
Pregen [Nitya
06/03]

06/03]
Script to run LVS

[Nitya 06/03]
Csdoc
Dkdoc
Tapeout
Update doc
[Binh]
Added UMC
manual set
[Binh 05/30]
Binh 06/15
Binh 06/30

verify TO DB [Nitya
06/03]
05/30]
Converted Converted
layout
schematic
Foundry PDK
Install GFS PDK [May]
Misc
Provide GFS with information regarding tapeout,

pregen and LVS deck[Nitya- Done 05/21]
Reviewed v1a2 tape-out database[Nitya 06/04]
Installed pdkumc55flash:
release test cases
DRC/LVS/PEX plus layout
DB conversion [tri/Binh
06/11]
Worked with Xian and Liz to approve Tiempo
proposal of merging ring modification [NityaDone 06/03]
a. Fab is not ready
involve us

c. TC0 T/O ~ June
d. TC1 T/O Oct
Run DRC on 16M DTC from GFS [Binh

05/29]
Streamedout example db to send to XMC
and later reviewed the database from Tri
upon Xian's request [Nitya - Done 06/03]
Porting sch/lay from one tech to another

tech [Tri 05/29]
AI

c. TC0 T/O ~ July
Customer
Tech
PM
Prio
Scripts
Tech files
Device lib
340 ND
GFS
SLT
355 YH
1130 LC
1180 LC
340 ND
UMC
LFR, LFA
355 WY
3110 XL
AST
TI
390 XL
365 JH
Mikron
NationZ
SMIC
390
KL
XMC
Copy fro
Generic Flow
Misc
Color code
Critical
Normal
Low priority
In-progress
Done
TD-CAD Methodology
markNet
Support SDL

Data organization
EM flow
micro pad placement
Gate lib
Sche Lib
Lay Lib
SPICE lib
Pregen deck
Provide array layout to

GFS [Nitya 05/30]
Re-generate 9 arrays [Tri

05/15]
Copy from ESF3-55GFS [Tri 06/10]
Create pregen
deck [Khoe 06/15]
Script to run
Pregen [Nitya
06/03]
DRC deck
LVS deck
PEX deck
Csdoc
Check APMOM
extraction[Nitya
05/30]
[Khoe/Binh 06/04]
1) Dummy filling
2) Antenna
3) ESD
4) Die Seal
5) Pregen
Add PEX, after

UMC40 tape-out
[Nitya]

invokes pre-gen
the share pre-gen
Binh 06/15
pre-gen [Nitya 06/15]
[Nitya 06/15]
[Nitya]

06/03]
Script to run LVS

[Nitya 06/03]
Dkdoc
Tapeout
Converted Converted
layout
schematic
Foundry PDK
Update doc
[Binh]
Review UMC 55 tape out

and compare with UMC40
layers [Binh 05/19]
release test cases
05/16]
Binh 06/30

verify TO DB [Nitya
06/03]
05/30]
Misc

a. Fab is not ready

involve us

c. TC0 T/O ~ June
d. TC1 T/O Oct
To compare DRC rules [Binh 06/04]

Run DRC on 16M DTC from GFS [Binh
05/23]
Porting sch/lay from one tech to another

tech [Tri 05/29]
AI

c. TC0 T/O ~ July
Customer
Tech
PM
Prio
Scripts
340 ND
GFS
SLT
355 YH
1130 LC
1180 LC
340 ND
UMC
LFR, LFA
355 WY
3110 XL
AST
TI
390 XL
365 JH
Mikron
NationZ
SMIC
390
KL
XMC
Generic Flow
Misc
Color code
Critical
Normal
Low priority
In-progress
Tech files
Device lib
Done
TD-CAD Methodology
markNet
Support SDL

Data organization
EM flow
micro pad placement
Gate lib
Sche Lib
Lay Lib
SPICE lib
Pregen deck
Re-generate 9 arrays [Tri

05/15]
Script to run
Pregen [Nitya]
DRC deck
LVS deck
PEX deck
Check LVS after

pregen [Nitya - Done
05/12 - April release
works without any
issues]
[Khoe/Binh 05/21]
1) Dummy filling
2) Antenna
3) ESD
4) Die Seal
5) Pregen
Script to run DRC [Nitya]
Add PEX, after

UMC40 tape-out
[Nitya]
Script to run LVS

[Nitya]
Csdoc
Dkdoc
Tapeout
Converted Converted
layout
schematic
Foundry PDK
Update doc
[Binh]
Review UMC 55 tape out

and compare with UMC40
layers [Binh 05/19]
release test cases
05/16]

verify TO DB [Nitya]
Misc

a. Fab is not ready

involve us

c. TC0 T/O ~ June
d. TC1 T/O Oct

Run DRC on 16M DTC from GFS
AI

c. TC0 T/O ~ July
Customer
Tech
PM
Prio
Scripts
Tech files
340 ND
LEF Gen
[Khoe/Binh]
GFS
355 YH
1130 LC
SLT
1180 LC
340 ND
UMC
LFR, LFA
355 WY
3110 XL
AST
390 XL
TI
365 JH
Mikron
NationZ
SMIC
390
KL
XMC
Misc
Color code
TD-CAD training for Tri/Khoe [Tri/Khoe/Binh]
DK 1.4 including
Klayout layer map,
markNet [Khoe
04/23]
Critical
Normal
Low priority
In-progress
Done
TD-CAD Methodology
markNet
Support SDL

Data organization
EM flow
Device lib
DK 1.4 including
sample device layout
and 2 resistor PCELL
Gate lib
Sche Lib
Lay Lib
Re-generate 6
arrays [Tri 05/13]
Removed MTL4 out

off rfiller [Tri 04/15]
SPICE lib
-- update display file also
Pregen deck
DRC deck
Update DRC deck

to reflect latest
release from
GFS[Nitya 04/02 ]
1st release
[Khoe 05/02]
LVS deck
PEX deck Csdoc
Dkdoc
Check LVS after

pregen [Nitya ?]
Add MV rules [Nitya

Add NH1, NHZ1
05/09]
[Khoe 05/7]
Update doc
[Binh]
Tapeout
Release pregen
deck and tapeout
flow to Design Team
[Nitya 04/2]
Taped out Linear
and Scaleo [Henry
04/21]
Converted Converted
layout
schematic
Foundry PDK
release test cases
05/16]
Installed V0.0.8 [Tri
04/15]
TC1 WAT TOII

[Henry 04/17]
Misc
AI
Install GFS Cadence lib [Nitya]
Provide tapeout information to GFS [Nitya Done 05/07]
Review IP Merging procedure [Nitya -Done with

initial review]
a. Fab is not ready

involve us

c. TC0 T/O ~ June
d. TC1 T/O Oct
a. Logic development
is on-going
b. Kick-off June
2014
c. TC0 T/O ~ July
d. TC1 T/O ~
November
Customer
Tech
PM
Prio
Scripts
Tech files
340 ND
LEF Gen
[Khoe/Binh]
GFS
SLT
355 YH
1130 LC
1180 LC
340 ND
UMC
LFR, LFA
355 WY
3110 XL
AST
390 XL
TI
365 JH
Mikron
NationZ
SMIC
390
KL
XMC
Misc
Color code
Critical
Normal
Low priority
In-progress
Done
DK 1.4 including
Klayout layer map,
markNet [Khoe
04/23]
TD-CAD Methodology
markNet
Support SDL

Data organization
Device lib
DK 1.4 including
Gate lib
Sche Lib
Lay Lib
6 arrays, clean LVS,

used in DTC A, B
[Tri 04/24]
Removed MTL4 out

SPICE lib
Pregen deck
DRC deck
Update DRC deck

to reflect latest
release from
GFS[Nitya 04/02 ]
1st release
[Khoe 05/02]
LVS deck
Check LVS after

pregen [Nitya ?]
Add MV rules [Nitya

Add NH1, NHZ1
05/09]
[Khoe 05/7]
PEX deck Csdoc Dkdoc
Tapeout
Release pregen
deck and tapeout
flow to Design Team
[Nitya 04/2]
Taped out Linear
and Scaleo [Henry
04/21]
Converted Converted
layout
schematic
Foundry PDK
Installed pdkumc55flash,
converted 2 sche DBs for
simulation [tri/Binh
05/01]
04/15]
TC1 WAT TOII

[Henry 04/17]
Installed [Tri]
Misc
Provide tapeout information to GFS [Nitya]
Review IP Merging procedure [Nitya ?]
a. Fab is not ready

involve us

c. TC0 T/O ~ June
d. TC1 T/O Oct
c. TC0 T/O ~ July
AI
Customer
Tech
PM
Prio
Scripts
Tech files
340 ND
LEF Gen
[Khoe/Binh]
355 YH
1130 LC
1180 LC
GFS
SLT
DK 1.4 including
Klayout layer map,
markNet [Khoe
04/23]
340 ND
UMC
355 WY
LFR, LFA
3110 XL
AST
390 XL
TI
365 JH
Mikron
NationZ
SMIC
390
KL
XMC
Misc
Color code
Critical
Normal
Low priority
In-progress
Done
TD-CAD Methodology
Support LEF generation [Binh to feedback Rodger/Pixy/Alice 12/27]
markNet
Support SDL

Data organization
Device lib
DK 1.4 including
Gate lib
Sche Lib
Lay Lib
6 arrays, clean LVS,

used in DTC A, B
[Tri 04/24]
Removed MTL4 out

SPICE lib
Pregen deck
DRC deck
Update DRC deck

to reflect latest
release from
GFS[Nitya 04/02 ]
1st release
[Khoe 05/02]
LVS deck
Check LVS after

pregen [Nitya ?]
Release DK r1.4 to
sync with FDK
ver.A11 [Khoe
Add NH1, NHZ1
04/23]
[Khoe 05/7]
Add MV rules [Nitya
05/09]
Tapeout
Release pregen
deck and tapeout
flow to Design Team
[Nitya 04/2]
Taped out Linear
and Scaleo [Henry
04/21]
Converted Converted
layout
schematic
Foundry PDK
Installed pdkumc55flash,
converted 2 sche DBs for
simulation [tri/Binh
05/01]
04/15]
TC1 WAT TOII

[Henry 04/17]
Installed [Tri]
Misc
Review IP Merging procedure [Nitya ?]
a. Fab is not ready

involve us

c. TC0 T/O ~ June
d. TC1 T/O Oct
c. TC0 T/O ~ July
AI
Customer
Tech
PM
Prio
Scripts
Tech files
340 ND
355 YH
GFS
1130 LC
SLT
1180 LC
340 ND
UMC
LFR, LFA
AST
TI
Mikron
NationZ
SMIC
LEF Gen [Khoe/Binh]
355 WY
3110 XL
390 XL
365 JH
390
KL
XMC
Color code
Critical
Normal
Low priority
In-progress
Done
Option: chip v.s. cell
TD-CAD Methodology
PDK flow: pregen first, then DRC
QA and Release flow [Binh ?]
markNet
Support SDL

Data organization
Device lib
Gate lib
mos subckt term

order [Nitya]
Opened gates
Sche Lib
Lay Lib
SPICE lib
Pregen deck
DRC deck
Update DRC deck

to reflect latest
release from
GFS[Nitya 03/25 ]
1) PEO
2) NEO
LVS deck
Tapeout
Converted Converted
layout
schematic
Foundry
PDK
Release pregen
deck and tapeout
flow to Design
Team [Nitya
03/28]
From ESF340GFS
[Binh]
[Tri/Binh]
Misc
Providing help whenever necessary to

figure out reason for TC issue[Nitya]
Create PDK package (DRC/LVS/Antenna) to
send to customer [Nitya - Done 03/17]
Answering questions about phantom ring
[Nitya]
a. Fab is not ready

b. Logic development begins in Q4 2014 may involve us

c. TC0 T/O ~ June
d. TC1 T/O Oct

c. TC0 T/O ~ July
AI
Progra
Prio
m
Manag rity
er
Tech
Customer
340 ND
355 YH
GFS
1130 LC
SLT
1180 LC
340 ND
UMC
LFR, LFA
355 WY
3110 XL
AST
390 XL
TI
365 JH
Mikron
NationZ
390
KL
Color code
Critical
Normal
Low priority
In-progress
Done
TD-CAD Methodology
PDK flow: pregen first, then DRC
markNet
Calibre LVS setup: path to CDL file
Support SDL
Data organization
Scripts (project
setup, virt*)
Tech files
(map,dis,tech)
Device library
Gate library
mos subckt term order

[Nitya]
Option: chip v.s. cell
[Binh 01/10]
Henry 01/17 - Done
Opened gates
[Henry/Binh 01/21]
[Henry/Binh 01/21]
Schematic
Library (example
array)
Layout Lib
(probe cell, IP
merging ring,
example array)
SPICE/HSIM lib
TRAN simulation can not

work well for HSIM
[Henry ?]
Integrate SPICE lib for

Synaptics tape out by
Jan/2014 [Nitya 12/20]
[Henry/Binh 01/21]
Pregen deck
Remove redundant signals

from lower level after
pregen to support LVS
after pregen [Nitya ?]
DRC deck
LVS deck
Sample sche
Logo rules [Nitya 12/19 Done]
Sample layout
5 samples [Binh 12/11]
Deck
Per Design team and
JinHo's input, Probecell
regconition not required in
DTC & current LVS deck
does not check for
probecell[Nitya]
Update Deck to reflect

latest version from
GFS[Nitya-Done 01/27]
from Parviz's update [Binh

01/07]
Update for poly residues

[Binh 01/24]
[Henry/Binh 02/06]
[Binh 02/11 ]
[Henry ??]
PEX deck
Csdoc
Dkdoc
Tapeout
DRC/LVS/PEX revisions for

tapeout [Nitya 01/07]
Add IP tag to Ceitec Macro

and Tapeout[Nitya]
[Binh 12/31]
Sent TC2 WAT db to SH/TW

teams [Nitya 01/08]
Install [Binh 02/14]
[Henry 11/17]
[Binh 02/05]
Taped out TC0 [Henry

01/09]
Converted layout
Converted
schematic
Misc
Work with GFS to resolve

cell recognition issue
during LVS using GFS
deck(request from GFS)
[Done: Nitya - 02/04]
Stream-in and pregen new
array from Shanghai
Team[Nitya - 01/02 Done]
Install
GFS
Cadence
Created
and
releasedlib
[cadsystem]
Tapeout
DRC/LVS/PEX deck
revision document to
GFS[Nitya-01/08 - Done]
Provided WAT TC2 starting
database to layout
team[Nitya-01/14 - Done]
Modify TC1
Update
IP Merging
Databases[Nitya
- 01/31] Ring[Nitya]
In
Discussion
with LFA
markNet
[Binh 12/20]
Pregen
TC3
Provided
LFAWAT
with a
database[Nitya]
preliminary review of the
latest DRC Deck and
Pregen
andmeeting
Tapeoutto
TC3
scheduled
TC
database[Nitya]
discuss
the same[Nitya 01/10] - Done
Modify Example array
layout in LF PDK[Nitya
01/15-Done]
Start early PDK

Grid snapping
Diva DRC for WAT
[Henry 02/06]
[Binh 01/15]
Add tsmcN90emf
to the system
AI
TD-CAD Tasklist
Last updated: 01/20/2014
Technology-specific tasks
Color code
Critical
Normal
Low priority
In-progress
Done
Tech
Customer
Program
Manager
Priori
ty
340 ND
GFS
355 YH
1130 LC
340 ND
UMC
LFR, LFA
AST
355 WY
3110 XL
390 XL
TI
Mikron
365 JH
390
NationZ
KL
TD-CAD Methodology
markNet
Remove pregen out of GFS55
Support SDL

Data organization
Scripts (project
setup, virt*)
Tech files
(map,dis,tech)
Device library
Gate library
mos subckt term

order [Nitya]
Option: chip v.s.

cell
Opened gates
[Binh 01/10]
[Henry 01/13]
Schematic
Library (example
array)
Layout Lib
(probe cell, IP
merging ring,
example array)
SPICE/HSIM lib
TRAN simulation can

not work well for
HSIM [Henry ?]
Integrate SPICE lib

for Synaptics tape
out by Jan/2014
[Nitya 12/20]
Pregen deck
DRC deck
LVS deck
Sample
sche
Logo rules
[Nitya 12/19]
Sample layout
5 samples [Binh
12/11]
Update for GFS

deck Sep
release [01/13
Nitya]
from Parviz's
update [Binh
01/07]
Update
Deck
[Binh 01/17 ]
PEX deck
Csdoc
Dkdoc
Update
Tapeout
DRC/LVS/PEX
revisions for
tapeout [Nitya
01/07]
[Binh
12/31]
Install
Converted layout
[Binh 12/20]
Sent TC2 WAT db to

SH/TW teams [Nitya
01/08]
Taped out TC0

[Henry 01/09]
[Binh 01/14]
Converted
schematic
Misc
Install GFS Cadence lib

[Nitya]
markNet [There is no issue
with markNet - Nitya 12/19]
markNet
Modify Example array layout

in LF PDK, Modify TC1
Databases[Nitya 01/15]
Convert to PDK to IC61
[Binh ?]
[Binh 01/15]
TI PDK setup [Henry/Binh

01/14]
system
AI
TD-CAD Tasklist
Color code
Critical
Normal
Low priority
In-progress
Done
Tech
Customer
Program
Manager
Priori
ty
Scripts (project
setup, virt*)
Tech files
(map,dis,tech)
340 ND
GFS
355 YH
1130 LC
340 ND
UMC
LFR, LFA
355 WY
3110 XL
AST
390 XL
TI
365 JH
1 [Binh 01/10]
Option: chip v.s.

cell
Mikron
NationZ
390
KL
TD-CAD Methodology
markNet
Support SDL

Data organization
Device library
Gate library
SPICE/HSIM lib
mos subckt term

order [Nitya]
DRC deck
Logo rules
[Nitya 12/19]
TRAN simulation can
not work well for
HSIM [Henry ?]
Opened gates
Integrate SPICE lib
for Synaptics tape
out by Jan/2014
[Nitya 12/20]
[Henry 01/13]
Pregen deck
Update for GFS

deck Sep
release [01/13
Nitya]
LVS deck
Sample
sche
Sample layout
5 samples [Binh
12/11]
from Parviz's
update [Binh
01/07]
[Binh 01/17 ]
PEX deck
Deck
Csdoc
Dkdoc
Update
Tapeout
Converted layout
Converted
schematic
DRC/LVS/PEX
revisions for
tapeout [Nitya
01/07]
[Binh
12/31]
[Binh 12/20]
Sent TC2 WAT db to

SH/TW teams [Nitya
01/08]
Taped out TC0

[Henry 01/09]
[Binh 01/14]
[Binh 01/15]
Misc

[Nitya]
markNet

[Binh ?]
TI PDK setup [Henry/Binh
01/14]
AI

system
TD-CAD Tasklist
Color code
Critical
Normal
Low priority
Done
Tech
Customer
Program
Manager
Priori
ty
Scripts (project
setup, virt*)
Tech files
(map,dis,tech)
340 ND
GFS
355 YH
1130 LC
340 ND
UMC
LFR, LFA
AST
355 WY
3110 XL
390 XL
Option: chip v.s.

cell
TI
Mikron
365 JH
390
NationZ
KL
TD-CAD Methodology
markNet
Support SDL

Device library
Gate library
SPICE/HSIM lib
mos subckt term

order [Nitya]
Pregen deck
DRC deck
Logo rules
[Nitya 12/19]
TRAN simulation can
not work well for
HSIM [Henry ?]
Opened gates
Integrate SPICE lib
for Synaptics tape
out by Jan/2014
[Nitya 12/20]
Update for GFS

deck Sep
release [01/13
Nitya]
Talking to TI for
K2 setup
[Henry/Binh
01/10]
LVS deck
Sample
sche
Sample layout
PEX deck
Deck
Per Design team and JinHo's input,

Probecell regconition not required in
5 samples [Binh DTC & current LVS deck does not check
12/11]
for probecell[Nitya]
from Parviz's
update [Binh
01/07]
[Binh ?]
Csdoc
Dkdoc
Update
[Binh
12/31]
Tapeout
Converted layout
DRC/LVS/PEX
revisions for
tapeout [Nitya
01/07]
[Binh 12/20]
Converted
schematic
[Binh ?]
Misc

[Nitya]
markNet

[Binh ?]
AI
Modify 3 masks for ESF3-55

UMC to support ESF3-65 TI
1.2V technology [Henry
12/19]
TC1: PDK release (2-4 weeks)
system
TD-CAD Tasklist
Color code
Critical
Normal
Low priority
Done
Tech
Customer
Program
Manager
Priori
ty
Tech files
(map,dis,tech)
mos subckt term

order [Nitya]
340 ND
GFS
355 YH
1130 LC
340 ND
UMC
LFR, LFA
355 WY
3110 XL
AST
390 XL
TI
Mikron
365 JH
390
Device library
Option: chip v.s.

2 cell
NationZ
KL
TD-CAD Methodology
markNet

Gate library
SPICE/HSIM lib
Pregen deck
DRC deck
LVS deck
Sample
sche
Logo rules
[Nitya 12/19]
TRAN simulation can
not work well for
HSIM [Henry ?]
Update for GFS

deck Sep
release [Nitya]
Opened gates
Integrate SPICE lib
for Synaptics tape
out by Jan/2014
[Nitya ?]
Review Hercules
TI 45 [Henry ?]
LVS deck
Sample layout
PEX deck
Csdoc
Dkdoc
Tapeout
Deck
probecell
5 samples [Binh regconition
12/11]
[Nitya]
Update
from Parviz's
update [Binh
01/07]
[Binh ?]
[Binh
12/31]
DRC/LVS/PEX
revisions for
tapeout [Binh
12/23]
Converted
layout
Converted
schematic
Misc
AI

[Nitya]
markNet
[Binh 12/20]
markNet
Update layers [Nitya ?]

[Binh ?]
[Binh ?]
Modify 3 masks for ESF3-55

UMC to support ESF3-65 TI
1.2V technology [Henry
12/19]
TC1: PDK release (2-4 weeks)

system
TD-CAD Tasklist
Color code
Critical
Normal
Low priority
Done
Tech
Customer
Tech files
(map,dis,tech)
340
GFS
355
1130
UMC
LFR
AST
Option: chip v.s.

340 cell
355
3110
390
TI
Mikron
Device library
Gate library
mos subckt term

order [Nitya]
365
390
NationZ
TD-CAD Methodology
Release flow
QA flow
Antenna info
markNet
Opened gates
SPICE/HSIM lib
Pregen deck
DRC deck
LVS deck
Sample
sche
+WAT deck
[Nitya 12/10]
Sample layout
5 samples [Binh
12/11]
TRAN simulation can

not work well for
HSIM
from Parviz's
update
[Binh 12/13]
VS deck
PEX deck
Csdoc
Dkdoc
Deck
probecell
regconition
[Nitya]
Update
Tapeout
Converted
layout
Converted
schematic
Misc

[Nitya]
markNet
markNet

Need to wait for TI PDK to
plan accordingly
system

TD-CAD Tasklist 20151113

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TD-CAD Tasklist 20151113

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Project

Implement PDK db2db command - phase2 Schematic Conversion

Review and improve genLVS.pl tool

Implement PDK db2db command - phase2 Schematic Conversion

review and improve my function

created skill functions use to

Implementing code to check missing parameters in netlist

Implement PDK db2db command - phase2 Schematic Conversion

ESF3 Compiler Review

All_device example is LVS/DRC clean (include

Below is the PEX files for LV just downloaded:

created skill functions use to

- Code SKILL to array bitcell

Implementing code to check missing parameters in netlist

Implement PDK db2db command - phase2 Schematic Conversion

ESF3 Compiler Review

Build a start point ESF3 template to generate A0 WAT

convert schematic from DK1.0 to DK1.1

Support generate WATs

a. Review ESF3 layout compiler to understand how to use the compiler to

Implement functions to process technology rules + via stack

1. Build other spines based on Jinho's requests

CDF params: done

created skill functions use to

Implementing code to check missing parameters in netlist

Implement PDK db2db command - phase2 Schematic Conversion

Support drawing an array of VIAs in the ring

ESF3 Compiler Review

Build a start point ESF3 template to generate A0 WAT

ESF3 Compiler Review:

CDF params: done

Implementing utility functions

Implement PDK db2db command - phase1 Layout Conversion

Support generating DTC/WAT arrays

Implementing code to check missing parameters in netlist

Implement PDK db2db command - phase2 Schematic Conversion

Implementing code to check missing parameters in netlist

Implemented script request for

file, but it needs to update

Ask Jenny Peng to send GDS/netlist to us to help debugging

Implement PDK db2db command - phase1 Layout Conversion

Support generating DTC/WAT arrays

Implementing code to check missing parameters in netlist

Implement PDK db2db command - phase2 Schematic Conversion

Implementing code to check missing parameters in netlist

Review V1.S7 and V2.S7 rules for pfm-340u512kx32_v10a database, to make

Converted.Layout.Li In.Reviewing Normal

Implemented script request for

a. Wrote code to parse xlsx

Ask Jenny Peng to send GDS/netlist to us to help debugging

Implement PDK db2db command

Update pdk compile command to add DRC/LVS running feature

Install the new version of Dummy Filling Rule deck

Sample tape-out run:

In the past tape-out runs were normally located at:

Implemented script request for

Implement PDK db2db command

ESF3-40 UMC schematic libraries to ESF3-110 LF schematic libraries

Update pdk compile command to add DRC/LVS running feature

Add layers CGPO:FLGT and CGPO:LVS into layermap file

Add layers CGPO:FLGT and CGPO:LVS into layermap file

Implemented script request for

Working on a.Thuan's feedback