04 MathALU

Number Systems and Arithmetic
Jason Mars
Thursday, January 24, 13
What do all those bits mean?
bits (011011011100010 ....01)

data
instruction
number
R-format
I-format ...
signed
...
integer
unsigned
...
text chars
..............
floating point
single precision
...
double precision
...
Questions About Numbers

How do you represent
negative numbers?
fractions?
really large numbers?
really small numbers?
How do you
do arithmetic?
identify errors (e.g. overflow)?
What is an ALU and what does it look like?
ALU=arithmetic logic unit
Introduction to Binary Numbers

Consider a 4 bit binary number
Decimal
0
Binary
0000
Decimal
4
Binary
0100
1
2
3
0001
0010
0011
5
6
7
0101
0110
0111
Examples of binary arithmetic

3+2=5
3+3=6

Decimal
0
Binary
0000
Decimal
4
Binary
0100
1
2
3
0001
0010
0011
5
6
7
0101
0110
0111

3+2=5
3+3=6

Decimal
0
Binary
0000
Decimal
4
Binary
0100
1
2
3
0001
0010
0011
5
6
7
0101
0110
0111

3+2=5
3+3=6

Decimal
0
Binary
0000
Decimal
4
Binary
0100
1
2
3
0001
0010
0011
5
6
7
0101
0110
0111

3+2=5
3+3=6

Decimal
0
Binary
0000
Decimal
4
Binary
0100
1
2
3
0001
0010
0011
5
6
7
0101
0110
0111

3+2=5
3+3=6

Decimal
0
Binary
0000
Decimal
4
Binary
0100
1
2
3
0001
0010
0011
5
6
7
0101
0110
0111

3+2=5
3+3=6

Decimal
0
Binary
0000
Decimal
4
Binary
0100
1
2
3
0001
0010
0011
5
6
7
0101
0110
0111

3+2=5
3+3=6
Negative Numbers?
We would like a number system that provides
obvious representation of 0,1,2...
uses adder for addition
single value of 0
equal coverage of positive and negative numbers
easy detection of sign
easy negation
Twos Complement Representation

2s complement representation of negative numbers
Take the bitwise inverse and add 1
Biggest 4-bit Binary Number: 7
Decimal
-8
-7
-6
-5
-4
-3
-2
-1
0
1
2
3
4
5
6
7
Smallest 4-bit Binary Number: -8

Two s Complement Binary
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
Twos Complement Arithmetic (Subtraction)

Decimal
2 s Complement Binary
Decimal
0
1
2
0000
0001
0010
-1
-2
-3
1111
1110
1101
3
4
0011
0100
-4
-5
1100
1011
5
6
7
0101
0110
0111
-6
-7
-8
1010
1001
1000
Examples: 7 - 6 = 7 + (- 6) = 1
3 - 5 = 3 + (- 5) = -2

Decimal
Decimal
0
1
2
0000
0001
0010
-1
-2
-3
1111
1110
1101
3
4
0011
0100
-4
-5
1100
1011
5
6
7
0101
0110
0111
-6
-7
-8
1010
1001
1000
Examples: 7 - 6 = 7 + (- 6) = 1
1
3 - 5 = 3 + (- 5) = -2

Decimal
Decimal
0
1
2
0000
0001
0010
-1
-2
-3
1111
1110
1101
3
4
0011
0100
-4
-5
1100
1011
5
6
7
0101
0110
0111
-6
-7
-8
1010
1001
1000
Examples: 7 - 6 = 7 + (- 6) = 1
3 - 5 = 3 + (- 5) = -2

Decimal
Decimal
0
1
2
0000
0001
0010
-1
-2
-3
1111
1110
1101
3
4
0011
0100
-4
-5
1100
1011
5
6
7
0101
0110
0111
-6
-7
-8
1010
1001
1000
Examples: 7 - 6 = 7 + (- 6) = 1
3 - 5 = 3 + (- 5) = -2

Decimal
Decimal
0
1
2
0000
0001
0010
-1
-2
-3
1111
1110
1101
3
4
0011
0100
-4
-5
1100
1011
5
6
7
0101
0110
0111
-6
-7
-8
1010
1001
1000
Examples: 7 - 6 = 7 + (- 6) = 1
3 - 5 = 3 + (- 5) = -2

Decimal
Decimal
0
1
2
0000
0001
0010
-1
-2
-3
1111
1110
1101
3
4
0011
0100
-4
-5
1100
1011
5
6
7
0101
0110
0111
-6
-7
-8
1010
1001
1000
Examples: 7 - 6 = 7 + (- 6) = 1
3 - 5 = 3 + (- 5) = -2

Decimal
Decimal
0
1
2
0000
0001
0010
-1
-2
-3
1111
1110
1101
3
4
0011
0100
-4
-5
1100
1011
5
6
7
0101
0110
0111
-6
-7
-8
1010
1001
1000
Examples: 7 - 6 = 7 + (- 6) = 1
3 - 5 = 3 + (- 5) = -2

Decimal
Decimal
0
1
2
0000
0001
0010
-1
-2
-3
1111
1110
1101
3
4
0011
0100
-4
-5
1100
1011
5
6
7
0101
0110
0111
-6
-7
-8
1010
1001
1000
Examples: 7 - 6 = 7 + (- 6) = 1
3 - 5 = 3 + (- 5) = -2

Decimal
Decimal
0
1
2
0000
0001
0010
-1
-2
-3
1111
1110
1101
3
4
0011
0100
-4
-5
1100
1011
5
6
7
0101
0110
0111
-6
-7
-8
1010
1001
1000
Examples: 7 - 6 = 7 + (- 6) = 1
3 - 5 = 3 + (- 5) = -2
1

Decimal
Decimal
0
1
2
0000
0001
0010
-1
-2
-3
1111
1110
1101
3
4
0011
0100
-4
-5
1100
1011
5
6
7
0101
0110
0111
-6
-7
-8
1010
1001
1000
Examples: 7 - 6 = 7 + (- 6) = 1
3 - 5 = 3 + (- 5) = -2
1

Decimal
Decimal
0
1
2
0000
0001
0010
-1
-2
-3
1111
1110
1101
3
4
0011
0100
-4
-5
1100
1011
5
6
7
0101
0110
0111
-6
-7
-8
1010
1001
1000
Examples: 7 - 6 = 7 + (- 6) = 1
3 - 5 = 3 + (- 5) = -2

Decimal
Decimal
0
1
2
0000
0001
0010
-1
-2
-3
1111
1110
1101
3
4
0011
0100
-4
-5
1100
1011
5
6
7
0101
0110
0111
-6
-7
-8
1010
1001
1000
Examples: 7 - 6 = 7 + (- 6) = 1
3 - 5 = 3 + (- 5) = -2

Decimal
Decimal
0
1
2
0000
0001
0010
-1
-2
-3
1111
1110
1101
3
4
0011
0100
-4
-5
1100
1011
5
6
7
0101
0110
0111
-6
-7
-8
1010
1001
1000
Examples: 7 - 6 = 7 + (- 6) = 1
3 - 5 = 3 + (- 5) = -2
Some Things We Want To Know About Our

Number System
Negation
Sign extension
+3 => 0011, 00000011, 0000000000000011
-3 => 1101, 11111101, 1111111111111101
Overflow detection
0101 5
+ 0110 6

Number System
Negation
Sign extension
+3 => 0011, 00000011, 0000000000000011
-3 => 1101, 11111101, 1111111111111101
Overflow detection
0101 5
+ 0110 6
1

Number System
Negation
Sign extension
+3 => 0011, 00000011, 0000000000000011
-3 => 1101, 11111101, 1111111111111101
Overflow detection
0101 5
+ 0110 6
11

Number System
Negation
Sign extension
+3 => 0011, 00000011, 0000000000000011
-3 => 1101, 11111101, 1111111111111101
Overflow detection
0101 5
+ 0110 6
011

Number System
Negation
Sign extension
+3 => 0011, 00000011, 0000000000000011
-3 => 1101, 11111101, 1111111111111101
Overflow detection
0101 5
+ 0110 6
1011

Number System
Negation
Sign extension
+3 => 0011, 00000011, 0000000000000011
-3 => 1101, 11111101, 1111111111111101
Overflow detection
0101 5
+ 0110 6
1011 -5

Number System
Negation
Sign extension
+3 => 0011, 00000011, 0000000000000011
-3 => 1101, 11111101, 1111111111111101
Overflow detection
0101 5
+ 0110 6
1011 -5
Overflow Detection
0
-6
How do we detect overflow?

XOR Carry In and Carry Out of MSB
-4
-2
-6
-4
-5
Overflow Detection
0
OK
-6

-4
-2
-6
-4
-5
Overflow Detection
0
OK
-6
Not OK

-4
-2
-6
-4
-5
Arithmetic -- The Heart of Instruction Execution

Instruction
Fetch
Instruction
Decode
operation
Operand
Fetch
a
Execute
32
ALU
result
Result
Store
Next
Instruction
32
b
32
Designing an Arithmetic Logic Unit

ALUop
A
Zero
ALU
Result
Overflow
N
CarryOut
ALU Control Lines (ALUop)

000
001
010
110
111
Function
And
Or
Add
Subtract
Set-on-less-than
A One Bit ALU

This 1-bit ALU will perform AND, OR, and ADD
-4
-2
-6
A One Bit ALU

-4
-2
-6
A One Bit ALU

0
1
-4
-2
-6
A One Bit ALU

-4
-2
-6
0
1
A One Bit ALU

-4
-2
-6
0
1
A One Bit ALU

-4
-2
-6
A One Bit ALU

-4
-2
-6
A One Bit ALU

-4
-2
-6
A One Bit ALU

-4
-2
-6
A One Bit ALU

-4
-2
-6
0
32 Bit ALU
1-bit ALU
32-bit ALU
Relationship Between ISAs and ALUs

Instruction
Fetch
Instruction
Decode
operation
Operand
Fetch
a
Execute
32
ALU
result
Result
Store
Next
Instruction
32
b
32

After Decode
Implements All Arithmetic Execution
Inputs
Source Operands, Registers
Destination
Destination Operand
Instruction
Fetch
Instruction
Decode
operation
Operand
Fetch
a
Execute
32
ALU
result
Result
Store
Next
Instruction
32
b
32

After Decode
Implements All Arithmetic Execution
Inputs
Source Operands, Registers
Destination
Destination Operand
Instruction
Fetch
Instruction
Decode
Execute
32
ALU
result
Result
Store
Next
Instruction
Will all come together with single cycle cpu, I promise ;-)
operation
Operand
Fetch
32
b
32
The ALUs Job - A Few Example Operations

And, Or, Addition
add

And, Or, Addition
add
Subtraction
sub

And, Or, Addition
add
Subtraction
sub
Set-on-less-than
slt

And, Or, Addition
add
Subtraction
sub
Set-on-less-than
slt
Branch-if-equal
beq
Adding Subtraction
Keep in mind the following:
(A - B) is the same as: A + (-B)
2s Complement negate: Take the inverse of every bit and add 1
Bit-wise inverse of B is !B:
A - B = A + (-B) = A + (!B + 1) = A + !B + 1
Adding Subtraction
A - B = A + (-B) = A + (!B + 1) = A + !B + 1
Adding Subtraction
A - B = A + (-B) = A + (!B + 1) = A + !B + 1
Lets throw in NOR while were at it!

Adding Subtraction
C-32
Appendix C The Basics of Logic Design
A - B = A + (-B) = A + (!B + 1) = A + !B + 1
Ainvert
Operation
Binvert
CarryIn
0
0
Result
CarryOut
Lets throw in NOR while were at it!
__
__
FIGURE C.5.9 A 1-bit ALU

__ that performs AND, OR, and addition on a and b or a and b. By
_
selecting a (Ainvert = 1) and b (Binvert = 1), we get a NOR b instead of a AND b.
multiplexor in Figure C.5.8 to add an input for the slt result. We call that new input
Adding Set-on-less-than
We are mostly there!

A < B = (A - B) < 0
If true, set LSB to 1, all others 0
Else, set all bits to 0
C.5
Constructing a Basic Arithmetic Logic Unit
Operation
Ainvert
Binvert
a
CarryIn
1
1
Result
b
1
Less
CarryOut
We are mostly
there!
Operation
Ainvert
CarryIn
A < B = (A Binvert
- B) < 0
If true,
set LSB
to 1, all others 0
a
0
0
1
1
C-33
!
1
Less
C.5
Binvert
CarryIn
a
Operation
Ainvert
Operation
Ainvert
Binvert
C-33
CarryOut
CarryIn
Result
b
Result
b
2
Less
Set
Less
MSB
CarryOut
We are mostly
there!
Operation
Ainvert
CarryIn
A < B = (A Binvert
- B) < 0
If true,
set LSB
to 1, all others 0
a
0
0
1
1
Overflow
detection
Overflow
__
FIGURE C.5.10 (Top) A 1-bit ALU that performs AND, OR, and addition on a and b or b, and
(bottom) a 1-bit ALU for the most significant bit. The top drawing includes a direct input that is
connected to perform the set on less than operation (see Figure C.5.11); the bottom has a direct output from
the adder for the less than comparison called Set. (See Exercise C.24 at the end of this Appendix to see how
to calculate overflow with fewer inputs.)
AppendixC-9780123747501.indd 33
!
1
Less
C.5
Binvert
CarryIn
a
Operation
Ainvert
Operation
Ainvert
Binvert
C-33
CarryOut
CarryIn
Result
b
Result
1
2
Less
Set
Less
Overflow
__
MSB
CarryOut
We are mostly
there!
Operation
Ainvert
CarryIn
A < B = (A Binvert
- B) < 0
If true,
set LSB
to 1, all others 0
a
0
0
1
1
Overflow
detection
FIGURE C.5.10 (Top) A 1-bit ALU that performs AND, OR, and addition on a and b or b, and
(bottom) a 1-bit ALU for the most significant bit. The top drawing includes a direct input that is
connected to perform the set on less than operation (see Figure C.5.11); the bottom has a direct output from
the adder for the less than comparison called Set. (See Exercise C.24 at the end of this Appendix to see how
to calculate overflow with fewer inputs.)
+
AppendixC-9780123747501.indd 33
0
1
1
0
1
1
0
1
0
0
1
1
0
1
1
What about overflow?
Overflow Detection
Decimal
-8
-7
-6
-5
-4
-3
-2
-1
0
1
2
3
4
5
6
7

1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
When is Overflow Possible?

Positive + Negative = Overflow Impossible
Negative + Positive = Overflow Impossible
Positive + Positive = Can Overflow
Negative + Negative = Can Overflow
Overflow Detection
Decimal
-8
-7
-6
-5
-4
-3
-2
-1
0
1
2
3
4
5
6
7

1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111

A Problem for SLT ( -7 < 6 ) -->
Overflow Detection
Decimal
-8
-7
-6
-5
-4
-3
-2
-1
0
1
2
3
4
5
6
7

1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111


-7 + (-6) = 3 -->
Overflow Detection
Decimal
-8
-7
-6
-5
-4
-3
-2
-1
0
1
2
3
4
5
6
7

1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111


-7 + (-6) = 3 -->
MSB=0 -->
Overflow Detection
Decimal
-8
-7
-6
-5
-4
-3
-2
-1
0
1
2
3
4
5
6
7

1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111


-7 + (-6) = 3 -->
MSB=0 -->
-7 > 6!!
Overflow Detection
Decimal
-8
-7
-6
-5
-4
-3
-2
-1
0
1
2
3
4
5
6
7

1000
1001
0
1010
1011
1100
+
1101
1110
1111
0000
0001
0
0010
0011
0100
+
0101
0110
0111
-6

-4
-2
-6
-4
-5

-7 + (-6) = 3 -->
MSB=0 -->
-7 > 6!!
Overflow Detection
Decimal
-8
-7
-6
-5
-4
-3
-2
-1
0
1
2
3
4
5
6
7

1000
1001
0
1010
1011
1100
+
1101
1110
1111
0000
0001
0
0010
0011
0100
+
0101
0110
0111
-6

OK
-4
-2
-6
-4
-5

-7 + (-6) = 3 -->
MSB=0 -->
-7 > 6!!
Overflow Detection
Decimal
-8
-7
-6
-5
-4
-3
-2
-1
0
1
2
3
4
5
6
7

1000
1001
0
1010
1011
1100
+
1101
1110
1111
0000
0001
0
0010
0011
0100
+
0101
0110
0111
-6

OK
Not
OK
-4
-2
-6
-4
-5

-7 + (-6) = 3 -->
MSB=0 -->
-7 > 6!!
Overflow Detection Logic

Carry into MSB ! = Carry out of MSB
For a N-bit ALU: Overflow = CarryIn[N - 1] XOR CarryOut[N - 1]
CarryIn0
A0
B0
A1
B1
A2
B2
1-bit
Result0
ALU
CarryIn1 CarryOut0
1-bit
Result1
ALU
CarryIn2 CarryOut1
1-bit
Result2
ALU
CarryOut2
CarryIn3
A3
B3
1-bit
ALU
CarryOut3
Result3
X XOR Y
0
0
0
1
0
1
1
1
0
1
1
0
Overflow Detection Logic

Carry into MSB ! = Carry out of MSB
For a N-bit ALU: Overflow = CarryIn[N - 1] XOR CarryOut[N - 1]
CarryIn0
A0
B0
A1
B1
A2
B2
1-bit
Result0
ALU
CarryIn1 CarryOut0
1-bit
Result1
ALU
CarryIn2 CarryOut1
X XOR Y
0
0
0
1
0
1
1
1
0
1
1
0
1-bit
Result2
ALU
CarryOut2
CarryIn3
A3
B3
1-bit
ALU
CarryOut3
Result3
Overflow
Adding Branch-if-equal
Subtract to the rescue
again!
again!
If (A - B = 0) --> A = B
again!
If (A - B = 0) --> A = B
Zero Detection Logic is just
one BIG NOR gate (for
equality test)
Any non-zero input to the
NOR gate will cause its
output to be zero
simplest way is to OR all the outputs together and then send that signal through
an inverter:
Zero = ( Result31 + Result30 + . . . + Result2 + Result1 + Result0 )
Figure B.5.12 shows the revised 32-bit ALU. We can think of the combination
of the 1-bit Ainvert line, the 1-bit Binvert line, and the 2-bit Operation lines as 4bit control lines for the ALU, telling it to perform add, subtract, AND, OR, or set
on less than. Figure B.5.13 shows the ALU control lines and the corresponding
ALU operation.
again!
Operation
Bnegate
Ainvert
If (A - B = 0) --> A = B
Zero Detection Logic is just
one BIG NOR gate (for
equality test)
Any non-zero input to the
NOR gate will cause its
output to be zero
a0
b0
CarryIn
ALU0
Less
CarryOut
a1
b1
0
CarryIn
ALU1
Less
CarryOut
CarryIn
ALU2
Less
CarryOut
a2
b2
0
..
.
.
..
. .. ..
.
a31
b31
0
Result0
Result1
..
.
Result2
..
. CarryIn
CarryIn
ALU31
Less
..
.
..
.
Result31
Set
FIGURE B.5.12 The final 32-bit ALU. This adds a Zero detector to Figure B.5.11.
Zero
Overflow
Full ALU
what signals accomplish:
Binvert CIn Oper
add?
sub?
and?
or?
beq?
slt?
C.5 Constructing a Basic A
ALU operation
a
Zero
ALU
Result
Overflow
CarryOut
FIGURE C.5.14 The symbol commonly used to represent an ALU,

C.5.12. This symbol is also used to represent an adder, so it is normally labeled eit
Full ALU
Binvert CIn Oper
0
0
2
add?
sub?
and?
or?
beq?
slt?
ALU operation
a
Zero
ALU
Result
Overflow
CarryOut

Full ALU
Binvert CIn Oper
0
0
2
add?
1
1
2
sub?
and?
or?
beq?
slt?
ALU operation
a
Zero
ALU
Result
Overflow
CarryOut

Full ALU
Binvert CIn Oper
0
0
2
add?
1
1
2
sub?
0
0
0
and?
or?
beq?
slt?
ALU operation
a
Zero
ALU
Result
Overflow
CarryOut

Full ALU
Binvert CIn Oper
0
0
2
add?
1
1
2
sub?
0
0
0
and?
0
0
1
or?
beq?
slt?
ALU operation
a
Zero
ALU
Result
Overflow
CarryOut

Full ALU
Binvert CIn Oper
0
0
2
add?
1
1
2
sub?
0
0
0
and?
0
0
1
or?
1
1
2
beq?
slt?
ALU operation
a
Zero
ALU
Result
Overflow
CarryOut

Full ALU
Binvert CIn Oper
0
0
2
add?
1
1
2
sub?
0
0
0
and?
0
0
1
or?
1
1
2
beq?
1
1
3
slt?
ALU operation
a
Zero
ALU
Result
Overflow
CarryOut

f a b CarryIn is true, then all of the other three terms must also be true, so we
an leave out this last term corresponding to the fourth line of the table. We can
hus simplify the equation to
CarryOut = (b CarryIn) + (a CarryIn) + (a b)
The Disadvantage of Ripple Carry
igure C.5.5 shows that the hardware within the adder black box for CarryOut
onsists of three AND gates and one OR gate. The three AND gates correspond
xactly to the three parenthesized terms of the formula above for CarryOut, and
he OR gate sums the three terms.
The adder we just built is called a

Ripple
Carry Adder
Inputs
a
0
1
1
1
CarryIn
The
carry1bit may have to
1
0
1
propagate
from LSB to MSB
1
0
Worst
delay
foris an
IGURE C.5.4 Values
of thecase
inputs when
CarryOut
a 1. N-bit
RC adder: 2N-gate delay
CarryIn0
A0
B0
A1
B1
CarryIn
A2
B2
A3
B3
CarryOut
IGURE C.5.5 Adder hardware for the CarryOut signal. The rest of the adder hardware is the logic
or the Sum output given in the equation on this page.
1-bit
Result0
ALU
CarryIn1 CarryOut0
1-bit
Result1
ALU
CarryIn2 CarryOut1
1-bit
Result2
ALU
CarryIn3 CarryOut2
1-bit
ALU
CarryOut3
Result3
f a b CarryIn is true, then all of the other three terms must also be true, so we
an leave out this last term corresponding to the fourth line of the table. We can
hus simplify the equation to
CarryOut = (b CarryIn) + (a CarryIn) + (a b)
The Disadvantage of Ripple Carry
igure C.5.5 shows that the hardware within the adder black box for CarryOut
onsists of three AND gates and one OR gate. The three AND gates correspond
xactly to the three parenthesized terms of the formula above for CarryOut, and
he OR gate sums the three terms.
The adder we just built is called a

Ripple
Carry Adder
Inputs
a
0
1
1
1
CarryIn
The
carry1bit may have to
1
0
1
propagate
from LSB to MSB
1
0
Worst
delay
foris an
IGURE C.5.4 Values
of thecase
inputs when
CarryOut
a 1. N-bit
RC adder: 2N-gate delay
CarryIn0
A0
B0
A1
B1
CarryIn
A2
B2
1-bit
Result0
ALU
CarryIn1 CarryOut0
1-bit
Result1
ALU
CarryIn2 CarryOut1
1-bit
Result2
ALU
CarryIn3 CarryOut2
A3
B3
CarryOut
IGURE C.5.5 Adder hardware for the CarryOut signal. The rest of the adder hardware is the logic
or the Sum output given in the equation on this page.
Faster Adders Possible: See C.6
1-bit
ALU
CarryOut3
Result3
Teaser!! The ALU in Perspective
Single Cycle CPU Next Time!!


04 MathALU

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