Questa Advanced Simulator

Questa's core simulation and debug engine

The Questa Advanced Simulator combines high performance and capacity simulation with
unified advanced debug capabilities for the most complete native support of Verilog,
SystemVerilog, VHDL, SystemC, PSL and UPF. The Questa Advanced Simulator is the core
simulation and debug engine of the Questa Verification Platform; the comprehensive advanced
verification platform capable of reducing the risk of validating complex FPGA and SoC designs.
Features

High Performance and Capacity

Assertion Based Verification
Test Automation
Questa Verification Management
Integrated Multi-Language Debugging
Power Aware Verification

Precision RTL
Precision RTL is Mentor Graphics entry-level FPGA synthesis solution offering excellent
quality of results and part of Mentor Graphics comprehensive FPGA vendor independent
solution.
With a rich feature set that includes advanced optimizations, award-winning analysis, and
industry-leading language support, Precision RTL enables vendor-independent design,
accelerates time to market, eliminates design defects, and delivers superior quality of results.
Key Features & Benefits
FPGA Vendor Independent Synthesis

Support for Actel, Altera, Lattice, and Xilinx

OEM support for Abound Logic, Achronix, Atmel, QuickLogic, and TierLogic
Same HDL and constraints for all devices

Excellent Quality of Results

Meet performance and area goals quickly

Advanced timing-driven optimizations
Technology inference for multiple vendors

Award-Winning-Analysis

RTL and gate-level technology schematics

Interactive static-timing engine to perform"what-if" timing analysis

Industry Leading Language Support

Supports any combination of Verilog, VHDL, SystemVerilog, and EDIF formats

Supports Synopsys Design Constraints

Precise-IP

Generate building block IP for any device

Leverage 3rd party IP validated for Precision

Integration with Mentor Tools

C synthesis with Catapult C

Design Reuse with HDL Designer
Equivalence Checking with FormalPro

ASIC Prototyping Support

Eases ASIC-to-FPGA migration

Automatic gated clock conversion
Conversion of DesignWare instances
Support for ASIC timing constraints (SDC)

Leonardo Spectrum
LeonardoSpectrum offers customers a well-proven, mature synthesis solution for both
FPGAs and ASICs.
Features and Benefits

One tool for CPLDs, FPGAs, ASICs

Supports current FPGA & ASIC families
Platform and device-independent
High quality of results for large designs

Controllable synthesis algorithms

Schematics to accelerate analysis
Hierarchical support to enable partitioning across multiple devices

HDL Designer
Visualizing Complex RTL Designs
HDL Designer combines deep analysis capabilities, advanced creation editors, and complete
project and flow management, to deliver a powerful HDL design environment that increases the
productivity of individual engineers and teams (local or remote) and enables a repeatable and
predictable design process.

Analyze
HDL Designer assists engineers in analyzing, assessing, and visualizing complex RTL designs,
providing code integrity analysis, connectivity completeness analysis, HDL code quality
assessment, and design visualization.
Create
Hand-in-hand with code analysis is code creation. HDL Designer provides engineers with a suite
of advanced design editors to facilitate development: interface-based design spreadsheet editor
(IBD) and block diagram, state-machine, truth table, flow chart and algorithmic state-machine
editors. To complement these editors, HDL Designer includes an EMACS/vi-compatible, HDLaware text editor.
Manage
In conjunction with design analysis and creation, design management is the third important task
facing designers. Along with managing the design data, teams need to manage the project
throughout the design flow. HDL Designer tackles the design management problem by providing
the designer with interfaces to other design tools within the flow; data and version management
solutions. HDL Designer also enables easy design and complete project documentation via
HTML, OLE, print, and graphics export.

Features
Highlights

Manages complex ASIC or FPGA designs in VHDL, Verilog and SystemVerilog

Accelerates RTL reuse
Extensive design checking rules and rulesets
Interactive HDL visualization and creation tools
Automatic documentation features and reporting
Intelligent debug and analysis
Concurrent design entry and checking

Design & Reuse

Quickly assess reused code quality and increase design understanding

Efficiently create RTL designs using text, tables, and graphics
Interactively manage design flow and all project data
Rapidly produce documentation
Accelerate IP repository population

SystemVerilog

Manage and understand code relationships

Accelerate language proficiency and results
Summarize and quantify code characteristics
Automate and simplify data management
Design, measure and document for practical code reuse

ReqTracer
Managing Requirements in Your Design Flow
ReqTracer manages requirements in your FPGA and ASIC design flows. ReqTracer simplifies,
automates and enables requirements traceability from specification of the hardware specification
through HDL coding, implementation and validation.
Benefits and Features

Interactive requirements tracing and analysis tool

Enables traceability of design requirements from source all the way to the details of the
design implementation and verification results

Interfaces to key Mentor design tools such and Questa, HDL Designer and Certe
Testbench Studio
Links design and verification data into requirements-aware relationships
Confirms all design requirements have been implemented and fully tested
ReqTracer assists in linking requirements to design source and verification results. A
variety of analysis and report generation can be done using the linked relationships
between requirements, design and test data.
Unique ability to link together diverse data in a variety of formats bridging the traditional
gap between requirements tools, design tools and test tools
ReqTracer has advanced interfaces with key Mentor hardware design tools allowing
access to data in a requirements-aware context.