Department Electrical and Electronics Engineering

EE 6502 Microprocessors and

Microcontrollers
1.

In 8085 name the 16 bit registers?

a) Stack pointer
b) Program counter
c) a & b

2.

Which interrupt has the highest priority?

a) INTR
b) TRAP
c) RST6.5

3.

What are level Triggering interrupts?

a) INTR&TRAP
b)RST6.5&RST5.5
c)RST7.5&RST6.5

4.

Why 8085 processor is called an 8 bit processor?

a) Because 8085 processor has 8 bit ALU.
b) Because 8085 processor has 8 bit data bus.
c) a & b.

5.

What is SIM?
a) Select Interrupt Mask
b) Sorting Interrupt Mask
c) Set Interrupt Mask

6.

What does microprocessor speed depends on?

NPR College of Engineering and Technology, Natham-624 401

Department Electrical and Electronics Engineering

a) Clock
b) Data bus width
c) Address bus width
7.

Can ROM be used as stack?

a) Yes
b) No
c) sometimes yes, sometimes no

8.

Which processor structure is pipelined?

a) all x80 processors
b) all x85 processors
c) all x86 processors

9.

In 8086 the overflow flag is set when

a) The sum is more than 16 bits
b) Signed numbers go out of their range after an arithmetic operation
c) Carry and sign flags are set
d) During subtraction

10.

The advantage of memory mapped I/O over I/O mapped I/O is,
a) Faster
b) Many instructions supporting memory mapped I/O
c) Require a bigger address decoder
d) All the above

11.

BHE of 8086 microprocessor signal is used to interface the

NPR College of Engineering and Technology, Natham-624 401

Department Electrical and Electronics Engineering

a) Even bank memory
b) Odd bank memory
c) I/O
d) DMA
12.

In 8086 microprocessor the following has the highest priority among all type interrupts.
a) NMI
b) DIV 0
c) TYPE 255
d) OVER FLOW

13.

What is meant by Maskable interrupts?

a) An interrupt which can never be turned off.
b) An interrupt that can be turned off by the programmer.
c) none

14.

Access time is faster for

a) ROM
b) SRAM
c)DRAM
d) EPROM

15.

Which stack in 8085?

a)FIFO
b)LIFO
c)FILO
d)LILO

16.

A microprocessor is a _______ chip integrating all the functions of a CPU of a computer.

a) multiple
b) single
c) double

NPR College of Engineering and Technology, Natham-624 401

Department Electrical and Electronics Engineering

d) triple
17.

The intel 8086 microprocessor is a _______ processor

a) 8 bit
b) 16 bit
c) 32 bit
d) 4 bit

18.

The flag of microprocessor is responsible to indicate ___________

a) the condition of result of ALU operation
b) the condition of memory
c) the result of addition
d the result of subtraction

18.

In which T-state does the CPU sends the address to memory or I/O and the ALE signal
for demultiplexing
a) T1.
b) T2.
c) T3.
d) T4.

19.

The register that may be used as an operand register is

a) Accumulator
b) B register
c) Data register
d) Accumulator and B register

20.

The registers that contains the status information is

a) control registers
b) instruction registers
c) program status word
d) all of the mentioned

21.

The logic required for implementing a program can be expressed in terms of

a) flowchart
b) algorithm
c) flowchart & algorithm

NPR College of Engineering and Technology, Natham-624 401

Department Electrical and Electronics Engineering

d) none of the mentioned
22.

The operands, source and destination in an instruction cannot be

a) register, register
b) memory location, memory location
c) memory location, register
d) immediate data, register

23.

The instruction that is not possible among the following is

a) MOV AX, BX
b) MOV AX, [BX]
c) MOV 55H, BL
d) MOV AL, 55H

24.

The registers that cannot be used as operands for arithmetic and logical instructions are
a) general purpose registers
b) pointers
c) index registers
d) segment registers

25.

The instruction, MOV AX, 0005H belongs to the address mode

a) register
b) direct
c) immediate
d) register relative

26.

If the data is present in a register and it is referred using the particular register, then it is
a) direct addressing mode
b) register addressing mode
c) indexed addressing mode
d) immediate addressing mode

27.

The instruction that is used to transfer the data from source operand to destination operand is
a) data copy/transfer instruction
b) branch instruction
c) arithmetic/logical instruction
d) string instruction

28.

The instructions that involve various string manipulation operations are

a) branch instructions
b) flag manipulation instructions
c) shift and rotate instructions
d) string instructions

NPR College of Engineering and Technology, Natham-624 401

Department Electrical and Electronics Engineering

29.

In PUSH instruction, after each execution of the instruction, the stack pointer is
a) incremented by 1
b) decremented by 1
c) incremented by 2
d) decremented by 2

30.

The instructions that are used for reading an input port and writing an output port respectively are
a) MOV, XCHG
b) MOV, IN
c) IN, MOV
d) IN, OUT

31

The instruction that supports addition when carry exists is

a) ADD
b) ADC
c) ADD & ADC
d) none of the mentioned

32.

What is the output of the following code

CF =0, BH = 179
RCL BH, 1
a) CF=0, OF= 1, BH= 01100101
b) CF=1, OF=1, BH=01100110
c) CF=1, OF =0, BH= 01001101
d) CF=0, OF=0, BH=00101100

33.

In 8086 microprocessor one of the following instructions is executed before an

arithmetic operation
a) AAM
b) AAD
c) DAS
d) DAA

34.

What is the output of the following code

AL= 49 BCD, BH= 72 BCD

NPR College of Engineering and Technology, Natham-624 401

Department Electrical and Electronics Engineering

SUB AL, BH
DAS
a) AL=D7, CF=1.
b) AL=7D, CF=1.
c) AL=77, CF=1
d) none of them.
35.

The instruction, INC increases the contents of the specified register or memory location by
a) 2
b) 0
c) 1
d) 3

36.

The instruction, CMP to compare source and destination operands it performs

a) addition
b) subtraction
c) division
d) multiplication

37.

The expansion of DAA is

a) decimal adjust after addition
b) decimal adjust before addition
c) decimal adjust accumulator
d) decimal adjust auxiliary

38.

Number of the times the instruction sequence below will loop before coming out of
loop is MOV AL, 00h
A1: INC AL
JNZ A1
a) 00
b) 01
c) 255
d) 256

39.

What will be the contents of register AL after the following has been executed

NPR College of Engineering and Technology, Natham-624 401

Department Electrical and Electronics Engineering

MOV BL, 8C
MOV AL, 7E
ADD AL, BL
a) 0A and carry flag is set
b) 0A and carry flag is reset
c) 6A and carry flag is set
d) 6A and carry flag is reset
40.

Pseudo instructions are basically

a) false instructions.
b) instructions that are ignored by the microprocessor.
c) assembler directives.
d) instructions that are treated like comments.

41.

The 8051 microcontroller is of ___pin package as a ______ processor.

a) 30, 1byte
b) 20, 1 byte
c) 40, 8 bit
d) 40, 8 byte

42.

What is the address range of SFR Register bank?

a) 00H-77H
b) 40H-80H
c) 80H-7FH
d) 80H-FFH

43.

Match the following:

1) TCON i) contains status information
2) SBUF ii) timer / counter control register.
3) TMOD iii) idle bit, power down bit

NPR College of Engineering and Technology, Natham-624 401

Department Electrical and Electronics Engineering

4) PSW iv) serial data buffer for Tx and Rx.
5) PCON v) timer/ counter modes of operation.
a) 1->ii, 2->iv, 3->v, 4->i, 5->iii.
b) 1->i, 2->v, 3->iv, 4->iii, 5->ii.
c) 1->v, 2->iii, 3->ii, 4->iv, 5->i.
d) 1->iii, 2->ii, 3->i, 4->v, 5->iv.
44.

In 8051 which interrupt has highest priority?

a)IE1
b)TF0
c)IE0
d)TF1

45.

Serial port interrupt is generated, if ____ bits are set

a) IE
b) RI, IE
c) IP, TI
d) RI, TI

46.

The transmit buffer of serial data buffer is a

a) serial-in parallel-out register
b) parallel-in serial-out register
c) serial-in serial-out register
d) parallel-in parallel-out register

47.

The registers that are not accessible by the user are

a) Accumulator and B register
b) IP and IE
c) instruction registers
d) TMP1 and TMP2

48.

The higher and lower bytes of a 16-bit register DPTR are represented respectively as
a) LDPTR and HDPTR
b) DPTRL and DPTRH
c) DPH and DPL
d) HDP and LDP

NPR College of Engineering and Technology, Natham-624 401

Department Electrical and Electronics Engineering

49.

Among the four groups of register banks, the number of groups that can be accessed at a time is
a) 1
b) 2
c) 3
d) all the four

50.

In idle mode, the device that is disabled is

a) serial port
b) timer block
c) clock to CPU
d) all of the mentioned

51.

The only way to terminate the power down mode is to

a) CLEAR
b) RESET
c) HOLD
d) HLT

52.

Which of the following is an external interrupt?

a) INT0(active low)
b) INT2(active low)
c) Timer0 interrupt
d) Timer1 interrupt

53.

If the external interrupt sources control the flags IE0 and IE1, then the interrupt programmed is
a) level-sensitive
b) edge-sensitive
c) in serial port
d) in parallel port

54.

In timer mode, the oscillator clock is divided by a prescalar

a) (1/8)
b) (1/4)
c) (1/16)
d) (1/32)

55.

The external interrupt that has the lowest priority among the following is
a) TF0
b) TF1
c) IE1
d) NONE

56.

All the interrupts are enabled using a special function register called

NPR College of Engineering and Technology, Natham-624 401

Department Electrical and Electronics Engineering

a) interrupt priority register
b) interrupt register
c) interrupt function register
d) interrupt enable register
57.

The step involved in PUSH operation is

a) increment stack by 2 and store 8-bit content to address pointed to by SP
b) decrement stack by 1 and store 16-bit content to address pointed to by SP
c) increment stack by 1 and store 8-bit content to address pointed to by SP
d) store 8-bit content to address pointed to by SP and then increment stack by 1

58.

The 8051 stack is

a) auto-decrement during PUSH operations
b) auto-increment during POP operations
c) auto-decrement during POP operations
d) auto-increment during PUSH operations

59.

After reset, the stack pointer(SP) is initialized to the address of

a) internal ROM
b) internal RAM
c) external ROM
d) external RAM

60.

The PCON register consists of

a) power mode bit
b) power idle bit
c) power ideal bit
d) power down bit and idle bit

61.

The example of output device is

a) CRT display
b) 7-segment display
c) printer
d) all of the mentioned

62.

The chip 74LS245 is

a) bidirectional buffer
b) 8-bit input port
c) one that has 8 buffers
d) all of the mentioned

63.

The latch or IC 74LS373 acts as

a) good input port
b) bad input port

NPR College of Engineering and Technology, Natham-624 401

Department Electrical and Electronics Engineering

c) good output port
d) bad output port
64.

Programmable peripheral input-output port is other name for

a) serial input-output port
b) parallel input-output port
c) serial input port
d) parallel output port

65.

All the functions of the ports of 8255 are achieved by programming the bits of an internal register
called
a) data bus control
b) read logic control
c) control word register
d) none

66.

The data bus buffer is controlled by

a) control word register
b) read/write control logic
c) data bus
d) none

67.

In BSR mode, only port C can be used to

a) set individual ports
b) reset individual ports
c) set and reset individual ports
d) programmable I/O ports

68.

The time taken by the ADC from the active edge of SOC(start of conversion) pulse till the active
edge of EOC(end of conversion) signal is called
a) edge time
b) conversion time
c) conversion delay
d) time delay

69.

The number of inputs that can be connected at a time to an ADC that is integrated with successive
approximation is
a) 4
b) 2
c) 8
d) 16

70.

Which of the following is not a mode of data transmission?

a) simplex
b) duplex
c) semi duplex

NPR College of Engineering and Technology, Natham-624 401

Department Electrical and Electronics Engineering

d) half duplex
71.

In 8251A, the pin that controls the rate at which the character is to be transmitted is
a) TXC(active low)
b) TXC(active high)
c) TXD(active low)
d) RXC(active low)

72.

The disadvantage of RS-232C is

a) limited speed of communication
b) high-voltage level signaling
c) big-size communication adapters
d) all of the mentioned

73.

The mode that is used to interrupt the processor by setting a suitable terminal count is
a) mode 0
b) mode 1
c) mode 2
d) mode 3

74.

In control word format, if RL1=1, RL0=1 then the operation performed is

a) read/load least significant byte only
b) read/load most significant byte only
c) read/load LSB first and then MSB
d) read/load MSB first and then LSB

75.

The counter starts counting only if

a) GATE signal is low
b) GATE signal is high
c) CLK signal is low
d) CLK signal is high

76.

The register that stores the bits required to mask the interrupt inputs is
a) In-service register
b) Priority resolver
c) Interrupt Mask register
d) none

77.

In cascaded mode, the number of vectored interrupts provided by 8259A is

a) 4
b) 8
c) 16
d) 64

78.

The sensor RAM acts as 8-byte first-in-first-out RAM in

NPR College of Engineering and Technology, Natham-624 401

Department Electrical and Electronics Engineering

a) keyboard mode
b) strobed input mode
c) keyboard and strobed input mode
d) scanned sensor matrix mode
79.

When a key is pressed, a debounce logic comes into operation in

a) scanned keyboard special error mode
b) scanned keyboard with N-key rollover
c) scanned keyboard mode with 2 key lockout
d) sensor matrix mode

80.

In 8257 (DMA), each of the four channels has

a) a pair of two 8-bit registers
b) a pair of two 16-bit registers
c) one 16-bit register
d) one 8-bit register

81.

The symbol, addr 16 represents the 16-bit address which is used by the instructions to specify the
a) destination address of CALL
b) source address of JUMP
c) destination address of call or jump
d) source address of call or jump

82.

The storage of addresses that can be directly accessed is

a) external data RAM
b) internal data ROM
c) internal data RAM and SFRS
d) external data ROM and SFRS

83.

The address register for storing the 8-bit addresses can be

a) R0 of selected bank of register
b) R1 of selected bank of register
c) stack pointer
d) all of the mentioned

84.

The instruction, ADD A, #100 performs

a) 100(decimal) is added to contents of address register
b) 100(decimal) is subtracted from accumulator
c) 100(decimal) is added to contents of accumulator
d) none

85.

The data address of look-up table is found by adding the contents of

a) accumulator with that of program counter
b) accumulator with that of program counter or data pointer
c) data register with that of program counter or accumulator
d) data register with that of program counter or data pointer

86.

Which of the following is true while executing data transfer instructions?

a) program counter is not accessible

NPR College of Engineering and Technology, Natham-624 401

Department Electrical and Electronics Engineering

b) restricted bit-transfer operations are allowed
c) both operands can be direct/indirect register operands
d) all of the mentioned
87.

The instruction that is used to complement or invert the bit of a bit addressable SFR is
a) CLR C
b) CPL C
c) CPL Bit
d) ANL Bit

88.

The instructions that change the sequence of execution are

a) conditional instructions
b) logical instructions
c) control transfer instructions
d) data transfer instructions

89.

The first byte of an absolute jump instruction consists of

a) 3 LSBs of opcode and 5 MSBs of 11-bit address
b) 5 MSBs of opcode and 3 LSBs of 11-bit address
c) 6 MSBs of opcode and 1 LSB of 11-bit address
d) 5 LSBs of opcode and 3 MSBs of 11-bit address

90.

The third byte of the long jump instruction is

a) opcode
b) 5 LSBs of opcode
c) higher byte of jump location or subroutine
d) lower byte of jump location or subroutine

91.

A stepper motor has a step-angle of 2.5. Determine the resolution?

a) 140.
b) 143.
c) 144.

92.

d) 145.
Which special type of motor has rotor movements in discrete steps?
a) Stepper motor.
b) Reluctance motor.
c) Servomotors.
d) Hysteresis motor.

93.

In cloth washing machines and refrigerators which motors are preferred?

NPR College of Engineering and Technology, Natham-624 401

Department Electrical and Electronics Engineering

a) DC cumulative compound motors.
b) Slip ring IM.
c) Universal motors.
d ) Stepper motor.
94.

Which is true in interfacing 7 segment code display?

a) transmitted by second port
b) display is selected by third port
c) display is selected by second port
d) none of the mentioned

95.

To convert its current output into voltage, the DAC 0808 is connected with
a) transistor(BJT) externally
b) FET externally
c) OPAMP externally
d) OPAMP internally

96.

For deriving chip selects of isolated memory or IO devices, the gates that are traditionally used are
a) NOR and NAND
b) NAND and NOT
c) NOT and NOR
d) AND, OR and NOT

97.

The current that is required for a LED for an appropriate glow is

a) 6-8 mA
b) 4-6 mA
c) 8-10 mA
d) 10-12 mA

98.

The step that is involved in the procedure of memory interfacing with 8051 is
a) data bus is connected to data lines of memory chips
b) PSEN(active low) is connected to OE(active low) of EPROM chips
c) writing address map of memory chip in bit form
d) all of the mentioned

99.

Which system needs more stability

a) Automatic washing machine
b) Traffic signal system
c) Home heating system
d) None of the above

100.

How many rows and columns are present in a 16*2 alphanumeric LCD?

NPR College of Engineering and Technology, Natham-624 401

Department Electrical and Electronics Engineering

a) rows=2, columns=32
b) rows=16, columns=2
c) rows=16, columns=16
d) rows=2, columns=16

NPR College of Engineering and Technology, Natham-624 401