TRNG I HC CN TH

KHOA CNG NGH

HDL PROJECT REPORT

VERILOG HDL SIMULATION

LABS
Group : 5
Instructor
L Hi Ton

Group Member :
1/ Nguyn B Quc Huy
2/ Nguyn L Khanh
3/ L Quc Huy
4/ Dng Vn oan
5/ Nguyn Tn Ti
6/ Nguyn Trung Nhn

HDL PROJECT REPORT

MSSV : B1306150
MSSV : B1306158
MSSV : B1306149
MSSV : B1306135
MSSV : B1306195
MSSV : B1306179

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TABLE OF CONTENT

Verilog HDL Simulation Labs ....Page 3

Lab 1 : Building Hierarchy .Page 4
Lab 2 : Simulation/Verification ..Page 7
Lab 3 : Memory Page 11
Lab 4 : n-bit binary counter Page 16
Lab 5 : Comparator .Page 22
Lab 6 :Arithmetic Logic Unit (ALU)..Page 26

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Verilog HDL Simulation Labs

Overview
The Verilog simulation labs in this course are designed to maximize your
hands on introduction to Verilog coding. Therefore, you are asked to
create all hardware modules and testbenches from scratch. After finishing
these labs, you will gain the level of coding skill, syntax proficiency, and
understanding that can only be achieved through meaningful practice and
effort.
Most of the early lab exercises are standalone tasks that reinforce and
illustrate language concepts that are fundamental to all Verilog coding.

Objectives
After completing these labs, you will be able to:
Write RTL descriptions for simple circuits
Create a structural Verilog description for simple circuits
Build hierarchy by using Verilog
Create a Verilog testbench to verify the hierarchical structure created in
the
previous steps
Use the simulation software
Create basic input stimulus
Run a simulation

Labs Outline
Lab 1: Building Hierarchy
Lab 2: Simulation/Verification
Lab 3: Memory
Lab 4: n-bit Binary Counter
Lab 5: Comparator
Lab 6: Arithmetic Logic Unit (ALU)

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Lab 1: Building Hierarchy

Request :
In this lab, you will write a complete RTL description for the modules
MY_AND2 and MY_OR2 and build the circuit shown below (Figure 1)
in a structural Verilog description of the top-level module AND_OR

This lab comprises three primary steps: You will create a software
project; write RTL descriptions; and check the syntax of your RTL code.

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Verilog Code:

// This is module AND_OR in Labs 1

// Design name : AND_OR
// File name
: AND_OR.v
// Coder
: Nhom 5
module AND_OR(
INP,
OUT1
);
input [3:0] INP;
output OUT1;
wire sig1, sig2;
and U0(sig1,INP[0],INP[1]);
and U1(sig2,INP[2],INP[3]);
or U3(OUT1,sig1,sig2);
endmodule

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Synthesis output:

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Lab 2: Simulation/Verification
Request :
In this lab, you will write a Verilog testbench for the AND_OR module
completed in the previous exercise. As part of the testbench, you will
create a simple input stimulus by using both concurrent and sequential
statements.
Examine the circuit below (Figure 2). In this lab, you will write a
complete Verilog testbench description for the module AND_OR.

This lab comprises four primary steps: You will create a new project and
import Verilog source files; create a testbench with the Verilog testbench
wizard in the simulation software; create initial and always input stimulus
statements; and, finally, verify the logic structure and functionality by
running a simulation and examining the resulting waveforms.

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Verilog code:

module AND_OR_TB();
reg [3:0] inp_tb;
wire out_view;
initial
#10
#10
#10
#10
end

begin
inp_tb
inp_tb
inp_tb
inp_tb

=
=
=
=

4'b0000;
4'b1111;
4'b0011;
4'b0000;

always begin
#10 inp_tb = inp_tb + 1;
end
initial begin
$monitor("INP = %b , OUT = %d " ,
inp_tb,out_view);
#300 $stop;
end
AND_OR U_test( inp_tb , out_view);
endmodule

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Simulation Result:

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Waveforms:

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Lab 3: Memory (ROM)

Request :
In this lab, you will write a complete RTL description for a ROM module
by using a one-dimensional array and a Verilog reg data type and a case
statement.

The memory was modeled as a ROM, which is a constant; therefore, you

were required to assign values at the time of declaration.
This lab comprises three primary steps: You will create a one dimensional
memory array using case statement; create a testbench with the Verilog
testbench wizard in the simulation software; finally, verify the logic
structure and functionality by running a simulation and examining the
resulting waveforms.

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Verilog Code:
//
This is a ROM module by using a
one-dimensional array
//
and a Verilog reg data type and a
case statement.
//File
: rom_case.v
//Coder
: Nhom 5
module rom_case(
address
,
read_en
,
clk
,
data
);
input [3:0] address;
input read_en;
input clk;
output [7:0] data;
reg [7:0] data;
always @(posedge clk, read_en) begin
if (read_en == 0) data = 0'bzzzzzzzz;
else
case (address)
0: data = 8'b1111_1110;
1: data = 8'b1111_1101;
2: data = 8'b1111_1011;
3: data = 8'b1111_0111;
4: data = 8'b1110_1111;
5: data = 8'b1101_1111;
6: data = 8'b1011_1111;
7: data = 8'b0111_1111;
8: data = 8'b0000_1000;
9: data = 8'b0000_1001;
default: data = 8'bzzzz_zzzz;
endcase
end
endmodule

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Testbench:

module rom_case_tb();
reg [3:0] address_tb;
reg clk, read_en_tb;
wire [7:0] data_tb;
initial begin
$monitor("Address = %b , read_en
= %d , data = %b",
address_tb,
read_en_tb,
data_tb
);
#200 $stop
;
end
initial begin
clk = 0;
read_en_tb = 0;
#20 read_en_tb = 1;
#10 address_tb = 8;
#10 address_tb = 0;
repeat (16) #10 address_tb =
address_tb + 1;
end
always #5 clk = !clk;
rom_case ROM_version1 (
.address (address_tb)
.clk
(clk)
.read_en (read_en_tb)
.data
(data_tb)
);
endmodule

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,
,
,

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Simulation result:

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Waveforms
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Lab 4 Counter
Request :
In this lab, you will write a complete RTL description for the module
CNTR by using parameter statements to specify the bit width. This is an
n-bit binary, up/down, loadable counter, with active-Low asynchronous
reset. You will then build a Verilog HDL testbench to verify the
functionality of the RTL code as well as the hardware it models.
Examine the circuit below (Figure 3). In this exercise, you will create a
fully functional binary counter that can be dynamically scaled to any
length. The use of parameter statements is an important tool for module
reuse and source code readability. The circuit is an n-bit binary, up/down
loadable counter, with active- Low asynchronous reset.

This lab comprises three primary steps: You will create a software project; declare
the parameter statements; and, finally, create a testbench to verify the design.
Create the input stimulus:
1. Set the CLOCK input to toggle at a rate of 100 MHz
2. Assert the RESET input at time 15 ns, hold for 25 ns, then de-assert
3. Set the CE input initially High, de-assert (set Low) at time 300, hold for 100 ns,
reassert
4. Set the LOAD input initially Low, toggle High at time 500 ns, for one full clock
cycle
5. Set UPDN to initially High, then Low at time 750 ns
7. Set the D_IN input value to 8h0F or 8b00001111
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Verilog Code:
// This is an n-bit binary, up/down, loadable
counter,
// with active-low asynchronous reset
// Coder: Nhom 5
module CNTR(
d_in,
ce,
load,
updn,
clk,
rst,
q_out
);
parameter n = 4;
input
input
input
input
input
input

[n-1:0] d_in;
ce;
load;
updn;
clk;
rst;

output [n-1:0] q_out;

reg [n-1:0] q_o;
initial q_o = 0;
always @(posedge clk) begin
if
(rst == 1'b0) q_o = 1'b0;
//Reset ve 0
else if (ce == 1)
if
(load == 1) q_o = d_in;
//Load dl tu d_in
else if (updn == 1) q_o = q_o
+1; //Dem len
else
q_o = q_o
-1; //Dem xuong
else
q_o = q_o;
end
assign q_out = (ce)? q_o : 16'bz;
//n<=16,
n>16 mach ko dung
endmodule
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Testbench
// This is an testbench for 8-bit binary, up/down, loadable
counter,
// with active-low asynchronous reset
// Coder: Nhom 5
module CNTR_TB ();
reg [7:0] d_in_tb;
reg clk_tb;
reg ce_tb;
reg load_tb;
reg rst_tb;
reg updn_tb;
wire [7:0] q_out_tb;
always #10 clk_tb = !clk_tb;
initial fork
clk_tb = 0;
begin
time 15 ns
#15 rst_tb = 0;
assert
#25 rst_tb = 1;
end
ce_tb = 1;
begin
#300 ce_tb = 0;
#100 ce_tb = 1;
end
load_tb = 0;
begin
#500 load_tb = 1;
#20 load_tb = 0;
end
updn_tb = 1;
#750 updn_tb = 0;
d_in_tb = 8'h0F;
join

//Assert the Reset input at

//hold for 25 ns, then de-

//Chip enable initially is High

//set Low at the time 300,
//hold for 100 ns, reassert
//Load initially Low,
//toggle High at time 500ns
//full clock cycle

CNTR #(8) my_counter(

.d_in
(d_in_tb) ,
.clk
(clk_tb),
.ce
(ce_tb),
.load
(load_tb),
.updn
(updn_tb),
.rst
(rst_tb),
.q_out (q_out_tb));
endmodule

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Waveforms:
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Lab 5 Comparator
Request :
In this lab, you will write description for the module COMP
(Synchronous Comparator) using an if/else statement.
Examine the circuit below (Figure 4):

This lab comprises four primary steps: You will create a software project;
create an RTL version of COMP; and, finally, create a testbench to verify
that the behavioral model functions correctly.
If the expected result and the data are equal, the result is TRUE;
otherwise, the result is FALSE.
Declarations of input and output are shown in the following table:

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Verilog code:

// Module name
// File
// Coder

:
:
:

comp
comp.v
Nhom 5

module comp(
expected,
data,
enable,
clk,
result);
input [3:0] expected;
input [3:0] data;
input clk;
input enable;
output result;
reg result;
initial result = 1'bz;
always @(posedge clk)
if (enable)
if (expected == data)
result = 1'b1;
else
result = 1'b0;
else result = 1'bz;
endmodule

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Testbench:
//Module name :
comp_tb
//
-> comparator testbench
//File name
:
comp_tb.v
//Coder
:
Nhom 5
module comp_tb();
reg [3:0] expected ;
reg clk;
reg enable;
reg [3:0] data;
wire result;
initial begin
clk = 0;
data = 0;
expected =0;
end
initial begin
#10 enable = 0;
#5 enable = 1;
#5 data
= 1;
#10 data
= 1;
expected = 1;
#5 expected = 0;
#10 data
= 5;
expected = 4;
#5 expected = 5;
end
always #5 clk = !clk;
comp compare1(
.expected (expected),
.clk
(clk),
.enable
(enable),
.data
(data),
.result
(result)
);
endmodule

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Waveform

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Lab 6 Arithmetic Logic Unit (ALU)

Request :
In this lab, you will write a complete RTL description for the module
ALU. The op-codes and functionality of the synchronous ALU is
described below.

Use a case statement to describe the functionality for the ALU as shown
in the following table, which shows the SELECTION OPCODE and the
operation/function for each. Do not forget the ENABLE input.

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Verilog Code:
// Module name
// File name
// Coder

: alu
: alu.v
: Nhom 5

module alu(
a_in,
b_in,
opcode,
enable,
clk,
alu_out);
input [3:0] a_in
;
input [3:0] b_in
;
input [3:0] opcode;
input clk;
input enable;
output [3:0] alu_out;
reg [3:0] alu_out;
initial alu_out = 4'bzzzz;
always @(posedge clk)
if(enable == 1)
case(opcode)
4'b0000 : alu_out
4'b0001 : alu_out
4'b0010 : alu_out
4'b0011 : alu_out
4'b0100 : alu_out
4'b0101 : alu_out
4'b0110 : alu_out
4'b0111 : alu_out
4'b1000 : alu_out
4'b1001 : alu_out
4'b1010 : alu_out
4'b1011 : alu_out
default alu_out =
endcase
else alu_out = 4'bzzzz;
endmodule

HDL PROJECT REPORT

= a_in;
= a_in +1;
= a_in + b_in;
= a_in + b_in + 1;
= a_in + (~b_in);
= a_in + (~b_in) + 1;
= a_in - 1;
= a_in && b_in;
= a_in || b_in;
= a_in ^ b_in;
= ~a_in;
= 0;
4'bzzzz;
//enable == 0

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Testbench:
module alu_tb();
reg [3:0] a_in;
reg [3:0] b_in;
reg [3:0] opcode;
reg clk;
reg enable;
wire [3:0] alu_out;
always #5 clk = !clk;
initial begin
clk = 0;
a_in = 4'b0011;
#10
enable = 0;
#10
b_in = 4'b1001;
#10
opcode = 4'b0000;
#10
enable = 1;
repeat (16) #10 opcode = opcode + 1;
end
initial begin
$monitor("A = %b , B = %b, OPCODE = %b ,Enable = %b,
ALU_OUT = %b ",
a_in, b_in,opcode,enable,alu_out);
#2000 $stop;
end
alu My_alu(
.a_in (a_in),
.b_in (b_in),
.opcode (opcode),
.clk (clk),
.alu_out (alu_out),
.enable (enable)
);
endmodule

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Simulation Result:

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Waveforms:

Waveform :

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