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borattory Man
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VLSI De
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Fa
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2

Co
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S Syed
Sir
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Technolo
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Un
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http://w
www.ssuett.edu.pk

TABLE OF CONTENTS
Lab No.
1.
2.
3.
4.
5.

TITLE
Introduction to Xilinx ISE 13.4 + Basic Schematic Example
and Simulation
Combinational Logic Schematic Example and Simulation.
Sequential Logic Schematic Example and Simulation.
Introduction to Verilog Language, Gate Level Modeling and
Example.
Define expressions, operators, and operands. Use dataflow
constructs to model practical digital circuits in Verilog

PAGE No
1 - 32
33 - 39
40 - 50
51 - 59
60 - 67

6.

Introduction to behavioral modeling

68 - 77

7.

Hierarchal model

78 - 86

8.

Midterm 8th week

9.

To study the characteristics of logic gates delays and to

calculate and measure the output of logic gates delays

10.

State Machines

11.

Introduction to Virtex 5 Development System

12.

Lab Quiz

13.

Projects related to Virtex-5 Development System

14.

Projects related to Virtex-5 Development System

15.

Lab Viva

16.

Lab Viva

87 - 93
94 - 111
112 - 149

Lab1

LAB 1
OBJECTIVE:
This lab is designed to help you to become familiar with the operation of the WebPack software
by creating a simple Schematic design (half adder /full adder) and simulating it on the Xilinx
ISim simulator.

INTRODUCTION TO XILINX ISE WEB PACK SOFTWARE:

Introduction to Xilinx ISE Environment:
Design Flow
The typical design flow for designing the VLSI circuits is shown. This design flow is
typically used by the designers who use HDLs.

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Integrated Software Environment (ISE)

Xilinx Integrated Software Environment (ISE) is a powerful yet flexible integrated design
environment. It allows designing of Xilinx FPGA devices from start to finish. ISE enables us
to start our design with any of a number of different source types i.e. Verilog HDL, VHDL,
Schematic Design etc.

Design Flow in ISE

There are different ways to define our design in ISE. ISE Text Editor, Schematic Editor,
Core Generator, Constrains Editor, Pinout area Constraint Editor, State CAD editor, Test
Bench Waveform.

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Design Flow in ISE (Implementation)

Translate - The Translate process merge all of the input netlists as well as design constraint
information into a Xilinx database file. Map - The Map program maps a logical design to a
Xilinx FPGA. Place and Route (PAR) - The PAR program accepts the mapped design,
places and routes the FPGA, and produces output for the bit stream generator. Floor Planner The Floor Planner allows you to view a graphical representation of the FPGA, and to view
and modify the placed design. FPGA Editor - The FPGA Editor allows you view and modify
the physical implementation, including routing.

Starting the ISE Software

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Create New Project

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Project Name & Working Directory

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select spartan 3e starter board

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show the project summary

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Design and process directory

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Console Window

LAB TASK # 1:
Design and simulate a Half Adder schematic.

THEORY:
HALF ADDER:

sum carry

In electronics, an adder is a digital circuit that

performs addition of numbers. In many computers
and other kinds of processors, adders are used not
only in the arithmetic logic units, but also in other
parts of the processor, where they are used to
calculate addresses, table indices, and etc

Truth Table
Lets take the following steps:

1. ENTERING THE DESIGN

The software we will be using is the Xilinx "ISE Project Navigator", in which you can enter the
Schematic design and simulate its outputs for a specified sequence of inputs. To start up, go to
Start
All Programs
Navigator

Xilinx ISE Design Suite 13.4

ISE Design Tools

Project

The screen shown in Figure 1 appears.

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Lab1

Figure 1
At this point, you have not yet created any project so we will start here. A "project" is a set of
files, including schematic file that define the circuit components and overall circuit, along with
auxiliary files related to simulations and other parts of the design performed.
You can either click New Project or go to File -> New Project. This launches the New Project
Wizard as shown in Figure 2. Enter a project name and location.
We would suggest you create the project in the "My Documents" folder, rather than the default
(C:\ project_name) to avoid adding lots of new files into your main 2 directory. This will take
you to the Design Properties pop-up as shown in Figure 3.

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Figure 2

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Figure 3

In the Design Properties window, you can specify the Device Family and the Device.
This is needed when you reach the "synthesis" stage in the design and implementation since the
synthesis stage needs to know the internal design of the specific programmable device. When
you click OK, a Project Summary window will pop-up. Click Finish (figure 3a).

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Figure 3a
We are now ready to begin entering our schematic. From the Project Navigators pull-down
menus, select Project -> New Source. This launches the New Source Wizard as shown in
Figure 4.

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Figure 4
This window can be used to add a variety of sources to your design. Select "Schematic" and add
the name of your circuit. The box "Add to project" should be checked. The location should
appear as the directory you selected above. Click Next and the screen shown in Figure 5 appears.

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Figure 5

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Figure 6
The screen in Figure 6 allows you to enter the "Schematic" of half adder. Design the schematics by drag
drop the symbols of logic gates involve in schematic as shown in Figure 7.

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Figure 7
Save the file. Click on Design option at the bottom of the process window select your file and
expand the Design Utilities option. Click on Check Design Rules, if it will be correct a green
arrow will appear. Then click Create Schematic Symbol to make your schematic a symbol for
further use. Again a green arrow will appear. All this is shown in the left of figure 7.

2. SIMULATING THE CIRCUIT

Now that we have a design that has been checked for its syntax, we can now proceed to a
simulation of the circuit designed. In order to simulate the circuit, we first need a set of signals to
drive our inputs A and B. We do this by constructing a separate source file called a test fixture.
This code defines the signals and then applies them to the entity under test.

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Figure 8
First check the simulation tab in Design panel after that click from the Project Navigator
window Project -> New Source. The same New Source Wizard (Figure 8) appears that was
used earlier to enter our halfadder schematic. This time, instead of selecting Schematic, select
Verilog Test Fixture. Name the file halfadder_tf (to distinguish it from the actual halfadder.sch
file) and click Next. New windows will pop-up asking you which module describes the circuit
you want to test. There is only one choice halfadder as shown in figure 9. Select this module
and then click Next. The New Source Wizard now shows a summary page. Click Finish.

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Figure 9
Clicking on Finish, the Project Navigator screen reappears and you will see that the wizard has
already generated some Verilog code, for a new module called halfadder_tf as shown in Figure
10. There may be some compiler errors that appear in the console window. Ignore them because
we are going to edit this test fixture file. It is not necessary for you to understand the semantics
of this test fixture module at this stage. Simply make the following changes.

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modulehalfadder_tf;

//Inputs

regA;

regB;

//Outputs

wireSum;

wireCarry;

//InstantiatetheUnitUnderTest(UUT)

halfadderuut(

.A(A),

.B(B),

.Sum(Sum),

.Carry(Carry)

);

initialbegin

//InitializeInputs

A=0;

B=0;

//Wait100nsforglobalresettofinish

#100;

//Addstimulushere

#100A=0;B=1;

#100A=0;B=0;

#100A=1;B=1;

#100A=1;B=0;

end
endmodule

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Figure 10
Save the file. Select halfadder_tf in the Hierarchy window and then in process panel double click
on Behavioral Check Syntax to check for errors. Correct any error if there is, and then save it and
check again. Once, the errors are removed, right-click on Simulate Behavioral Model in process
panel and select Process Properties. This will generate the Isim Properties pop-up window as
shown in Figure 11. Set the Simulation Run Time to 200 ns and click OK.

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Figure 11
We are now ready to run the simulation. Double-click on Simulate Behavioral Model. This
brings up the ISim simulation window as shown in Figure 12. Waveforms are plotted in the top
right-hand window. Note that the simulator very conveniently plots the last 3ps of the
simulation! In order to see the whole simulation, click the Zoom to Full View icon in the tool-bar
immediately above the simulation window. The waveforms will now appear as shown in Figure
13. Check for correct functionality of the half adder. Note the timing delays as outputs respond to
inputs according to the delays we specified in the Verilog test fixture code.

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Figure 12

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Figure 13

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LAB TASK # 2:
Design and simulate a full adder using two half adders.

THEORY:
FULL ADDER:
A full adder adds binary numbers and accounts
for values carried in as well as out. A one-bit
full adder adds three one-bit numbers, often
written as A, B, and Ci; A and B are the
operands, and Ci is a bit carried in. The circuit
produces a two-bit output, S and Co; the final
sum is 2 X Co +S.

A
0
0
0
0
1
1
1
1

B
0
0
1
1
0
0
1
1

Ci
0
1
0
1
0
1
0
1

sum
0
1
1
0
1
0
0
1

Co
0
0
0
1
0
1
1
1

Truth Table
Lets take the following steps:

1. ENTERING THE DESIGN

Follow the lab task 1 of half adder, start from the new source.
From the Project Navigators pull-down menus, select Project -> New Source. This launches the New
Source Wizard. This window can be used to add a variety of sources to your design. Select "Schematic"
and add the name of your circuit. The box "Add to project" should be checked. The location should
appear as the directory you selected above. Click Next shown in figure 14.

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Lab1

Figure 14
Design the schematics by drag drop the symbols. Remember you create a symbol of your half adder
schematic, now use that symbol to make full adder schematic as shown in Figure 15.

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Lab1

Figure 15

Save the file. Click on Design option at the bottom of the process window select your file and
expand the Design Utilities option. Click on Check Design Rules, if it will be correct a green
arrow will appear. Then click Create Schematic Symbol to make your schematic a symbol for
further use. Again a green arrow will appear.

2. SIMULATING THE CIRCUIT

First check the simulation tab in Design panel after that click from the Project Navigator
window Project -> New Source. The same New Source Wizard appears that was used earlier
to enter our fullfadder schematic. This time, instead of selecting Schematic, select Verilog Test
Fixture. Name the file fulladder_tf (to distinguish it from the actual fulladder.sch file) and click
Next. A new window will pop-up asking you which module describes the circuit you want to test.
Here you have to choice fulladder module. Select this module and then click Next. The New
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Lab1

Source Wizard now shows a summary page. Click Finish. Clicking on Finish, the Project
Navigator screen reappears and you will see that the wizard has already generated some Verilog
code. Now for full adder test fixture write the following code:
Test Fixture Code:
moduleFullAdder_tf;

//Inputs

regA;

regB;

regCin;

//Outputs

wireSum;

wireCout;

integeri;

//InstantiatetheUnitUnderTest(UUT)

FullAdderuut(

.A(A),

.B(B),

.Cin(Cin),

.Sum(Sum),

.Cout(Cout)

);
initialbegin

//InitializeInputs

A=0;

B=0;

Cin=0;

end
always@(A,B,Cin)

begin

//generatetruthtable

for(i=0;i<8;i=i+1)
//every10nsseta,b,andctothebinaryrep.ofi

#10{A,B,Cin}=i;

//stop10nsafterlastchangeofinputs

#10$stop;

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Lab1

//Wait100nsforglobalresettofinish

#100;
end
endmodule

Save the file. Select fulladder_tf in the Hierarchy window and then in process panel double click
on Behavioral Check Syntax to check for errors. Correct any errors if there is then save it and
check again. Once, the code is free from error, right-click on Simulate Behavioral Model in
process panel and select Process Properties. This will generate the Isim Properties pop-up
window. Set the Simulation Run Time to 200 ns and click OK.
Double-click on Simulate Behavioral Model in process panel. The waveforms will now appear as
shown in Figure 16. Check for correct functionality of the full adder. Note the timing delays as
outputs respond to inputs according to the delays we specified in the VHDL code.
Your second task is completed successfully. Now add and explain the screen shot of your task#2
design simulation.

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Lab1

LAB TASK # 3:
Design and simulate a 4 bit ripple carry Adder using 4 full adders.

THEORY:
4 BIT RIPPLE CARRY ADDER:
Multiple Basic (1-bit) Full Adders can be cascaded to form a Multi-bit Full Adder. Four Basic
Full Adders are chained together to form a 4-bit Ripple Adder, with the Carry Out (CO) of a
Basic Full Adder connected to the Carry In (Cin) of the next most significant Basic Full Adder.
Addition between two Multi-bit Binary Numbers A and B is done by adding the bits
successively, starting from the Least Significant Bit (LSB), i.e. A0 + B0. Any Carry bit from
previous bits is added to the sum of the next consecutive bits.
Lets take the following steps:

1. ENTERING THE DESIGN

Follow the lab task 2 of full adder, start from the new source. From the Project Navigators pulldown menus and select Project -> New Source. This launches the New Source Wizard. This
window can be used to add a variety of sources to your design. Select "Schematic" and add the
name of your circuit. The box "Add to project" should be checked. The location should appear as
the directory you selected above. Click Next.
Design the schematics by drag drop the symbols. Remember you create a symbol of your full
adder schematic, now use that symbol to make 4 bit ripple carry adder schematic as shown in
Figure 17.

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Lab1

Figure 16
Save the file. Click on Design option at the bottom of the process window select your file and
expand the Design Utilities option. Click on Check Design Rules, if it will be correct a green
arrow will appear.

2. SIMULATING THE CIRCUIT

Again follow the same steps as in example 1 and 2 for creating a test bench file.
Write the following code in the test fixture file:

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Test Fixture Code:

always@(A0,A1,A2,A3,B0,B1,B2,B3)

begin
//generatetruthtable

for(i=0;i<255;i=i+1)
//every10nsseta,b,andctothebinaryrep.ofi

#10{A0,A1,A2,A3,B0,B1,B2,B3}=i;
//stop10nsafterlastchangeofinputs

#10$stop;

//Wait100nsforglobalresettofinish

#100;
end

Your third task is completed successfully. Now add and explain the screen shot of your task#3
design simulation.

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Lab2

LAB 2
OBJECTIVE:
Combinational Logic Schematic Example and Simulation.

LAB TASK # 1:
Design and simulate a 4 to 1 Multiplexer.

THEORY:
4 TO 1 MULTIPLXER:
A multiplexer performs the function of selecting the input on any one of 'n' input lines and
feeding this input to one output line. Multiplexers are used as one method of reducing the
number of integrated circuit packages required by a particular circuit design. This in turn reduces
the cost of the system.
A 4x1 multiplexer is shown in figure below, having 4 inputs A, B, C and D and two selection
lines S0 and S1. There is a single output Y. The working results are shown in truth table.

4x1 Multiplexer

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Truth Table

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Lab2

Lets take the following steps:

ENTERING THE DESIGN

Up till now you are familiar with the software Xilinx, you understand how to make a new project
and start with new source. So keeping that steps in mind, start from creating the desire
schematic. As shown in figure 1 below.

Figure 1
Save the file. Click on Design option at the bottom of the process window select your file and
expand the Design Utilities option. Click on Check Design Rules, if it will be correct a green
arrow will be appearing. Then click Create Schematic Symbol to make your schematic a symbol
for further use. Again a green arrow will appear.

SIMULATING THE CIRCUIT

Follow the same steps for simulation as in lab 1.
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Lab2

Now for 4x1 multiplexer test fixture write the following code:

modulemultiplexer_multiplexer_sch_tb();
//Inputs
regA;
regB;
regC;
regD;
regs0;
regs1;

//Output
wireY;

multiplexerUUT(

.A(A),

.B(B),

.C(C),

.D(D),

.s0(s0),

.s1(s1),

.Y(Y)
);
initialbegin

A=1;

B=0;

C=0;

D=0;

s0=0;

s1=0;

#100

s0=0;s1=1;

#100

s0=1;s1=0;

#100

s0=1;s1=1;
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Lab2

end
endmodule

Your task is completed successfully. Now add and explain the screen shot of your task design
simulation.

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Lab2

LAB ASSIGNMENTS
Lab Assignment 1:
Design a 3x8 decoder. The theory given below will help you to design the schematic. Also verify
the results from truth table given below.

3x8 DECODER:
A decoder is used to determine the ordinal value of a particular bit pattern. In other words, it
decodes the number represented by a stream of binary digits.The 3-to-8 line decoder is so named
because it takes three input signals and converts them into the correct output signal, choosing
from the eight possible values.
If the decoder is fed 101 (the binary for 5), the decoder performs the following tasks: x is on, so
all AND gates with the negation of x cannot turn on. This leaves gates D1, D3, D5, and D7 as
possible output gates. y is off, so all gates without the negation of y cannot turn on. (This turns
off D3 and D7.) z is on, and the only gate that could be turned on is therefore D5 (since D1 could
only be activated if z were off). The output can be determined by the following Boolean
equations:
___
D0 = z y x
__
D1 = z y x
_ _
D2 = z y x
_
D3 = z y x
__
D4 = z y x
_
D5 = z y x
_
D6 = z y x
D7 = z y x

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Lab2

OBSERVATION & RESULT:

________________________________________________________________
________________________________________________________________
________________________________________________________________
________________________________________________________________
_______________________________________________________________

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Lab2

Lab Assignment 2:
Design a 8x3 Encoder / Multiplexer. Theory given below will help you to design the
schematic. Also verify the results from truth table given below.

8x3 ENCODER:
An encoder is a combinational circuit that converts a signal on exactly one input into its
corresponding binary number.
The maximum number of inputs is directly related to the number of outputs. An encoder with
n outputs supports 2^n inputs. When n = 2, there are 2^2 = 4 inputs that can be encoded.
When n = 3, there are 2^3 = 8 inputs that can be encoded.
The output can be determined by the following Boolean equations:
__ __ __
__
A = ( Y6 ( Y4 Y2 Y1 + Y4 Y3 + Y5) + Y7)
__ __
B = (Y5 Y4 (Y2 + Y3) + Y6 + Y7)
C = (Y4 + Y5 + Y6 + Y7)

Truth table of a 8x3 encoder:

OBSERVATION & RESULT:

__________________________________________________________________
__________________________________________________________________
__________________________________________________________________
__________________________________________________________________
__________________________________________________________________

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Lab3

LAB 3
OBJECTIVE:
Sequential Logic Schematic Example and Simulation.
Design and simulate a D flip flop then T flip flop and in hierarchal manner design a 4 bit ripple
carry counter.

LAB TASK # 1:
Design and simulate D-Latch with Enable

THEORY:
LATCHES AND FLIP FLOPS:
Latches and flip-flops are the basic elements for storing information. One latch or flip-flop can
store one bit of information. The main difference between latches and flip-flops is that for
latches, their outputs are constantly affected by their inputs as long as the enable signal is
asserted. In other words, when they are enabled, their content changes immediately when their
inputs change. Flip-flops, on the other hand, have their content change only either at the rising or
falling edge of the enable signal. This enable signal is usually the controlling clock signal. After
the rising or falling edge of the clock, the flip-flop content remains constant even if the input
changes. There are basically four main types of latches and flip-flops: SR, D, JK, and T. The
major differences in these flip-flop types are the number of inputs they have and how they change
state.Foreachtype,therearealsodifferentvariationsthatenhancetheiroperations.In this chapter,
we will look at the operations of the various latches and flip flops.

D LATCH WITH ENABLE:

Just like the SR latch with an enable input, the D latch can also have an enable input .When the E
input is asserted (E = 1), the Q output follows the D input. In this situation, the latch is said to
beopenand the path from the input D to the output Q is transparent. Hence the circuit is often
referred to as a transparent latch. When E is de-asserted (E = 0), the latch is disabled or
closed, and the Q output retains its last value independent of the D input.
E
0
0
1
1

0
1

Q
0
1

0
1
0
1

1
0
1
0

NOTE:adon'tcaretermisaninputsequenceto
afunctionthatthedesigndoesnotcareabout.

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LOGIC SYMBOL OF D LATCH WITH ENABLE

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Lab3

Lets take the following steps:

1. ENTERING THE DESIGN

The software we will be using is the Xilinx "ISE Project Navigator", in which you can enter the
Schematic design and simulate its outputs for a specified sequence of inputs (as we have learned
in lab 1 and 2) as shown in figure 1 below.

Figure 1
Save the file. Click on Design option at the bottom of the process window select your file and
expand the Design Utilities option. Click on Check Design Rules, if it will be correct a green
arrow will be appearing. Then click Create Schematic Symbol to make your schematic a symbol
for further use. Again a green arrow will appear.

2. SIMULATING THE CIRCUIT

Now that we have a design that has been checked for its syntax, we can now proceed to a
simulation of the circuit designed. In order to simulate the circuit, we first need a set of signals to
drive our inputs. We do this by constructing a separate source file called a test fixture. This code
defines the signals and then applies them to the entity under test.

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Test Fixture Code:

moduledlatche_dlatche_sch_tb();
//Inputs
regclk;
regD;
regreset;

//Output
wireQdesh;
wireQ;

//Bidirs

//InstantiatetheUUT
dlatcheUUT(

.Qdesh(Qdesh),

.Q(Q),

.clk(clk),

.D(D),

.reset(reset)
);
//InitializeInputs
initialbegin

clk=0;

D=0;

reset=1;
#100reset=0;clk=1;D=1;
#100clk=0;D=0;
end
endmodule

Save the file. Select D_tf in the Hierarchy window and then in process panel double click on
Behavioral Check Syntax to check for errors. Correct any error if there is, and then save it and
check again. Once, the errors are removed, right-click on Simulate Behavioral Model in process
panel and select Process Properties. This will generate the Isim Properties.
We are now ready to run the simulation. Double-click on Simulate Behavioral Model. This
brings up the ISim simulation window. Waveforms are plotted in the top right-hand window.
Note that the simulator very conveniently plots the last 3ps of the simulation! In order to see the
whole simulation, click the Zoom to Full View icon in the tool-bar immediately above the
simulation window. The waveforms will now appear. Check for correct functionality of the half
adder. Note the timing delays as outputs respond to inputs according to the delays we specified
in the Verilog test fixture code.
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Lab3

Figure 2

LAB TASK # 2:
Design and simulate D-Flip-flop

D FLIP-FLOP:
Latches are often called level-sensitive because their output follows their inputs as long as they
are enabled. They are transparent during this entire time when the enable signal is asserted.
There are situations when it is more useful to have the output change only at the rising or falling
edge of the enable signal. This enable signal is usually the controlling clock signal. Thus, we can
have all changes synchronized to the rising or falling edge of the clock. An edge-triggered flipflop achieves this by combining in series a pair of latches. Figure shows a positive edge-triggered
D flip-flop where two D latches are connected in series. The first latch is called the master latch.
The master latch is enabled when Clk = 0 and follows the primary input D. When Clk is 1, the
master latch is disabled but the second latch, called the slave latch, is enabled so that the output
from the master latch is transferred to the slave latch. The slave latch is enabled all the while that
Clk = 1, but its content changes only at the beginning of the cycle, that is, only at the rising edge
of the signal because once Clk is 1, the master latch is disabled and so the input to the slave latch
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Lab3

will not change. The circuit is called a positive edge-triggered flip flop because the output Q on
the slave latch changes only at the rising edge of the clock. If the slave latch is enabled when the
clock is low, then it is referred to as a negative edge-triggered flip-flop. The circuit is also
referred to as a master slave D flip-flop because of the two latches used in the circuit.

TRUTH TABLE

Logic Symbol

Figure 3

Test Fixture Code:

moduleD_FlipFlop_D_FlipFlop_sch_tb();

//Inputs
regD;
regReset;
regClk;

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Lab3

//Output
wireQ;
wireQbar;

//Bidirs

//InstantiatetheUUT
D_FlipFlopUUT(
.D(D),
.Q(Q),
.Qbar(Qbar),
.Reset(Reset),
.Clk(Clk)
);
parameterperiod=100;

alwaysbegin
Clk=1;
#(period/2)
Clk=0;
#(period/2);
end
initialbegin
D=0;
Reset=1;
#100Reset=0;D=1;
#90D=0;
end
endmodule

Your task is completed successfully. Now add and explain the screen shot of your task design
simulation.

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LAB TASK # 3:
Design T Flip Flop using D Flip Flop

T FLIP FLOP:
The T flip-flop has one input in addition to the clock. T stands for toggle for the obvious reason.
When T is asserted (T = 1), the flip-flop state toggles back and forth, and when T is de-asserted,
the flip-flop keeps its current state. The T flip-flop can be constructed using a D flip-flop with
the two outputs Q and Q'.
T

LOGIC SYMBOL OF T FLIP FLOP

TRUTH TABLE

Figure 5
Test Fixture Code:
moduleT_FlipFlop_T_FlipFlop_sch_tb();
//Inputs
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regT;
regClk;
regReset;
//Output
wireQ;
//Bidirs
//InstantiatetheUUT
T_FlipFlopUUT(
.T(T),
.Q(Q),
.Clk(Clk),
.Reset(Reset)
);
parameterperiod=100;
alwaysbegin
Clk=1;
#(period/2)
Clk=0;
#(period/2);
end
//InitializeInputs
initialbegin
T=1;
Reset=1;
#100Reset=0;T=1;
end
endmodule

Your task is completed successfully. Now add and explain the screen shot of your task design
simulation.

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LAB TASK # 4
Design Up down counter using T Flip Flop

COUNTER:
Acounterisasequentialcircuitwhoseoutputprogressesinapredictablerepeatingpattern,advancing
byonestateforeachclockpulse.Ithasanumberofbinaryoutputswhosestatesprogressthrougha
fixedsequence.Thiscountsequencecanbeascending,descending,ornonlinear.

UP DOWN COUNTER:
Acounterthatcanchangestateineitherdirection,underthecontrolofanup/downselectorinput,is
knownasanup/downcounter.Whentheselectorisintheupstate,thecounterincrementsitsvalue.
Whentheselectorisinthedownstate,thecounterdecrementsthecount.Acombinationofup
countersanddowncountersthatallowsyoutoincreaseanddecreasevaluesbyanincrementof1.
U/D
1
1
1
1
1
1
0
0
0
0
0
0

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0 0
0
0
0
0
0
0
1
0
1
0

..
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1

..
0
0
0
TRUTHTABLE

0
1
0
0
.
1
1
0
1
1

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Lab3

Figure 7

Test Fixture Code:

modulecounter_counter_sch_tb();
//Inputs
regupdown;
regReset;
regClk;
//Output
wireQ0;
wireQ1;
wireQ2;
wireQ3;
//InstantiatetheUUT
counterUUT(
.updown(updown),
.Reset(Reset),
.Clk(Clk),
.Q0(Q0),
.Q1(Q1),
.Q2(Q2),
.Q3(Q3)
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);
parameterperiod=100;

alwaysbegin
Clk=1;
#(period/2)
Clk=0;
#(period/2);
end
//InitializeInputs
initialbegin
updown=1;
Reset=1;
#100Reset=0;
#900;
end
endmodule

Your task is completed successfully. Now add and explain the screen shot of your task design
simulation.

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LAB 4
OBJECTIVE
Introduction to Verilog Language, Gate Level Modeling and Example.

THEORY
WHAT IS MODULE IN VERILOG
A module is the basic building block in Verilog. Just like functions and procedures in C or
any other language, in verilog a module can be an element or a collection of lower-level
design blocks
In Verilog, a module is declared by the keyword module.
A corresponding keyword endmodule must appear at the end of the module definition
Each module must have a module_name, which is the identifier for the module, and a
module_terminal_list, which describes the input and output terminals of the module.

STRUCTURE OF MODULE IN VERILOG

module <module name> (<module_terminal_list>);
...
<module internals>
...
...
Endmodule
In verilog, the internals of module can be defined at four levels of abstraction.
These levels are:
a) Behavioral level
b) Data flow level
c) Gate level
d) Switch level

WHAT IS INSTANCE IN VERILOG

In verilog, A module provides a template from which we can create actual
objects
When a module is invoked, Verilog creates a unique object from the template
Each object has its own name, variables, parameters, and I/O interface
The process of creating objects from a module template is called instantiation,
and the objects are called instances
module ripple_carry(<module_terminal_list>);
full_adder fa(<module_terminal_list>);
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endmodule
module full_adder (<module_terminal_list>);
<module internals>
endmodule

LEXICAL CONVENTIONS

Whitespace
Blank spaces, tabs and newlines, comprise the whitespace.
Comments
A one-line comment starts with "//".
A multiple-line comment starts with "/*" and ends with "*/".
Operators
Operators are of three types: unary, binary, and ternary.
a = ~ b; // ~ is a unary operator. b is the operand
a = b && c; // && is a binary operator. b and c are operands
a = b ? c : d; // ?: is a ternary operator. b, c and d are operands
Number Specification
Sized numbers are represented as <size> '<base format> <number>.
4b1111 // This is a 4-bit binary number
12habc // This is a 12-bit hexadecimal number
16d255 // This is a 16-bit decimal number

DATA TYPES

Nets

Nets represent connections between hardware elements.

Nets are declared primarily with the keyword wire.
wire a;
// Declare net a for the above circuit
wire b, c; // Declare two wires b,c for the above circuit
wire d = 1b0; // Net d is fixed to logic value 0 at declaration
Registers
Registers represent storage data elements.
Register data types are commonly declared by the key word reg.
reg reset; // declare a variable that can hold its value
Vectors
Nets or reg data types can be declared as vectors.
If bit width is not specified, the default is scalar.
wire a;
// scalar net variable, default
wire [7:0] bus;
// 8-bit bus
wire [31:0] busA, busB, busC; // 3 buses of 32-bit width
reg clock;
// scalar register, default
reg [0:40] virtual_addr; // vector register, 41-bits wide

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PORTS
Ports provide the interface by which a module can communicate with its environment.
For example, the Input/Output pins of an IC chip are its ports.
module fulladd4(sum, c_out, a, b, c_in);
output sum, c_out;
input a, b, c_in;
Different types of Port available like
Input
Output
Inout

PORT CONNECTION RULES

There are rules governing port connections when modules are instantiated within other
modules.
Inputs
Internally, input ports must always be of the type net. Externally, the inputs can be
connected to a variable which is a reg or a net.
Outputs
Internally, outputs ports can be of the type reg or net. Externally, outputs must always
be connected to a net. They cannot be connected to a reg.
Inouts
Internally, inout ports must be of the type net. Externally, inout ports must always be
connected to a net.

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SYSTEM TASKS AND COMPILER DIRECTIVES

System tasks appear in the form $<keyword>

Displaying information
$display is the main system task for displaying values of variables or strings or
expressions. (%b, %h,%o,%s,%d,%c)
Usage: $display(p1, p2, p3,....., pn);

GATE-LEVEL MODELING

Identify logic gate primitives provided in Verilog.

Understand instantiation of gates, gate symbols, and truth tables for AND, OR and NOT
type gates.
Understand how to construct a Verilog description from the logic diagram of the circuit.
Describe rise, fall, and turn-off delays in the gate-level design.

GATE TYPES

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and and_1(out, in1, in2);

or or_1(out, in1, in2);
nand nand_1( out, in1, in2);
nor nor_1( out, in1, in2);
xor xor_1( out, in1, in2);
xnor xnor_1( out, in1, in2);

and a1(out, in1, in2);

and a2(out, in1, in2, in3);
and a3(out, in1, in2, in3,in4);

GATE DELAYS

In real circuits, logic gates have delays associated with them.

Until now, we described circuits without any delays (i.e., zero delay).
There are three types of delays from the inputs to the output of a primitive gate.
Rise, Fall, and Turn-off Delays

LAB TASK # 1
GATE-LEVEL MULTIPLEXER

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// Module 4-to-1 multiplexer. Port list is taken exactly from the I/O diagram
module mux4_to_1 (out, i0, i1, i2, i3, s1, s0);
// Port declarations from the I/O diagram
output out;
input i0, i1, i2, i3;
input s0, s1;
// Internal wire declarations
wire s1n, s0n;
wire y0, y1, y2, y3;
// Gate instantiations
// Create s1n and s0n signals
not (s1n, s1);
not (s0n, s0);
// 3-input and gates instantiated
and (y0, i0, s1n, s0n);
and (y1, i1, s1n, s0);
and (y2, i2, s1, s0n);
and (y3, i3, s1, s0);
// 4-input or gate instantiated
or (out, y0, y1, y2, y3);
endmodule

Your task is completed successfully. Now add and explain the screen shot of your task design
simulation.

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LAB TASK # 2

A 2-input XOR gate can be built from AND, OR and NOT gates. Construct an XOR gate
module in Verilog that realizes the logic function
z = xy + xy
Inputs are x and y, and z is the output.

Your task is completed successfully. Now add and explain the screen shot of your task design
simulation.

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LAB ASSIGNMENT
Lab Assignment 1:
Implement the following circuit diagram

OBSERVATION & RESULT:

__________________________________________________________________
__________________________________________________________________
__________________________________________________________________
__________________________________________________________________
__________________________________________________________________

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Lab Assignment 2:
Implement the 7 segment display logic circuit.

OBSERVATION & RESULT:

__________________________________________________________________
__________________________________________________________________
__________________________________________________________________
__________________________________________________________________
__________________________________________________________________

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Lab5

LAB 5
OBJECTIVES
Define expressions, operators, and operands. Use dataflow constructs to model practical digital
circuits in Verilog.

THEORY
REASON FOR USING DATAFLOW MODELING
For small circuits, the gate-level modeling approach works very well. For small circuits, the
gate-level modeling approach works very well The reason is that the number of gates is limited
and the designer can instantiate and connect every gate individually but in complex designs the
number of gates is very large. Thus, designers can design more effectively if they concentrate on
implementing the function at a level of abstraction higher than gate level.
This is the point where Dataflow Modeling comes, provides a powerful way to implement a
design.

IMPORTANCE OF DATAFLOW MODELING

Dataflow Modeling provides much easier platform for designing as compared to gate level
because gate densities on chips increasing rapidly. In this context, even gate-level circuits are
created using logic synthesis from a dataflow design description for maximum flexibility; gatelevel, data flow, and behavioral design are used in combination.

CONTINUOUS ASSIGNMENT
The basic statement in dataflow modeling is continuous assignment .Its purpose is to drive value
onto a net .This assignment replaces gates in the description of the circuit and describes the
circuit at a higher level of abstraction .The keyword for continuous assignment is assign

CHARACTERISTICS OF CONTINUOUS ASSIGNMENT

The left hand side of an assignment must always be a scalar or vector net or a concatenation of
scalar and vector nets. It cannot be a scalar or vector register Continuous assignments are always
active.
The assignment expression is evaluated as soon as one of the right-hand-side operands
changes and the value is assigned to the left-hand-side net. The operands on the right-hand side
can be registers or nets or function calls. Registers or nets can be scalars or vectors.

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EXAMPLES
2 x 1 multiplexer
//method 1
module mux21(q, sel, a, b);
input sel, a, b;
output q;
assign q = (~sel & a) | (sel & b);
//assign q = sel ? b : a;
endmodule
//method 2
module mux21(q, sel, a, b);
input sel, a, b;
output q;
assign q = (~sel & a) | (sel & b);
endmodule
EXPRESSIONS, OPERATORS AND OPERANDS
Dataflow modeling describes the design in terms of expressions instead of primitive gates
a) Expressions:
Expressions are constructs that combine operators and operands to produce a result.
b) Operands:
Operands can be constants, integers, real numbers, nets, registers.
c) Operators:
Operators act on the operands to produce desired results. Verilog provides various types of
operators.

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LAB TASK
T
#1

CODE #1:
// Modulee 4-to-1 mulltiplexer. Porrt list is takeen exactly froom the I/O diagram
d
module mux4_to_1
m
(out,
(
i0, i1, i22, i3, s1, s0));
// Port deeclarations frrom the I/O diagram
output ouut;
input i0, i1, i2, i3;
input s0, s1;
assign ouut = s1 ? (s0
0 ? i3 : i2):(s00 ? i1 : i0) ;
endmoduule

CODE##2:
// Modulee 4-to-1 mulltiplexer. Porrt list is takeen exactly froom the I/O diagram
d
module mux4_to_1
m
(out,
(
i0, i1, i22, i3, s1, s0));
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// Port deeclarations frrom the I/O diagram

output ouut;
input i0, i1, i2, i3;
input s0, s1;
assign ouut = (i0 & (~
~s0) & (~s1))) | (i1 & s0 & (~s1)) | (i22 & (~s0) & s1) |
(i3 & s0 & s1);
endmoduule
Your task is completed successffully. Now add
a and expplain the screeen shot of your task design
d
simulatioon.

LAB TASK
T
#2

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CODE :
// Module 2-bit Full Adder. Port list is taken exactly from the I/O diagram
module fulladd2_bit(y, z, c, b, a);
// Port declarations from the I/O diagram
output y, z;
input c, b, a;
assign y = c ? (a?(b?1:0):(b?0:1)):(a?(b?0:1):(b?1:0));
assign z = (c ? (a?1:b):(a?(b?1:0):0));
endmodule
Your task is completed successfully. Now add and explain the screen shot of your task design
simulation.

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Lab5

LAB ASSIGNMENT
Lab Assignment 1:
Given below is the theory and logic of 8 bit Ripple Carry Adder / Subtractor. Your assignment is
to design a 8 bit Ripple Carry Adder / Subtractor using Data flow Modeling record a truth table
for this adder / subtractor.

ADDER / SUBTRACTOR
The adder / subtractor circuit performs subtraction by adding the negated value of the second
operand. Recall that to negate a value in twos complement representation, we simply invert all
the bits from 0 to 1 and vice versa, and then add a 1.
When the subtraction operation is selected, i.e. S = 1, the B operand needs to be inverted.
Recalling that x
1 = x', we can thus simply flip the bits in B by performing the operation B
S since S = 1. Finally, the addition of a 1 is accomplished by setting the primary carry-in signal
c0 to 1. On the other hand, when the addition operation is selected, i.e. S = 0, the B operand will
not be inverted by the XOR operation. In this case, we also want c0 = S = 0.

8-bit adder / subtractor combination circuit

Operation performed

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Lab5

OBSERVATION & RESULT:

__________________________________________________________________
__________________________________________________________________
__________________________________________________________________
__________________________________________________________________
__________________________________________________________________

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LAB 6

LAB
B6
OBJECTIVE
Introducttion to behav
vioral modelling.

THEO
ORY
BEHAV
VIORAL MODELI
M
ING
Behaviorral modeling
g is the higheest level of abstraction in
i the Veriloog HDL. The other moddeling
techniquees are relativ
vely detailedd. They requuire some knnowledge off how hardw
ware or harddware
signals work.
w
The ab
bstraction inn this modeling is as sim
mple as writting the logiic in C languuage.
This is a very powerrful abstracttion techniquue. All that designer neeeds are the algorithm of
o the
design, which
w
is the basic inform
mation for anny design .M
Most of the behavioral
b
m
modeling,
is done
using tw
wo importantt constructs: initial and always. Alll the other behavioral
b
statements apppear
only insidde these two
o structured procedure
p
coonstructs.

THE CONDITIO
C
ONAL STA
ATEMEN
NT IF-ELS
SE
Conditionnal statemen
nts are used for
f making decisions
d
based upon cerrtain conditiion

Thesee conditions are used to decide whetther or not a statement shhould be exeecuted.
Keyw
words if and else are usedd for conditiional statemeents

1) SIMP
PLE IF ST
TATEMEN
NT
if (enablee)
q <= d;

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LAB 6

2) ONE
E ELSE ST
TATEMEN
NT
if (reset == 1'b1)
q <= 0;
else
q <= d;

3) NESTED IF-E
ELSE-IF STATEME
S
ENT
= 1'b0)
if (reset ==
counter <=
< 4'b0000;
else if (ennable == 1'b
b1 && up_enn == 1'b1)
counter <=
< counter + 1'b1;
else if (ennable == 1'b
b1 && downn_en == 1'b1);
counter <=
< counter - 1'b0;
else
counter <=
< counter; //
/ Redundantt code

THE CASE
C
STA
ATEMENT
T
The casee statement is
i a multi-w
way decision statement thhat tests whhether an exppression maatches
one of thhe expression
ns and brancches accordiingly. Keywords case annd end case are used to make
m
a case staatement. Thee case statem
ment syntax is
i as followss.

If there are
a multiple statements
s
u
under
a singlle match, theen they are grouped
g
using begin, andd end
keywords .The defau
ult item is opptional.
Case stattement with don't cares: casez and caasex
casez treaats high-imp
pedance valuues (z) as donn't cares. cassex treats booth high-impedance (z) and
a
unknownn (x) values as
a don't carees. Don't-caree values (z values
v
for caasez, z and x values for
casex) inn any bit of either
e
the casse expressionn or the casee items shall be treated as don't-care
conditionns during thee comparisonn, and that bit position shhall not be considered.
c
T don't carres
The
are represented using
g the ? mark..

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THE CASEZ AND CASEX STATEMENT

Special versions of the case statement allow the x and z logic values to be used as "don't
care
casez uses the z as the don't care instead of as a logic value
casex uses either the x or the z as don't care instead of as logic values

EXAMPLE:
casez (opcode)
4'b1zzz : out = a; // don't care about lower 3 bits
4'b01??: out = b; //the ? is same as z in a number
4'b001?: out = c;
default: out = $display ("Error xxxx does matches 0000");
endcase

STRUCTURED PROCEDURES
All procedures in the Verilog HDL are specified within one of the following four statements:

INITIAL (CONSTRUCT)
An initial block consists of a statement or a group of statements enclosed in begin... end or a
single statement, which will be executed only once at simulation time 0. If there is more than one
block they execute concurrently and independently. The initial block is normally used for
initialization, monitoring, generating wave forms (e.g., clock pulses) and processes which are
executed once in a simulation. An example of initialization and wave generation is given below
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EXAMPLE
always@(posedgeclk)
begin:D_FF
if (reset == 1)
q <= 0;
else
q <=d; end

ALWAYS (CONSTRUCT)
An always block is similar to the initial block, but the statements inside an always block will
repeated continuously, in a looping fashion, until stopped by $finish or $stop.NOTE: the $finish
command actually terminates the simulation where as $stop. Merely pauses it and awaits further
instructions. Thus $finish is the preferred command unless you are using an interactive version
of the simulator.One way to simulate a clock pulse is shown in the example below. Note, this is
not the best way to simulate a clock. See the section on the forever loop for a better method.
EXAMPLE
initial
Begin
clk = 0;
reset = 0;
enable= 0;
data=0;
end

PROCEDURAL ASSIGNMENTS

Procedural assignments update values of reg, integer, real, or time variables

The value placed on a variable will remain unchanged until another procedural assignment
updates the variable with a different value
The left-hand side of a procedural assignment <lvalue> can be a reg, integer, real, or time
register variable or a memory element
The right-hand side can be any expression that evaluates to a value
There are two types of procedural assignment statements: blocking and no blocking.

BLOCKING ASSIGNMENTS

The = operator is used to specify blocking assignments. A blocking statement must be

executed before the execution of the statements that follow it in a sequential block.

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Synthessis Output

NON BLOCKIN
B
NG ASSIG
GNMENTS
S

Non-blocking staatements alloow you to scchedule assiggnments withhout blockinng the proceddural
flow
Synthesis Output

SEQUE
ENTIAL AND
A
PAR
RALLEL BLOCKS
B

Blocck statementts are used too group multtiple statemeents to act toogether as onne. There aree two
typees of blocks: sequential blocks
b
and parallel blockks

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LAB 6

SEQUE
ENTIAL BLOCKS
B

The keywords begin and endd are used too group stateements into sequential
s
bllocks
Sequuential blocks have the following chharacteristicss:
The statements in
i a sequentiial block aree processed in the order they
t
are speccified.
If deelay or eventt control is specified,
s
it is
i relative to the simulatiion time wheen the previoous
stateement in the block comppleted executtion

Parallel Blocks

The keywords
k
forrk and join are
a used to group
g
statem
ments into seqquential bloccks.
Paralllel blocks haave the folloowing characcteristics:
Statem
ments in a parallel
p
blockk are executeed concurrenntly Orderingg of statements is controolled
by the delay or ev
vent control assigned to each statem
ment.
If dellay or event control is sppecified, it iss relative to the
t time the block was entered in Paarallel
Blockk, the order in
i which thee statements are written is
i not importtant.
fork: splitting sin
ngle flow intoo independeent flows
join: joining
j
indeependent flow
ws into singlle flow

Examplee
//parallell block
reg x,y;
reg [1:0] z,w;
Initial
fork
x = 1b0;;\\ completess at simulatioon time 0
#5 y = 1b1; \\ complletes at simuulation time 5
#10 z = (x,y);
(
\\ comp
pletes at sim
mulation timee 10
#20 w = (y,x); \\ com
mpletes at sim
mulation tim
me 20
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LAB 6

join
The ressult is that th
he simulationn will end att time 20 insttead of time 35 b/c all sttatements aree
runningg in parallel..

LAB TASK#1:
T
:

a and expplain the screeen shot of your task design

d
Your task is completed successffully. Now add
simulatioon.
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LAB 6

LAB TASK#2:
T
:
1) Writee and verify a verilog moodel of up_ddown_counteer the circuitt that increm
ment or decreement
the coount at every
y clock and up_down_pt
u
tr.

a and expplain the screeen shot of your task design

d
Your task is completed successffully. Now add
simulatioon.

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B

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LAB 6

LAB ASSIGN
NMENT
Lab Asssignment 1:
3-bit up-down counter with addiitional featurres that loadd an initial coount and enaable the couunting
activity.

OBS
SERVATIION & RE
ESULT:
_____________
___________________
_________________________________________
_____________
___________________
_________________________________________
_____________
___________________
_________________________________________
_____________
___________________
_________________________________________
_____________
___________________
________________________________________

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LAB 6

Lab Asssignment 2:
Design keypad
k
Scann
ner and Encooder.

OBS
SERVATIION & RE
ESULT:
_____________
___________________
_________________________________________
_____________
___________________
_________________________________________
_____________
___________________
_________________________________________
_____________
___________________
_________________________________________
_____________
___________________
________________________________________

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B

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Lab7

LAB 7
OBJECTIVE:
Hierarchal model.

THEORY:
DESIGN METHODOLOGY:
Basically there are two types of design methodologies:
a) Top-down methodology
Bottom-up methodology
In a top-down design methodology, we define the top-level block and identify the subblocks necessary to build the top-level block

In a bottom-up design methodology, we first identify the building blocks that are
available to us. We build bigger cells, using these building blocks

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Lab7

In common applications, a combination of top-down and bottom-up methodology is used

WHAT IS MODULE IN VERILOG

A module is the basic building block in Verilog. Just like functions and procedures in C
or any other language, in verilog a module can be an element or a collection of lowerlevel design blocks
In Verilog, a module is declared by the keyword module.
A corresponding keyword endmodule must appear at the end of the module definition
Each module must have a module_name, which is the identifier for the module, and a
module_terminal_list, which describes the input and output terminals of the module.

WHAT IS MODULE IN VERILOG

A module is the basic building block in Verilog. Just like functions and procedures in C
or any other language, in verilog a module can be an element or a collection of lowerlevel design blocks
In Verilog, a module is declared by the keyword module.
A corresponding keyword endmodule must appear at the end of the module definition
Each module must have a module_name, which is the identifier for the module, and a
module_terminal_list, which describes the input and output terminals of the module.

STRUCTURE OF MODULE IN VERILOG

module <module name> (<module_terminal_list>);
...
<module internals>
...
...
Endmodule
In verilog, the internals of module can be defined at four levels of abstraction.
These levels are:
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a)
b)
c)
d)

Behavioral level
Data flow level
Gate level
Switch level

WHAT IS INSTANCE IN VERILOG

In verilog, A module provides a template from which we can create actual
objects
When a module is invoked, Verilog creates a unique object from the template
Each object has its own name, variables, parameters, and I/O interface
The process of creating objects from a module template is called instantiation,
and the objects are called instances
module Counter (<module_terminal_list>);
T_FF TFF(<module_terminal_list>);
endmodule
module T_FF (<module_terminal_list>);
<module internals>
endmodule

PORTS
Ports provide the interface by which a module can communicate with its environment.
For example, the Input/Output pins of an IC chip are its ports.
module fulladd4(sum, c_out, a, b, c_in);
output sum, c_out;
input a, b, c_in;
Different types of Port available like
Input
Output
Inout

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DATA TYPES
Value Set
Verilog supports four values

Value Level

Condition in Hardware Circuits

Logic zero, false condition

Logic one, true condition

Unknown logic value

High impedance, floating state

A PRACTICAL EXAMPLE
We can take a practical example of 4-bit Ripple Carry Counter for verilog
module
We are using bottom-up methodology for the design

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LAB TASK # 1:
Step one is to design a D-FlipFlop
Truth table for D-FlipFlop
Verilog module for D-flipflop
module D_FF(q, d, clk, reset);
output q;
input d, clk, reset;
reg q;
always @ ( posedge clk or negedge reset)
if (~reset) begin
q <= 1'b0;
end
else begin
q <= data;
end
endmodule

Your task is completed successfully. Now add and explain the screen shot of your task design
simulation.

LAB TASK # 2:
Step one is to Design T-flipflop using D-flipflop and inverter
Schematic for T-FlipFlop
Verilog module for T-flipflop
module T_FF(q, clk, reset);
output q;
input clk, reset;
wire d;
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D_FF dff0(q, d, clk, reset);

not n1(d, q); // not is a Verilog-provided primitive. case sensitive
endmodule

Your task is completed successfully. Now add and explain the screen shot of your task design
simulation.

LAB TASK # 3:
Design Ripple Carry Counter using four T-FlipFlop
Verilog module for Ripple Carry Counter
module ripple_carry_counter(q, clk, reset);
output [3:0] q;
input clk, reset;
//4 instances of the module T_FF are created.
T_FF tff0(q[0],clk, reset);
T_FF tff1(q[1],q[0], reset);
T_FF tff2(q[2],q[1], reset);
T_FF tff3(q[3],q[2], reset);
Endmodule

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Your task is completed successfully. Now add and explain the screen shot of your task design
simulation.

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LAB ASSIGNMENTS
Lab Assignment 1:
The theory of SIPO (serial in parallel out) 4 bit shift register is given below, your assignment is
to design and simulate and record the output in the form of truth table.

SIPO:
This configuration allows conversion from serial to parallel format. Data is input serially, Once
the data has been input, it may be either read off at each output simultaneously, or it can be
shifted out and replaced.

OBSERVATION & RESULT:

__________________________________________________________________
__________________________________________________________________
__________________________________________________________________
__________________________________________________________________
__________________________________________________________________

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Lab Assignment 2:
The theory of PISO (parallel in serial out) 4 Bit shift register is given below, your assignment is
to design and simulate and record the output in the form of truth table.

PISO:
This configuration has the data input on lines D1 through D4 in parallel format. To write the data
to the register, the Write/Shift control line must be held LOW. To shift the data, the W/S control
line is brought HIGH and the registers are clocked. The arrangement now acts as a SISO shift
register, with D1 as the Data Input. However, as long as the number of clock cycles is not more
than the length of the data-string, the Data Output, Q, will be the parallel data read off in order.

OBSERVATION & RESULT:

__________________________________________________________________
__________________________________________________________________
__________________________________________________________________
__________________________________________________________________
__________________________________________________________________

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LAB
B9
OBJECTIVE:
To studyy the characteeristics of loogic gates deelays and to calculate
c
andd measure thhe output of logic
gates delays.

THEO
ORY:

In reeal circuits, logic

l
gates haves
h
delays associated with
w them.
Veriilog providess the mechannism to assoociate delays with gates.
Gatee delays allow the Veriloog user to sppecify delayss through thee logic circuiits.
Therre are three types
t
of delaays from the inputs to the output of a primitive gate:
g
a)) Rise, Falll and Turn-off delays.
b)) Minimal, Typical, andd Maximum
m delays.

RISE DE
ELAY
The rise delay is asso
ociated with a gate outpuut transition to a 1 from another valuue.

D
FALL DELAY
The fall delay
d
is asso
ociated with a gate outpuut transition to
t a 0 from another
a
valuue.

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TURN OFF DELAY

The turn-off delay is associated with a gate output transition to the high impedance value (z)
from another value.
Three types of delay specifications are allowed:
If only one delay is specified, this value is used for all transitions.
If two delays are specified, they refer to the rise and fall delay values.
If all three delays are specified, they refer to rise, fall, and turn-off delay Values.
The turn-off delay is the minimum of the two delays.

Examples
// Delay for all transitions
or #5 u_or (a,b,c);
// Rise and fall delay
and #(1,2) u_and (a,b,c);
// Rise, fall and turn off delay
nor # (1,2,3) u_nor (a,b,c);
//One Delay, min, typ and max

nand #(1:2:3) u_nand (a,b,c);

//Two delays, min,typ and max
buf #(1:4:8,4:5:6) u_buf (a,b);
//hree delays, min, typ, and max
notif1 #(1:2:3,4:5:6,7:8:9) u_notif1 (a,b,c);
LOOPING STATEMENTS
Verilog has four looping statements like any other programming language.

forever
repeat
while
for

All looping statements can appear only inside an initial or always block. Loops may contain
delay expressions.

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THE FOREVER STATEMENT

The forever loop executes continually, the loop never ends
syntax : forever <statement>
Example
Free running clock generator
initial begin
clk = 0;
forever #5 clk = !clk;
end
THE REPEAT STATEMENT
The repeat loop executes statement fixed <number> of times
syntax : repeat (<number>) <statement>
Example
if (opcode == 10) //perform rotate
repeat (8) begin
temp = data[7];
data = {data<<1,temp};
end
THE WHILE LOOP STATEMENT
The while loop executes as long as an <expression> evaluates as true
syntax : while (<expression>) <statement>
Example
loc=0;
if(data=0)//exampleofa1detectshiftvalue
loc=32;
elsewhile(data[0]==0);//findthefirstsetbit
begin
loc=loc+1;
data=data<<1;
end

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THE FOR LOOP STATEMENT

The For loop is same as the For loop used in any other programming language.
Executes an <initial assignment> once at the start of the loop.
Executes the loop as long as an <expression> evaluates as true.
Executes a <step assignment> at the end of each pass through the loop.

Syntax
for (<initial assignment>; <expression>, <step assignment>)
<statement>
Example
for (i=0;i<=63;i=i+1)
ram[i] <= 0; // Inialize the RAM with 0
PROCEDURAL TIMING CONTROL

Delays controls.
Edge-Sensitive Event controls
Level-Sensitive Event controls-Wait statements
Named Events

DELAYS CONTROLS
Delays the execution of a procedural statement by specific simulation time.
syntax : #<time> <statement>;
Example
module clk_gen (clk,reset);
output clk,reset;
reg clk, reset;
initial begin
clk = 0;
reset = 0;
#2 reset = 1;
#5 reset = 0;
end
always
#1 clk = !clk;
Endmodule
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EDGE SENSITIVE EVENT CONTROLS

Delays execution of the next statement until the specified transition on a signal.
syntax : @ (<posedge>|<negedge> signal) <statement>;
Example
always @ (posedge enable)
begin
repeat (5) // Wait for 5 clock cycles
@ (posedge clk) ;
trigger = 1;
end
LEVEL-SENSITIVE EVEN CONTROLS ( WAIT STATEMENTS )
Delays execution of the next statement until the <expression> evaluates as true.
syntax : wait (<expression>) <statement>;
Example
while (mem_read == 1'b1)
begin
wait (data_ready) data = data_bus;
read_ack = 1;
end

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LAB AS
SSIGNME
ENTS
Lab Asssignment 1:
Use a forr loop to deteect number of
o times 0100 pattern is found in a 32-bit
3
input din.
d The pattterns
can overllap each otheer, ex. 010100 counts as two
t patterns. The 4-bit output
o
is nam
med count

OBSER
RVATION
N & RESU
ULT:
________________
__________________________________________________________
________________
__________________________________________________________
________________
__________________________________________________________
________________
__________________________________________________________
________________
__________________________________________________________

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B

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Lab Asssignment 2:
Use whille loop to design a circuiit which diviides a 16-bitt input din byy 3. The 15-bbit output reesult
holds thee result of thee division, and
a 2-bit outpput remainder the remainnder.
Hint

Use successiv
U
ve subtractioons to get thee result and the
t remaindeer.
Y can assu
You
ume that din is always a positive
p
num
mber.

OBSER
RVATION
N & RESU
ULT:
________________
__________________________________________________________
________________
__________________________________________________________
________________
__________________________________________________________
________________
__________________________________________________________
________________
__________________________________________________________

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Lab10

LAB 10
OBJECTIVE:
State Machines

THEORY:
STATE MACHINE:
An event is an occurrence of a phenomenon at a certain moment in time. The occurrence of the
event itself is assumed to have no duration. Typically, when an event occurs, it affects the state
of an object. A state machine is a model of the behavior of a single object over time and helps
you to understand how that object's state affects its reactions to events.
There are two types of state machines: Mealy machines and Moore machines. You can model
both types of machines in Verilog.
MOORE MACHINES:
In a Moore machine, the outputs are a function of the current state. This implies that the outputs
from the Moore machine are synchronous to the state changes. In moore, it has to wait for one
clock cycle since it changes with the state.

Moore State Machine

MEALY MACHINES:
In a Mealy machine, the outputs are a function of both the state and the inputs. Mealy will be
faster. In the sense that,output will change as soon as the input transition according to the logic.

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Mealy State Machine

A state machine can be broken down into three parts: The state register, the next state logic, and
the output logic.
A state machines can be depicted as shown in Figure below:

LAB TASK # 1:
Designs a vending machine in which the following action are perform:
Release item after 15 cents are deposited
Single coin slot for dimes, nickels
No change
The diagram is shown below:

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Suitable Abstract Representation for the Moore machine is:

Tabulate typical input sequences:

o 3 nickels
o nickel, dime
o dime, nickel
o two dimes

Draw state diagram:

o Inputs: N, D, reset
o Output: open chute
Assumptions:
o Assume N and D asserted for one cycle
o Each state has a self loop for N = D = 0 (no coin)

Lets start with the following steps:

CREATING A PROJECT FOR MOORE MACHINE:

The software we will be using is the Xilinx "ISE Project Navigator", in which you can enter the
Schematic design and simulate its outputs for a specified sequence of inputs. To start up, go to
Start
All Programs
Navigator

Xilinx ISE Design Suite 13.4

ISE Design Tools

Project

The screen shown in Figure 1 appears.

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0

Figure1

At this point,
p
you haave not yet created
c
any project so we
w will startt here. A "prroject" is a set
s of
files, including schem
matic file thhat define thhe circuit com
mponents annd overall ciircuit, along with
d to simulatioons and otheer parts of thhe design perrformed.
auxiliaryy files related
You can either click New Projecct or go to File
F -> New Project. Thhis launches the New Prroject
Wizard as
a shown in Figure 2. Ennter a projecct name and location.
l
We woulld suggest you
y create thhe project in the "My Doocuments" folder,
f
ratherr than the deefault
(C:\ project_name) to
t avoid addding lots of new
n
files innto your maiin 2 directorry. This willl take
wn in Figuree 3.
you to thhe Design Prroperties pop-up as show

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B

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0

Figure 2

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B

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0

Figure 3

In the Deesign Properrties window

w, you can specify
s
the Device
D
Familly and the Device.
This is needed
n
when
n you reach the
t "synthesis" stage in the design and
a implemeentation sincce the
synthesiss stage need
ds to know the
t internal design of thhe specific programmab
p
ble device. When
W
you clickk OK, a Projject Summaary window will pop-up.. Click Finissh.
From thee Project Naavigators puull-down meenus, select Project -> New Sourcce. This launnches
the New Source Wiizard as shoown in Figuure 4. This window
w
can be used to add a varieety of
sources to
t your desig
gn. Select "V
Verilog Moddule" and addd the name of
o your circuuit. The box "Add
to projecct" should bee checked. The
T locationn should apppear as the directory
d
youu selected abbove.
Click Neext, skip the inputout puut pin wizarrd and click next and thhe screen shhown in Figuure 5
appears.

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0

Figure 4

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B

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0

Figure 5
Now heree you can writte the followinng verilog coode for moore state machinne:

module Vending_M
V
Moore( open1, clk,reset,N,D);
output open1;
o
input clk;
input reeset;
input N;
input D;
reg open
n1;
reg [1:0]] state; // sta
ate register
reg [1:0]] next_state;
parametter zero = 0,, five = 1, ten = 2, fifteen = 3;
always @(N
@ or D orr state)
case (staate)
zero: beggin
if (N) next_state = five;
fi
else if (D
D) next_statee = ten;
else nextt_state = zerro;
open1 = 0;
end
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five: begin
if (N) next_state = ten;
else if (D) next_state = fifteen;
else next_state = five;
open1 = 0;
end
ten: begin
if (N) next_state = fifteen;
else if (D) next_state = fifteen;
else next_state = ten;
open1 = 0;
end
fifteen: begin
if (!reset) next_state = fifteen;
else next_state = zero;
open1 = 1;
end
endcase
always @(posedge clk)
if (reset || (!N && !D)) state <= zero;
else state <= next_state;
endmodule
Save file and expand Synthesize XST in process window at the left of the window. Click on
Check Syntax. If
appears, your file completed successfully.

CREATING VERILOG TEST FIXTURE MODULE FOR MOORE

MACHINE:
Select from the Project Navigator window Project -> New Source. The same New Source
Wizard (Figure 4) appears that was used earlier to enter our Verilog module. This time, instead
of selecting Verilog Module, select Verilog Test Fixture. Name the file state_tf (to distinguish it
from the actual state file) and click Next. New windows will pop-up asking you which file
describes the circuit you want to test. Select the file and then click Next. The New Source Wizard
now shows a summary page. Click Finish.
Clicking on Finish, the Project Navigator screen reappears and you will see that the wizard has
already generated some more code, for a new entity called state_tf as shown in Figure 6. There
may be some compiler errors that appear in the console window. Ignore them because we are

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going to edit this file. It is not necessary for you to understand the semantics of this entity at this
stage. Simply write the following code.
module stat_tf;
// Inputs
reg clk;
reg reset;
reg N;
reg D;
// Outputs
wire open1;
// Instantiate the Unit Under Test (UUT)
Vending_Moore uut (
.open1(open1),
.clk(clk),
.reset(reset),
.N(N),
.D(D)
);
parameter PERIOD=100;
always begin
clk=1;
#(PERIOD/2)
clk=0;
#(PERIOD/2);
end
initial begin
// Initialize Inputs
reset = 1;
N = 0;
D = 0;
// Wait 100 ns for global reset to finish
#100 reset = 0; N=1; D=0;
#100 N=0; D=1;
#100 N=0; D=0;
end
endmodule
Save the file and expand ISim Simulator. Double click on Behavioral Check Syntax. When
there is no error, a
VLSILAB

appears next to it, click Simulate Behavioral Mode, ISim (0.87xd)

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0

window appear in which

w
input and
a output waves
w
are shhown with Name
N
and Vales
V
as show
wn in
figure 7. Verify the output.
o

Figure 6

Now cheeck and verrify the outpput, also tabbulate the typical input sequences as
a describe in the
objectiveofthistaskalsoadd and explain
e
the screen
s
shot of
o your task design simuulation.

LAB TASK
T
# 2:
2
Design the same vending
v
maachine mechhanism witth
m
Mealy machines.
Up till now you can un
nderstand the difference beetween mealy
N follow thhe same steps as in task 1
And moree machines. Now
And writte the follow
wing code inn Verilog moodule for thiis
machine.

module vending_Me
v
ealy (open, Clk, Reset, N, D);
input Clk, Reset, N,, D; output open;
reg open
n; reg state; // state regiister
reg next__state; reg next_open;
n
parametter zero = 0,, five = 1, ten = 2, fifteen = 3;
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always @(N or D or state)

case (state)
zero: begin
if (N) begin
next_state = five; next_open = 0;
end
else if (D) begin
next_state = ten; next_open = 0;
end
else begin
next_state = zero; next_open = 0;
end
end
five: begin
if (N) begin
next_state = ten; next_open = 0;
end
else if (D) begin
next_state = fifteen; next_open = 1;
end
else begin
next_state = five; next_open = 0;
end
end
ten: begin
if (N) begin
next_state = fifteen; next_open = 1;
end
else if (D) begin
next_state = fifteen; next_open = 1;
end
else begin
next_state = ten; next_open = 0;
end
end
fifteen: begin
if (!Reset) next_state = fifteen;
else next_state = zero;
next_open = 1;
end
endcase
always @(posedge clk)
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if (Reset || (!N && !D)) begin state <= zero; open <= 0; end
else begin state <= next_state; open <= next_open; end
endmodule

CREATING A VERILOG TEST FIXTURE FOR MEALY MACHINE:

Follow the same steps as in previous labs for the simulation part and write the following code in Verilog
test fixture and verify the output according to the typical input sequence as describe in task 1.

module Mealy_tf;
// Inputs
reg Clk;
reg Reset;
reg N;
reg D;
// Outputs
wire open1;
// Instantiate the Unit Under Test (UUT)
Vending_Mealy uut (
.open1(open1),
.Clk(Clk),
Reset(Reset),
.N(N),
.D(D)
);
parameter PERIOD=100;
always begin
Clk=1;
#(PERIOD/2)
Clk=0;
#(PERIOD/2);
end
initial begin
// Initialize Inputs
Reset = 1;
N = 0;
D = 0;
// Wait 100 ns for global reset to finish
#100 Reset=0; N=1; D=0;
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#100 N=0; D=1;

#100 N=1; D=0;
#100 N=0; D=0;
end
endmodule
Now check and verify the output, also tabulate the typical input sequences as describe in the
objectiveofthistaskalsoadd and explain the screen shot of your task design simulation.

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LAB ASSIGNMENTS
Lab Assignment:
Traffic light controller.
A busy highway is intersected by a little used farmroad
Detectors C sense the presence of cars waiting on the farmroad
with no car on farmroad, light remain green in highway direction
if vehicle on farmroad, highway lights go from Green to Yellow to Red, allowing the
farmroad lights to become green
these stay green only as long as a farmroad car is detected but never longer than a set interval
when these are met, farm lights transition from Green to Yellow to Red, allowing highway to
return to green even if farmroad vehicles are waiting, highway gets at least a set interval as
green
Assume you have an interval timer that generates:
a short time pulse (TS) and
a long time pulse (TL),
in response to a set (ST) signal.
TS is to be used for timing yellow lights and TL for green lights
Highway/farm road intersection is shown as follows:

Tabulation of Inputs and Outputs

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Lab10

Inputs
reset

Description
place FSM in initial state

Outputs
HG, HY, HR

detect vehicle on the farm road

FG, FY, FR

TS

short time interval expired

ST

TL

long time interval expired

Description
assert green/yellow/red
highway lights
assert green/yellow/red
highway lights
start timing a short or long
interval

Tabulation of unique states some light configurations imply others

state description
S0
highway green (farm road red)
S1
highway yellow (farm road red)
S2
farm road green (highway red)
S3
farm road yellow (highway red)
State Diagram is shown below:

Consider state assignments:

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Lab10

Coding for Verilog Module is given below, your task is to complete the code according to the
senario describe above.
module traffic (ST, Clk, Reset, C, TL, TS);
input Clk, Reset, C, TL, TS; output ST;
reg ST; reg state;
reg next_state; reg next_ST;
parameter S0 = 0, S1 = 1, S2 = 2, S3 = 3;
always @(C or TL or TS or state)
case (state)
S0: if (!(TL && C)) begin
next_state = S0; next_ST = 0;
else if (TL || C) begin
next_state = S1; next_ST = 1;
end

endcase
always @(posedge Clk)
if (Reset) begin state <= S0; ST <= 0; end
else begin state <= next_state; ST <= next_ST; end
endmodule

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OBSERVATION & RESULT:

__________________________________________________________________
__________________________________________________________________
__________________________________________________________________
__________________________________________________________________
_______________________________________________________________

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Lab11

LAB 11
OBJECTIVES
IntroductiontoVirtex5DevelopmentSystem.

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THEORY
Xilinx Virtex 5 Development Kit Specification

Xilinx Virtex-5 LX50T FPGA in a 1136-pin BGA package

256Mbyte DDR2 SODIMM with 64-bit wide data

10/100/1000 Ethernet PHY and RS-232 serial port

Multiple USB2 ports for programming, data transfer, and hosting applications

HDMI video with resolution up to 1600x1200 & 24-bit color.

AC-97 Codec with 48KHz sampling and line-in, line-out, microphone and headphone ports

Real time power monitors on all power rails

32Mbyte Numonyx StrataFlash for configuration and user-data storage

100MHz fixed oscillator and (up to) 400MHz programmable clock generator

112 FPGA I/Os routed to expansion connectors (two high-speed parallel VHDC
connectors and four 8-pin headers)

GPIO includes 8 LEDs, 2 buttons, two-axis navigation switch, 8 slide switches, and a 16x2
character LCD

20W power supply, USB cable, and protective plexiglass covers

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LAB TASK # 1:
Objective- Design Parallel to serial converter in Xilinx ISE 13.4 environment using Verilog
HDL.

1. Starting the ISE Software

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2. Create New Project

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3. Project Name & Working Directory

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4. Select Spartan 3E Starter Board

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5. Add New Design Source File

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6. Verilog HDL Source File View

7. Write Verilog HDL Code

Write the following Verilog Code in the editor
module Parallel_To_Serial(clk, reset, strobe, data_in, data_out);
input [3:0] data_in;
input
clk, reset, strobe;
output data_out;
wire data_out;
reg [3:0] temp_data;
always @(posedge clk) begin
if(reset)
temp_data <= 4'b0000;
else if(strobe)
temp_data <= data_in;
else
temp_data[3:0] <= {temp_data[2:0],1'b0};
end
assign data_out = temp_data[3];
endmodule
Write these lines before endmodule and Save the Parallel_To_Serial.v file

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8. Verilog HDL Source File View

9. Check Syntax

Checking the Syntax of the New Parallel_to_Serial ModuleVerify that Implementation is

selected at the top of design window.
Select the Parallel_to_Serial design source in the Sources window to display the related
processes in the Processes window.
Click the + next to the Synthesize-XST process to expand the process group.
Double-click the Synthesize-XST process.
Close the HDL file.

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10. Perform Behavioral Simulation

Verifying Functionality using Behavioral Simulation

Create the test bench as follows:

Select the Parallel_To_Serial HDL file in the Sources window.
Create a new test bench source by selecting Project New Source.
In the New Source Wizard, select Verilog Test Fixture as the source type, and
type ParallelToSerialConverter_TB in the File Name field.

Click Next.
11. Behavioral Simulation

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12. Select Design for Behavioral Simulation

The Associate Source page shows that you are associating the test bench with the source file
Parallel_To_Serial. Click Next.
The Summary page shows that the source will be added to the project, and it displays the
source directory, type and name. Click Finish.

Associate Source

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13. Test Bench Summary

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14. Verilog Simulation Construct

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Clock Declaration

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Stimulus Declaration

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Simulate the Design

Simulating Design Functionality

Verify that Behavioral Simulation and ParallelToSerialConverter_TB are selected
in the Sources window.
In the Processes tab, click the + to expand the ISim Simulator process and
double-click the Behavioral Check Syntax process.
Then double-click on the Simulate Behavioral Model
The ISE Simulator opens and runs the simulation to the end of the test bench.

Test Fixture File Syntax Check

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Behavioral Simulation Verification

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15. Implementing the Design

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After simulation verification, we will implement design on FPGA.

Select the Parallel_To_Serial source file in the Sources window.

Double-click the Implement Design process in the Processes tab.

Notice that after Implementation is complete, the Implementation processes have a green
check mark next to them indicating that they completed successfully without errors or
warnings.

Design Implementation

View Pinout Report

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First, review the Pinout Report from the previous implementation by doing the following:

Locate the Performance Summary table near the bottom of the Design Summary.

Open the Design Summary by double-clicking the View Design Summary process in the
Processes tab.

Select the Pinout Report and click on the Signal Name column header to sort the signal
names. Notice the Pin Numbers assigned to the design ports in the absence of location
constraints.

User Constraint File Creation

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Specify the pin locations for the ports of the design so that they are connected correctly on
the Spartan 3E/ Virtex development kits.

To constrain the design ports to package pins, do the following:

Verify that Parallel_To_Serial is selected in the Source window.
Create a new source by selecting Project New Source.
In the New Source Wizard, select Implementation Constraints File as the source
type, and type ParallelToSerial_UCF in the File Name field.
Click Next.

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16. Assigning Pin Location

Write the following constraints in UCF file;
//Clock constraints
NET "clk" LOC = "AG18"; # Bank = 4, Pin name = IO_L6P_GC_4, Type = GCLK, Sch name
= GCLK0
//Reset and Strobe Pins
NET "reset" LOC = "J19"; # Bank = 3, Pin name = IO_L3N_GC_3,

Sch name = SW0

NET "strobe" LOC = "L18"; # Bank = 3, Pin name = IO_L1N_CC_GC_3, Sch name = SW1
//Datain pins
NET "data_in[0]" LOC = "K18"; # Bank = 3, Pin name = IO_L3P_GC_3,

Sch name = SW2

NET "data_in[1]" LOC = "H18"; # Bank = 3, Pin name = IO_L0N_CC_GC_3, Sch name =
SW3
NET "data_in[2]" LOC = "H17"; # Bank = 3, Pin name = IO_L0P_CC_GC_3, Sch name =
SW4
NET "data_in[3]" LOC = "K17"; # Bank = 3, Pin name = IO_L1P_CC_GC_3, Sch name =
SW5
//Dataout pins
NET "data_out" LOC = "AG8"; # Bank = 22, Pin name = IO_L18P_22,

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Select File Save.

Notice that, the Implementation processes have a orange check mark with ? sign next to
them indicating that it is required to run this process again.

Final UCF

Re-Implement Design Process

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Re-implement the design and verify that the ports of the Parallel_To_Serial design are
routed to the package pins specifcied in the UCF.

Re-implement the design by double-clicking the Implement Design process.

Select the Pinout Report again and select the Signal Name column header to sort the signal
names.

Verify that signals are now being routed to the correct package pins.

Close the Design Summary.

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Generate Bit File

Select Implementation in the top menu of Sources window.

Select Parallel_To_Serial in the Sources window.

In the Processes window, double click the Generate Programming File processes to create
the bit stream of the design.

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Download Design to FPGA Board

This is the last step in the design verification process. This section provides simple
instructions for downloading the Parallel_To_Serial design to the Spartan 3E Development
board.

Connect the 5V DC power cable to the power input on the demo board.

Connect the download JTAG cable between the PC and demo board.

Start iMPACT Tool

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Run Boundry Scan

Initialize JTAG Chain

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Assign Configuration File

Assign New Configuration File

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Decline Configuration for PROM

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Bypass Configuration for System ACE

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Bypass Configuration for PROM

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Apply Device Setting Properties

Right Click on FPGA and Click at Program

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Downloading of Design on FPGA

Download Completion

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The Xilinx WebTalk Dialog box may open during this process. Click Decline.

Select Disable the collection of device usage statistics for this project only and click OK.

iMPACT opens and the Configure Devices dialog box is displayed.

In the Welcome dialog box, select Configure devices using Boundary-Scan (JTAG).

Verify that Automatically connect to a cable and identify Boundary-Scan chain is selected.

Click Finish.

If you get a message saying that there are two devices found, click OK to continue.

The devices connected to the JTAG chain on the board will be detected and displayed in the
iMPACT window.

The Assign New Configuration File dialog box appears. To assign a configuration file to
the XC3S500E device in the JTAG chain, select the Parallel_To_Serial.bit file and click
Open.

If you get a Warning message, click OK.

Select Bypass to skip any remaining devices.

Right-click on the XC3S500E device image, and select Program... The Programming
Properties dialog box opens.

Click OK to program the device.

When programming is complete, the Program Succeeded message is displayed.

Close iMPACT without saving.

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LAB ASSIGNMENTS
Lab Assignment:
Write UCF file for 4-bit Ripple Carry Counter which we design in Lab 7.

OBSERVATION & RESULT:

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