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School of VLSI Technology (Bengal Engineering and Science University at Shibpur, India)
Dept. of Electronics and Telecommunication (Bengal Engineering and Science University at Shibpur, India)
3
Dept. of Electrical and Computer Engineering (University of Illinois at Chicago, USA)
4
Dept. of Information Technology (Bengal Engineering and Science University at Shibpur, India)
*
E-mail: sudip_etc@yahoo.co.in
VLSI
Architecture,Reversible
I.
Watermarking,
INTRODUCTION
RELATED WORKS
Atransform
MODULE 1
Btransform
A
OUTA
B
Atransform
Btransform
X
Atransform(9:0)
MODULE 2
Btransform
X
Y
Z
OUTB
MODULE 3
Y
Z
(1)
(2)
SUB
SUB
SUB
SUB
Btransform
B
A
B
A
Atransform
256 byte
RAM
Address decoder
2.
DECODER:
The decoder block is structured similarly like the encoder
block. It is comprised of the three modules, the signal
generation block, the inverse transform block, and the image
and watermark extraction block. The entire decoder
architecture is given in Fig. 5. Following sections from (i)(iii) give a detailed hardware description of the individual
modules of the decoder.
Control Signal:
Similar to the encoder part, the control signals are generated
from the 8-bit input data received from the transmitter i.e. the
encoder. The watermark image data as well as the
transformation information has been embedded into the LSB
of the transmitted pairs. Therefore, the preliminary task of this
module is to extract LSB of both the received pairs. The LSB
of the WIA received signal contained the transformation
information and WIB contained the watermark data. The
(3)
(4)
Different modules
Pixel
Control
transform signal
Watermark Watermarking
embedding
encoder
432
17
19
528
268
10
303
152
23
50
230
Different modules
pixel inverse
transform
control
signal
Watermark
extraction
(decoder)
48
56
217
13
613
125
347
42
20
37
CONCLUSION