MICROELECTRONICS SIMULATIONS LABORATORY

DEPT OF ELECTRICAL ENGINEERING, IIT BOMBAY

ASSIGNMENT 4 SMALL AREA MOSFET

SIMULATION OF SMALL AREA MOSFET (SUB 100nm)
NAME INDRANIL CHAKRABORTY
ROLL NO- 143070072

PROGRAMME M.TECH

DEPT ELECTRICAL ENGINEERING

SPECIALIZATION MICROELECTRONICS

ACKNOWLEDGEMENTS:
SIMULATION SOFTWARE SENTAURUS
BOOKS REFERRED - Silicon VLSI
Technology (Plummer)

Firstly, we scale down the MOSFET designed in the previous assignment to sub-100 nm and analyze its
characteristics.

SPROCESS
We simply reduce the gate length to 90nm and reduce the oxide thickness to 1.5nm, and do not optimize
the device any further.

We observe that the effective Gate Length has reduced significantly.

SDEVICE

Threshold Voltage

Vtlin
We plot the ID-VG curve at low VDS(0.05V) and find out the linear threshold voltage by max-gm method.

Observed Vtlin:
= 0.508

= 0.483

Vtsat
We plot the ID-VG curve at high VDS(1.2V) and find out the saturation threshold voltage by max-gm
method.

Observed Vtsat:
= 0.438
= 0.55
= 0.6

= 1.09

So, we observe that the On current and Off current do not meet specifications, and hence we have to
optimize the device.

OPTIMIZATION
We optimize the above device in the following way:
1) Deep Boron Implant: Deep Boron implants were done
implant Boron dose=3.15e14<cm-2> energy=200<keV> tilt=0 rotation=0
implant Boron dose=0.55e14<cm-2> energy= 80<keV> tilt=0 rotation=0

2) Vt adjust implant: Shallow Boron implants were done to adjust the threshold voltage around
0.3-0.5V
implant Boron dose=0.8e13<cm-2> energy= 28<keV> tilt=0 rotation=0
3) LDD implant: Lightly doped drain gives us shallow drain junctions in the overlap region of drain
and gate. Hence, we applied this implant so as to reduce the hot carrier effect by reducing the
electric field in the channel near the drain region.
implant Arsenic dose=3.1e14<cm-2> energy=2<keV> tilt=0 rotation=0
4) Halo Implants: Halo Boron implants were done to avoid Punch through of the depletion region
as the drain and source are quite near to each other.
implant Boron dose=1e13<cm-2> energy=3<keV>
rotation=0
implant Boron dose=1e13<cm-2> energy=3<keV>
rotation=90<degree>
implant Boron dose=1e13<cm-2> energy=3<keV>
rotation=180<degree>
implant Boron dose=1e13<cm-2> energy=3<keV>
rotation=270<degree>
diffuse temperature=1050<C> time=5.0<s>

tilt=30<degree> \
tilt=30<degree> \
tilt=30<degree> \
tilt=30<degree> \

5) Nitride Spacer Creation: Spacer is the created so as to separate the deep source and drain
implants from the gate or channel region.
deposit material= {Nitride} type=isotropic
time=1 rate= {0.08}
etch
material= {Nitride} type=anisotropic time=1 rate= {0.096}
etch
material= {Oxide}
type=anisotropic time=1 rate= {0.01}
6) Deep Source/Drain implants: Deep implants are done using a slight tilt so as to introduce the
implants ions at an inclined angle away from the Gate.
implant Arsenic dose=1e15<cm-2> energy=6<keV> tilt=7<degree> \
rotation=-90<degree>

FINAL DEVICE

SPECIFICATIONS:
Effective Gate Length = 68nm
Oxide Thickness = 1.5nm
Source/Drain Depth: 40nm

DEVICE CHARACTERISTICS
EXTRACTION of Vt:
We have used a script to find out the threshold voltage by the max-gm method using the
INSPECT tool
load_library EXTRACT
set Vt [ExtractVtgm Vtgm <Curve> nMOS]
1) Threshold Voltage (low VDS)(Vtlin)(VDS = 0.05V)

By max-gm method, we observe,

= 0.335

= 0.311

2) Threshold Voltage (high VDS)(Vtlin)(VDS = 1.2V)(n=1.3)

ID-VG

ID1/n-VG(n=1.3)

= 0.306

3) Vt roll off
At L=80nm
ID1/n-VG curve(n=1.4)

= 0.27

At L=70nm
ID1/n-VG curve(n=1.4)

L
90
80
70

= 0.251
0.306
0.277
0.251

Vt roll off

4) Ion/Ioff
LOGARITHMIC PLOT OF ID-VG(at Hight VDS)

= 11.9
= 1

= 84033.61

5) EFFECT of DIBL
We observed ID-VG curves at low VDS and high VDS to observe the effect of drain induced
barrier lowering. We observed the following plots:

90nm

180nm

DIBL is a short channel effect which causes the drain voltage to take a larger control of the drain current
as the length shortens. We observe that for this length, the gap between the two current plots is much
higher than that of a 180nm device.

6) Gate Leakage current

We observe Gate leakage current for a low VDS. We turn on the Direct Tunneling model in
our Physics section to observe this effect:
IG-VG curve

= 0: 2.21 1017

= 1.2: 1.374 1011

7) FAMILY OF ID-VD curves:

We observed ID-VD curves at VG = 0.4, 0.6,0.8,1,1.2V

We observe that with increasing VG, ID-VD family of curves rises upwards, because the current increases
with rising VG.

8) FAMILY OF ID-VG curves:

We observed ID-VG curves at VD = 0.4, 0.6,0.8,1,1.2V

We observe that with increasing VD, ID-VG family of curves rises upwards as the current increases with
rising VD.

9) Low-field mobility:
We plot mobility by distance for low VDS(VDS = 50mV) and observe the mobility in the channel. So, we
take a X-cut near the channel to find out the low field mobility.

We observe a maxima in the channel region in the mobility curve. That is the value of low field mobility
required.
= 4262 /

10) RSD and L

We observed Ron for different VGS at different values of L(70nm, 80nm, 90nm) and plotted fit
curves to obtain RSD and L.

VGS
0.4
0.6
0.8
1
1.2

Ron

70
80
90
70.0
80.0
90.0
70.0
80.0
90.0
70.0
80.0
90.0
70.0
80.0
90.0

3143.258
3626.698
4123.569
1276.494
1413.317
1584.811
868.3721
964.6674
1039.2917
707.9145
750.469
792.8202
3143.258
3626.698
4123.569

= 414

= 25.459

11) Effective Mobility vs Effective Electric field

We plot the effective mobility by effective electric field in the channel by turning on the
effective mobility option
CurrentPlot {
PMIModel (
Name="EffectiveMobility"
Start=(-0.033,0,0)
)
}
At high VDS (1.2V), we observe the following plot.

We observe that the effective mobility decreases at low fields, and increases at high fields.