Chapter 1

Computer System
Overview
BIT1213 OPERATING SYSTEMS

Objectives

Basic elements of computer

Instruction Execution

Interrupts

The Memory Hierarchy

Cache Memory

Multiprocessor and multicore organization

Operating System
Operating System is a program or software that help to :-

Exploits the hardware resources of one or more

processors

Provides a set of services to system users

Manages secondary memory and I/O devices

CPU

Operating System like a middleman

Operating System

Application

Basic Elements of Computer

Processor

Main
Memory

I/O
Modules

System
Bus

Data Bus
COntroller Bus
Address Bus

Processor
Controls the
operation of the
computer

Performs the data

processing
functions

What are the main part of processor :- ALU ( arithmetic logic unit), Control unit, Register

Referred to as the
Central Processing
Unit (CPU)

AMD
Intel
=Pins cant be touched with hand

Main Memory
Main Memory = RAM (random access memory)

Volatile

Contents of the memory is lost when the computer

is shut down

Also referred to as real memory or primary

memory

Cache is the fastest access

Access time is faster compared to hard disc

I/O Modules
modules are attached to motherboard

storage (e.g.
hard drive)
Moves data between
the computer and
external environments
such as:

communication
s equipment
terminals

System Bus

Provides for
communication
among
processors,
main memory,
and I/O
modules

When execute then only each instruction is stored in main memory.

Then each cycle CPU will fetch instruction and execute the statement
All go through system bus (wire).

Instruction Execution

A program consists of a set of instructions

stored in memory

START

Fetch Stage

Execute Stage

Fetch Next
Instruction

Execute
Instruction

Figure 1.2 Basic Instruction Cycle

HALT

Instruction Fetch and Execute

The processor fetches the instruction from memory

Program counter (PC) holds address of the instruction to be

fetched next
PC is incremented after each fetch

Fetched instruction is loaded into Instruction Register (IR)

Processor interprets the instruction and performs required action:

Processor-memory
Processor-I/O
Data processing
Control

Fetch Stage
Memory
300 1 9 4 0
301 5 9 4 1
302 2 9 4 1

Execute Stage

CPU Registers
Memory
300 1 9 4 0
3 0 0 PC
AC 301 5 9 4 1
1 9 4 0 IR 302 2 9 4 1

940 0 0 0 3
941 0 0 0 2

940 0 0 0 3
941 0 0 0 2

Step 1

Step 2

Memory
300 1 9 4 0
301 5 9 4 1
302 2 9 4 1

CPU Registers
Memory
300 1 9 4 0
3 0 1 PC
0 0 0 3 AC 301 5 9 4 1
5 9 4 1 IR 302 2 9 4 1

CPU Registers
3 0 2 PC
0 0 0 5 AC
5 9 4 1 IR

940 0 0 0 3
941 0 0 0 2

940 0 0 0 3
941 0 0 0 2

Step 3

Step 4

Memory
300 1 9 4 0
301 5 9 4 1
302 2 9 4 1

CPU Registers
3 0 1 PC
0 0 0 3 AC
1 9 4 0 IR

CPU Registers
Memory
300 1 9 4 0
3 0 2 PC
0 0 0 5 AC 301 5 9 4 1
2 9 4 1 IR 302 2 9 4 1

3+2=5

CPU Registers
3 0 3 PC
0 0 0 5 AC
2 9 4 1 IR

940 0 0 0 3
941 0 0 0 2

940 0 0 0 3
941 0 0 0 5

Step 5

Step 6

Figure 1.4 Example of Program Execution

(contents of memory and registers in hexadecimal)

1. The PC contains 300, the address of the first

instruction. This instruction (the value 1940 in
hexadecimal) is loaded into the IR and the PC
is incremented. Note that this process involves
the use of a memory address register (MAR)
and a memory buffer register (MBR). For
simplicity, these intermediate registers are not
shown.
2. The first 4 bits (first hexadecimal digit) in the IR
indicate that the AC is to be loaded from
memory. The remaining 12 bits (three
hexadecimal digits) specify the address, which
is 940.
3. The next instruction (5941) is fetched from
location 301 and the PC is incremented.
4. The old contents of the AC and the contents of
location 941 are added and the result is stored
in the AC.
5. The next instruction (2941) is fetched from
location 302 and the PC is incremented.
6. The contents of the AC are stored in location
941.

Interrupts

Interrupt the normal sequencing of the processor

Provided to improve processor utilization

most I/O devices are slower than the processor

processor must pause to wait for device
wasteful use of the processor

Table 1.1

Classes of Interrupts

Program

Generated by some condition that occurs as a result of an

instruction execution, such as arithmetic overflow, division
by zero, attempt to execute an illegal machine instruction,
and reference outside a user's allowed memory space.

Timer

Generated by a timer within the processor. This allows the

operating system to perform certain functions on a regular
basis.

I/O

Generated by an I/O controller, to signal normal

completion of an operation or to signal a variety of error
conditions.

Hardware
failure

Generated by a failure, such as power failure or memory

parity error.

User
Program

I/O
Program
4

Figure 1.5a

I/O
Command

WRITE

User
Program
1

WRITE

5
2a

END
2

Flow of Control
Without
Interrupts

2b

WRITE

WRITE

3a

3
3b

WRITE

WRITE
(a) No interrupts

(b) Inter

User
Program

I/O
Program
4

I/O
Command

WRITE

User
Program

I/O
Program
4

WRITE

I/O
Command

User
Program
1

WRITE

5
2a

Figure 1.5b

END

2
Interrupt
Handler

2b

WRITE

WRITE

Short I/O Wait

WRITE

END
3a

3
3b

WRITE

WRITE
(a) No interrupts

(b) Interrupts; short I/O wait

WRITE

(c) In

No interrupts

I/O
Program
4
I/O
Command

User
Program

I/O
Program
4

WRITE

I/O
Command

User
Program

I/O
Program
4

WRITE

I/O
Command

Figure 1.5c
2a

END

2
Interrupt
Handler

2b

Long I/O Wait

WRITE

Interrupt
Handler
5

WRITE

END

END

3a

3
3b

WRITE
(b) Interrupts; short I/O wait

WRITE
(c) Interrupts; long I/O wait

User Program

Interrupt Handler

1
2

Interrupt
occurs here

i
i+1

Figure 1.6 Transfer of Control via Interrupts

Fetch Stage

Execute Stage

Interrupt Stage

Interrupts
Disabled
START

Fetch next
instruction

Execute
instruction

Interrupts
Enabled

Check for
interrupt;
initiate interrupt
handler

At every instruction cycle must check for

interrupt

HALT

Figure 1.7 Instruction Cycle with Interrupts

Hardware
Device controller or
other system hardware
issues an interrupt

Processor finishes
execution of current
instruction

Software

Save remainder of
process state
information

Process interrupt
Processor signals
acknowledgment
of interrupt
Restore process state
information
Processor pushes PSW
and PC onto control
stack
Restore old PSW
and PC
Processor loads new
PC value based on
interrupt

Figure 1.10 Simple Interrupt Processing

Multiple Interrupts
An interrupt occurs while
another interrupt is being
processed

Two approaches:

e.g. receiving data from

a communications line
and printing results at
the same time

disable interrupts while

an interrupt is being
processed
use a priority scheme

Memory Hierarchy

Major constraints in memory

amount
speed
expense

Memory must be able to keep up with the processor

Cost of memory must be reasonable in relationship

to the other components

Memory Relationships

Faster access
time =
greater cost
per bit

Greater capacity =
smaller cost per bit
Greater capacity
= slower access
speed
go through many slot

The Memory Hierarchy

lower level

Going down the

hierarchy:

decreasing cost per bit

increasing capacity
increasing access time
decreasing frequency of
access to the memory by the
processor

Inb
Me oard
mo
ry

Ou
t
Sto boar
rag d
e

Of
S t o f - li n e
rag
e

gRe r s
e
i st
Ca

e
ch
in
M a or y
m
Me

sk
Di
tic
ne OM
g
M a D- R W
C D -R W
R M
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DD V D- R A y
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DV lu-R
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higher level
Figure 1.14

The Memory Hierarchy

Principle of Locality
stored in low level - easier to access

Memory references by the processor tend to cluster

Data is organized so that the percentage of accesses

to each successively lower level is substantially less
than that of the level above

Can be applied across more than two levels of

memory

Secondary
Memory
hard disc - permanent memory

Also referred to
as auxiliary
memory
external
nonvolatile
used to store
program and data
files

Cache Memory

Invisible to the OS

Interacts with other memory management hardware

Processor must access memory at least once per instruction

cycle

Processor execution is limited by memory cycle time

Exploit the principle of locality with a small, fast memory

Block Transfer
Word Transfer

Main Memory

Cache

CPU
Fast

Slow

(a) Single cache

Level 2
(L2) cache

Level 1
(L1) cache

CPU
Fastest

Fast

Level 3
(L3) cache
Less
fast

(b) Three-level cache organization

Figure 1.16 Cache and Main Memory

Main
Memory
Slow

Line
Number Tag
0
1
2

Block

Memory
address
0
1
2
3

Block 0
(K words)

C-1
Block Length
(K Words)

(a) Cache

Block M 1
2n - 1
Word
Length

(b) Main memory

Figure 1.17 Cache/Main-Memory Structure

START
RA - read address
Receive address
RA from CPU

Is block
containing RA
in cache?

Access main
memory for block
containing RA

No

Yes
Allocate cache
slot for main
memory block

Fetch RA word
and deliver
to CPU

Load main
memory block
into cache slot

Deliver RA word
to CPU

DONE

Figure 1.18 Cache Read Operation

Symmetric Multiprocessors (SMP)

A stand-alone computer system with the

following characteristics:

two or more similar processors of comparable capability

processors share the same main memory and are
interconnected by a bus or other internal connection scheme
processors share access to I/O devices
all processors can perform the same functions
the system is controlled by an integrated operating system
that provides interaction between processors and their
programs at the job, task, file, and data element levels

SMP Advantages
Performance

Scaling

a system with multiple

processors will yield greater
performance if work can be
done in parallel

vendors can offer a range of

products with different price
and performance
characteristics

Availability

Incremental Growth

the failure of a single

processor does not halt the
machine

an additional processor can

be added to enhance
performance

Processor

Processor

L1 Cache

Processor

L1 Cache

L2 Cache

L1 Cache

L2 Cache

L2 Cache

System Bus

Main
Memory

I/O
Subsystem

I/O
Adapter

I/O
Adapter

I/O
Adapter

Figure 1.19 Symmetric Multiprocessor Organization

Multicore Computer

Also known as a chip multiprocessor

Combines two or more processors (cores) on a single

piece of silicon (die)

each core consists of all of the components of an

independent processor

In addition, multicore chips also include L2 cache

and in some cases L3 cache

Core 0

Core 1

Core 2

Core 3

Core 4

Core 5

32 kB 32 kB
L1-I L1-D

32 kB 32 kB
L1-I L1-D

32 kB 32 kB
L1-I L1-D

32 kB 32 kB
L1-I L1-D

32 kB 32 kB
L1-I L1-D

32 kB 32 kB
L1-I L1-D

256 kB
L2 Cache

256 kB
L2 Cache

256 kB
L2 Cache

256 kB
L2 Cache

256 kB
L2 Cache

256 kB
L2 Cache

12 MB
L3 Cache
DDR3 Memory
Controllers

3 8B @ 1.33 GT/s

QuickPath
Interconnect

20b @ 6.4 GT/s

Figure 1.20 Intel Core i7-990X Block Diagram

Review Questions
1.

List and briefly define the four main elements

of a computer.

2.

What is cache memory?

3.

What is the difference multi-core and

multiprocessing?

Review Questions
4. Suppose the hypothetical processor of Figure 1.3 also has two I/O
instructions:
0011 Load AC from I/O
0111 Store AC to I/O
In these cases, the 12-bit address identifies a particular external device.
Show the program execution (using format of Figure 1.4) for the
following program:
1.
Load AC from device 5.
2.
Add contents of memory location 940.
3.
Store AC to device 6.
Assume that the next value retrieved from device 5 is 3 and that location
940 contains a value of 2.