DEPARTMENT OF ELECTRONICS & COMM.ENGG.

B.I.T., MESRA, RANCHI

EC6111

VLSI DESIGN

Module 1:
Circuits and System Representation:
Behavioural, structural and physical representation, Example of a triangular waveform generator
and its behavioural, Structural and physical description.
(6)
Text Book:
1. Principle of CMOS VLSI Design A System Perspective, Weste Neil H E & Eshraghian
K, Pearson Education, 1993 Chapter 1 (1.6-1.7)
Module 2:
Basic CMOS Technology:
Basic n-well CMOS Process, P-well process, Twin-tub process, Silicon on insulator, CMOS
process enhancements, Metal interconnect, Polysilicon/ refractory metal interconnect, Local
interconnect, Circuit elements like resistors, Capacitors, EAROM, Bipolar transistors and thin
film transistor.
(7)
Text Book:
1. Principle of CMOS VLSI Design A System Perspective, Weste Neil H E & Eshraghian
K, Pearson Education, 1993 Chapter 3 (3.2-3.3)
Module 3:
Layout Design Rules:
Layer representations, CMOS n-well rules, Design rule backgrounder, Layer assignment, Latchup problem, Latch-up triggering, Internal latch-up prevention techniques, Resistance estimation,
and Capacitance estimation.
(6)
Text Book:
1. Principle of CMOS VLSI Design A System Perspective, Weste Neil H E & Eshraghian
K, Pearson Education, 1993 Chapter 3 (3.4-3.5.4); Chapter 4 (4.2-4.3.2)
Module 4:
Basic Physical Design of Simple Logic Gates:
Invertor, NAND and NOR gates, Complex logic gates layout, CMOS standard cell design, Gate
array layout, Sea-of-gates layout, General CMOS logic gate layout guidelines, Layout
optimisation for performance, Transmission gate layout consideration, 2-input multiplexers, I/O
structures, VDD and VSS pads, Output & input pads, Tri-state and bi-directional pads,
Miscellaneous pads.
(7)

Text Book:
1. Principle of CMOS VLSI Design A System Perspective, Weste Neil H E & Eshraghian
K, Pearson Education, 1993 Chapter 5(5.3.1-5.3.10; 5.6.1-5.6.7)
Module 5:
CMOS Analogue Design Method:
Op amp design, OP amp as a comparator, Sample and hold, Analogue layout considerations,
Transistor layouts, Centroid design, Capacitor matching, rResistor layout, Noise consideration.
(6)
Text Book:
1. Analogue Integrated Circuits Design, Johns D and Martin K, John Wiley & Sons, 1997.
Chapters 2.4; 5.1; 7.1-7.2; 8.1-8.2
Module 6:
CMOS Digital Design Methods:
Structured design strategies, Hierarchy, Regularity, Modularity, Locality, Design options like PL,
Re-programmable gate arrays, Standard Cell design, Behavioural synthesis, RTL synthesis,
Logic optimisation, Structural to layout synthesis, Placement, Routing
(7)
Text Book:
1. Principle of CMOS VLSI Design A System Perspective, Weste Neil H E & Eshraghian
K, Pearson Education, 1993 Chapter 6 (6.2; 6.3.1;6.3.4; 6.3.6;6.4)
Module 7:
CMOS Subsystem Design:
Single bit address, Bit parallel adder, Transmission gate adder, Asynchronous counter,
Synchronous counter, RAM, Finite state machines, Multilevel logic.
(6)
Text Book:
1. Principle of CMOS VLSI Design A System Perspective, Weste Neil H E & Eshraghian
K, Pearson Education, 1993 Chapter 8 (8.2.1;8.2.5;8.3;8.4.1)

TUTORIAL
EC6111

VLSI DESIGN

Module 1:
1.

Explain the operation of n-channel FET.

2.

Derive the expression for threshold voltage including the body effect.

3.

Derive the expression for linear and saturation region channel in MOS transistor.

4.

Calculate the threshold voltage for a n transistor at 300 0 K for a process with a Si
substrate with NA = 1.8 1016. A SiO2 Gate oxide with thickness 200 0 (Assume ms=
-0.9V, fc=0).

5.

Explain the function of NMOS pass transistor and derive the expression of output
voltage.

6.

Suppose that V00 5 V and Vth 0.7 V. Find the output of the NFET in fig. 1 for the
following input voltage value. (a) Vin = 2 V , (b) Vin = 4.5 V (c) Vin = 3.5 V
VGG
Vin

Vout

Fig.1

Module 2:
1.

Write the effect of scaling.

2.

Convert the logic gate given in fig. 2. in CMOS logic gate circuit.
A
B
F
Fig.2

C
D

3.

Design a CMOS logic gate that provides the function

i. Out = x. (y.z + z.w)

4.

Design the circuit and layout for a CMOS gate that implement the function
ii. F= a.b.c + a.d
b. Using the fewest number of transistor and compact layout style

5.

Design a full adder circuit using CMOS logic gate.

6.

Design a full adder circuit using CMOS transmission gate.

7.

Design a RS Flip-flop using CMOS logic gate circuit.

8.

Design a T- Flip-flop using CMOS logic gate.

9.

Design a JK- Flip-flop using CMOS logic gate.

10.

Design a D- Flip-flop using CMOS logic gate.

11.

Design a Master-Slave Flip-flop using Transmission gate.

12.

Design a counter with state 1,3,5,4 using T flip-flop.

13.

Explain the DC characteristics of CMOS invertors.

Module 3:
1.

Use SPICE to obtain the output characteristics of the n-channel transistor shown ion
fig3. Using the LEVEL 1 model and the parameter values V TO = 0.7, K1 = 110 A/V2 ,
= 0.4 V1/2, = 0.04 V-1 , 2 |F | = 0.7 V. The output curve is to be plotted for drain-source
voltage from 0 to
5 V and for gate-source voltage of 1, 2, 3, 4 and 5 V. Assuming
that bulk voltage is zero volt.
M1

Fig. 3

2.

VDS

VGS

Use the data from prob. 20 and use the SPICE simulator to obtain a plot of the value of
VOUT as a function of VIN of fig. 4. Identify the dc value of VIN that gives VOUT = 0 V?
VDD = 5V

Fig. 4

M3

M2
Vout

R1= 100K

M1

3.

Use SPICE to obtain a small signal frequency response of V OUT ()/VIN () when the
amplifier is biased in transition region. Assume that a 5 pF capacitor is attached to the
output of the fig. 4 and find the magnitude and phase response over the frequency
range of 100 Hz to 100 MHz.

Module 4:
1.

Calculate the threshold voltage of NMOS XOR with substrate grounded. Given
c. Substrate doping density NA = 2 1015/cm3
d. polysilicon gate doping density NA = 1 1020/cm3
e. gate oxide thickness tox= 1000 A0
f. Oxide interface fixed charge density Nox =1 1010/cm3

2.

For an enhancement MOS find w/l if following parameters are given

g. VTO = 0.8 V; = 0.2 V1/2; |2dF | = 0.84 V ;
h. k(Tranconductance)= 20A/V2 , VGS= 2.8 V; VDS= 5.0 V; VBS= 0 V
i. & ID = 0.24 mA

3.

Explain the effect of scaling on gate delay& speed power product.

4.

Calculate the noise margin of CMOS inverter with V DD = 5V ;VTO, n = 1 V VTO, p= -1 V, kn

= 200 A/V2

5.

By increasing w/l ratio of NMOS & decreasing w/l of PMOS threshold can be obtained
in middle of voltage transfer curve. Justify it.

6.

Design the circuit Y= A (B+C) (D+E) using CMOS logic. Also find the CMOS invertor
circuit for simultaneous switching of all L/P assuming (w/l) p=5 and (w/l) n=2 for all
PMOS & NMOS XOR respectively.

7.

Draw the layout of 2i/p NOR gate.

8.

Draw the stick diagram of 2i/p NOR gate.

9.

Draw the stick diagram of 2i/p CMOS NAND gate.

10.

Draw the layout of CMOS invertor.

Module 5:
1.

Write the VHDL program for 8-bit adder and simulate.

2.

Design a 2 1 mux using CMOS TG.

3.

Design a XOR gate using CPL design style.

4.

Write VHDL code for JK F/F.

5.

Design and simulate mealy FSM in VHDL

0/0

1/0

0/0

1/0

1/0

0/0
0/0

6.

Compare CPLD with FPGA in terms of No. of I/O, process technology, power
consumption, Architecture etc.

7.

Implement multiply and add circuit using shift resister modules, multiplying module and
adder module.

8.

Write VHDL code for 8 bit up-down counter.

9.

Implement BCD to gray code using PLA.

10.

Implement BCD to seven segment using ROM.

Module 6:
1.

Design the current and w/l values of current mirror load differential amplifier to satisfy
following spec: VDD= -VSS = 2.5 V, SR 10 V/ s, CL = 5 pF, f-3dB 100 kHz. Small signal
voltage gain 100, 1 mW Pdoss and 2VICMR-1.5
j. kn= 110 A/V2 , kp= 50 A/V2 , VTN= 0.7 V, VTP= -0.7V, N= 0.04 V-1, and P= 0.5 V1

VDD

2/1
2/1

M3

Vout
VG1

2/1

2/1

VG2

Vbias
2.

Design a CMOS differential amplifier with current mirror load.

3.

Explain what is current amplifier.

4.

Design a two-stage CMOS op-Amp.

5.

How the 1/f noise is reduced in designing a op-amp?

6.

Explain the CMOS invertor DC transfer characteristics and operating range.

7.

Explain the Operating range of CMOS invertor and draw the equivalent circuit.

8.

Explain the pseudo NMOS invertor.

9.

Explain differential amplifier, which employs an active current mirror load instead of
resistance p transistors.

10.

Explain rule and rule.

11.

Explain DRC & mask circuit extraction program related to CAD.

12.

Find out the MOS capacitor in accumulation, depletion and inversion layer.

13.

Explain the effect of static dissipation in CMOS circuit.

14.

Explain the effect of dynamic dissipation in CMOS circuit.

15.

Explain the various ways by which power saving occurs.

16.

For a given size of transistor NAND gates are generally a better choice than NOR
gates in complementary CMOS logic. Justify it.

17.

How current mirror differential amplifier reduces the on chip VDD supply?

18.

Explain SPICE modelling of MOS capacitance.

Module 7:
1.

Explain Ion Implantation & Electron beam technology.

2.

Explain circuit level, timing and logic level simulation.

3.

Estimate the hysteresis for a simplified CMOS latch where the aspect ratio of the
CMOS transmission gate is 4.5. While those of inverter a and base 6 and 0.6
respectively for both PMOS and NMOS.

4.

Design and explain the operation of a pseudo NMOS tri-phase latch.

5.

Design a CMOS D flip-flop with asynchronous set-reset and output buffer. Why is the
o/p buffer needed?

6.

What additional circuitry is needed at the minimum, to realize a JK flip flop starting
from the D-flipflop of Ques. 66?

7.

Realise the Boolean expression Z = (A+B).(C.E') using CVSL and explain its operation.

8.

What is a pseudo NMOS logic? Give an example. What are its advantages over
conventional NMOS or CMOS logics?

9.

Realise the Boolean expression Z = A.B + C.E' using CMOS logic and explain its
operation.

10.

Show that to grow an oxide layer of thickness x, a thickness of 0.44x of silicon is

consumed. Given molecular weight and density of Si is 28.09 gm/mole, 2.33 gm/cm 3
and that of SiO2 is 60.08 gm/mole and 2.21 gm/cm3 respectively.

11.

A silicon ingot with 3 X 1016 antimony atoms/cm3 is to be grown by CZ technique. What

should be the concentration of antimony in the melt to obtain the required doping
concentration the segregation coefficient of antimony is 0.023.

12.

A silicon ingot should contain 5X10 16 boron atoms/cm3 when grown by CZ technique.
What concentration of boron atoms should be in the melt to give the required
concentration in the ingot? If the initial load of silicon in the crucible is 60 kg, how many
grams of boron should be added? Segregation coefficient of boron is 0.8

13.

For a reference inverter assume that the load is a depletion mode transistor. If V DD =
5V, VOL = 0.25 V, VOH= 5V, VT Load = -3 V and VT Driver = 1V size the inverter so that both
the transistors work in saturation.

14.

Derive sizing of various transistors in a 4-input NAND gate based on the reference
inverter for which the driver and the load has aspect ratios of 2/1 and 3/1 respectively.
Assume a depletion transistor load to draw the schematic using NMOS only.

15. Simulate a 2-input NAND gate using SPICE for all the input switching combinations. The
two inputs taken are Vin1 and Vin2 in the simulation programme.
Case
Case
1
Case
1
Case
1
Case
1

Vin1

Vin2

Pulse

Pulse

Pulse

Pulse

16. Implement the function Y = [(A+B+C) (D+E) F] using CMOS logic based on dual pull-up
and pull-down graph.
17. Write the complete code of half adder, full adder and 8 bit adder using VHDL.
18. Design a 2X1 multiplexer using CMOS X-gate.
19. Write the complete VHDL code for RS, JK and D flip flop.
20. Design the FSM given in fig. 80

S0/0

S1/0

S2/0

S3/0

Fig 80

21. Write the VHDL code for the design given for fig 80.