Annexure - e - Ecs351 (III)

BUDDHA INSTITUTE OF TECHNOLOGY
Department of Computer Science & Engineering
LAB MANUAL
Semester :
THIRD
Sub Code :
ECS-351
Subject :
LOGIC DESIGN LAB
Buddha Institute of Technology, Gorakhpur -Department of Computer Science & Engg.
INDEX
Sl.
#
Experiment / Program
Page
#
TTL TRANSFER CHARACTERISTICS AND TTL IC

GATES
1-2
CMOS GATE TRANSFER CHARACTERISTICS
3-4
IMPLEMENTATION OF A 3-BIT SIPO AND SISO

SHIFT REGISTER USING FLIP-FLOPS
5-6
IMPLEMENTATION OF A 3-BIT PIPO AND PISO

SHIFT REGISTER USING FLIP-FLOPS
DESIGN OF SEVEN SEGMENT DISPLAY DRIVER

FOR BCD CODES
9-11
BCD ADDER & SUBTRACTOR

6
7
12-13
A L U
14-15
8085 ASSAMBLY LANGUAGE PROGRAMMING

8
Session: July- Dec. 2012
16-17
Lab Manual Logic Design Page 0
Experiment # 1 : To study TTL transfer characteristics.

AIM: To study TTL transfer characteristics.
APPARATUS REQUIRED: Digital Trainer Kit, Dual Power supply, Multimeter.
IC 74LS00 (TTL Based Quad 2-Input NAND Gate) and

Connecting wires.
THEORY:
TTL CHARACTERISTICS:
Fan-in is the maximum number of inputs to a gate. Although physical considerations
limit fan-in, more pragmatic factors, such as limitations on the number of pins possible
on IC packages and their standardization predominate. TTL NAND gates typically
provide 1, 2, 4, or 8 inputs.
If more than eight inputs are required, then a network of NAND gates must be
employed.
Fan-out specifies the number of standard loads that the output of a gate can drive
without impairing its normal operation. A standard load is defined to be the amount of
current required to drive an input of another gate in the same logic family. Due to the
nature of TTL gates, two different fan-out values are given, one for HIGH outputs and
one for LOW outputs.
Negative; hence, IILmax = -1.6mA. A typical TTL gate can source 400 A (I0H(max)) of
Current and can sink 16 mA (I0L(max)). Hence TTL gates typically have a HIGH (logic
level) fan-out of |I0H(max)/IIH(max)| = |-400 A / 40 A| = 10, and a LOW fan-out of |
I0L(max)/IIL(max)| = |16 mA / -1.6 mA| = 10. Exceeding these fan-out limits may
result in incorrect voltage levels at the output, as a gate cannot provide or sink
enough current. A
CIRCUIT DIAGRAM:
voltage transfer curve is a graph of the input voltage to a gate versus its output
voltage Figure 3.2 shows the transfer curve for TTL inverter without any fan out. When
the input voltage is 0 V, the output is HIGH at 3.3 V. As the input voltage is increased
from 0 to 0.7 V, the output
Current & Voltage parameters:

High level i/p voltage VIH : This is the min. i/p voltage at the o/p corresponding to
logic1.

Low level i/p voltage VIL : This is the max. i/p voltage which is recognized by the
gate as logic0.
High level output voltage VOH : This is the min. voltage available at the o/p
corresponding to logic1.
Low level o/p voltage VOL : This is the max. voltage available at the o/p
corresponding to logic0.
PROCEDURE:
1) Connect the circuit as per circuit diagram for TTL IC.

2) Vary the i/p voltage in steps & note down corresponding o/p voltage.
3) Plot graph of Vi Vs Vo.
OBSERVATIONS:
Sr.
1
2
3
4
5
6
7
Vi
Vo
RESULT: Thus transfer characteristics of TTL IC is studied.

PRECAUTIONS:
(i)
(ii)
Connections were given as per circuit diagram.

Switch on the power supply after connecting circuit.

(iii)
(iv)
Logical inputs were given as per truth table.

Observe the logical output and verify with the truth tables.
Experiment # 2 : To study TTL transfer characteristics.

AIM: To study CMOS transfer characteristics.
APPARATUS REQUIRED: Digital Trainer Kit, Dual Power supply, Multimeter.
IC 74H00 ((CMOS Based Quad 2-Input NAND Gate))
and
THEORY:
Connecting wires.
CMOS FAMILY
CMOS logic is exemplified by its extremely low power consumption and high noise
immunity. Hence, it is prevalently used in devices demanding low power dissipation,
such as digital wristwatches and other battery powered devices, or in devices
operated in noisy environments, such as industrial plants. A wide variety of CMOS
logic devices in the 4000 series are available. Unlike TTL logic, CMOS logic requires
two supply voltages, VDD and VSS. In typical logical designs, VDD ranges from +3 V
to +16 V. The other supply, VSS, is normally grounded. Also, the physical
representation of the binary states in CMOS logic is not entirely compatible with TTL
logic. As a consequence of CMOS's extremely high input impedance, the logic levels in
CMOS systems are essentially VDD and ground. If, for example, a 5 volt power supply
is used, LOW typically ranges from 0 to 0.01 V and HIGH from 4.99 to 5.0 V for CMOS
outputs. Input voltages ranging from 3.5 to 5 V are recognized as HIGH and voltages
from 0 to 1.5 V as LOW. It may appear that CMOS output logic levels, using a 5 V
power supply, completely conform to the TTL logic level ranges of 0 to 0.8 V for LOW
and 2.0 to 5.5 V for HIGH. However, the Typical CMOS gates can sink about 0.4 mA in
the LOW state while maintaining an output voltage of 0.4 V or less. (A pull-up resistor
to +5 can be connected to the gate output to assure that the output is above 3.5V.)
Whether this is sufficient for reliable operation depends upon the exact specifications
for both the TTL outputs and the CMOS inputs.
CIRCUIT DIAGRAM:
CMOS CHARACTERISTICS:
The voltage transfer curve for a typical CMOS logic gate is shown in Figure 3.6. Note
that the curves in the transition region are almost vertical. This narrow transition
region is the reason for CMOS logic's high noise immunity. Not much voltage range is
covered in the transition from voltage and is approximately half the supply voltage.
As with TTL logic, current spiking occurs during switching. Hence, bypass capacitors
are used in CMOS logic design as well. However, they are not as critical as in TTL logic
design because of CMOS's high noise immunity. Whereas the typical quiescent (static)

power dissipation (power dissipation of a device that is not changing logic states) of
TTL IC's was about 40 mW, the power dissipation of CMOS IC's are typically 25 nW.
PROCEDURE:
1) Connect the circuit as per circuit diagram for CMOS IC.
2) Vary the i/p voltage in steps & note down corresponding o/p voltage.
3) Plot graph of Vi Vs Vo.
OBSERVATIONS:
Sr.
1
2
3
4
5
6
7
Vi
Vo
RESULT: Thus transfer characteristics of CMOS IC is studied.

PRECAUTIONS:
(i)
(ii)
(iii)
(iv)

Experiment # 3 : Bread board implementation of a 3-bit SIPO & SISO

shift resisters using flip-flops.
AIM: Bread board implementation of a 3-bit SIPO & SISO shift resisters using flipflops.
APPARATUS REQUIRED: Digital Trainer Kit and Connecting wires.
THEORY:
In digital circuits, a shift register is a cascade of flip flops, sharing the same clock,
which has the output of any one but the last flip-flop connected to the "data" input of
the next one in the chain, resulting in a circuit that shifts by one position the onedimensional "bit array" stored in it, shifting in the data present at its input and shifting
out the last bit in the array, when enabled to do so by a transition of the clock input.
More generally, a shift register may be multidimensional; such that its "data in"
input and stage outputs are themselves bit arrays: this is implemented simply by
running several shift registers of the same bit-length in parallel.
Shift registers can have both parallel and serial inputs and outputs. These are often
configured as serial-in, parallel-out (SIPO) or as parallel-in, serial-out (PISO).
There are also types that have both serial and parallel input and types with serial and
parallel output. There are also bi-directional shift registers which allow shifting in
both directions: LR or RL. The serial input and last output of a shift register can
also be connected together to create a circular shift register.
Serial-in, serial-out (SISO)

Destructive readout
These are the simplest kind of shift registers. The data string is presented at 'Data In',
and is shifted right one stage each time 'Data Advance' is brought high. At each
advance, the bit on the far left (i.e. 'Data In') is shifted into the first flip-flop's output.
The bit on the far right (i.e. 'Data Out') is shifted out and lost.
The data are stored after each flip-flop on the 'Q' output, so there are four storage
'slots' available in this arrangement; hence it is a 4-Bit Register. To give an idea of the
shifting pattern, imagine that the register holds 0000 (so all storage slots are empty).
As 'Data In' presents 1, 0,1,1,0,0,0,0 (in that order, with a pulse at 'Data Advance'
each time this is called clocking or strobing) to the register, this is the result. The
left hand column corresponds to the left-most flip-flop's output pin, and so on.
So the serial output of the entire register is 10110000 . As you can see if we were to
continue to input data, we would get exactly what was put in, but offset by four 'Data
Advance' cycles. This arrangement is the hardware equivalent of a queue. Also, at any
time, the whole register can be set to zero by bringing the reset (R) pins high.
Serial-in, parallel-out (SIPO)

This configuration allows conversion from serial to parallel format. Data is input
serially, as described in the SISO section above. Once the data has been input, it may
be either read off at each output simultaneously, or it can be shifted out and replaced.
4-Bit SIPO Shift Register

RESULT: The entire shift right & shift left operations are verified operations.
PRECAUTIONS:
(i)
(ii)
(iii)
(iv)

Experiment # 4 : Bread board implementation of a 3-bit PIPO & PISO

shift resisters using flip-flops.
AIM: Bread board implementation of a 3-bit PIPO & PISO shift resisters using flipflops.
APPARATUS REQUIRED: Digital Trainer Kit and Connecting wires.
THEORY:
Parallel-in, serial-out (PISO)
This configuration has the data input on lines D1 through D4 in parallel format. To
write the data to the register, the Write/Shift control line must be held LOW. To shift
the data, the W/S control line is brought HIGH and the registers are clocked. The
arrangement now acts as a PISO shift register, with D1 as the Data Input. However, as
long as the number of clock cycles is not more than the length of the data-string, the
Data Output, Q, will be the parallel data read off in order.
4-Bit PISO Shift Register
The animation below shows the write/shift sequence, including the internal state of
the shift register.
PIPO:Truth Table
Clock
Time
Clock-2
Clock-1
T0
T1
T2
T3
T4
Q3
1
Outputs
Q2 Q1
Q0
1
0
1
1
1
0
1
1
1
Parallel In Serial Out (PISO):

1. Connections are made as per circuit diagram.
2. Apply the desired 4 bit data at A, B, C and D.
3. Keeping the mode control M=1 apply one clock pulse. The data applied at
A, B, C and D will appear at QA, QB, QC and QD respectively.
4. Now mode control M=0. Apply clock pulses one by one and observe the
Data coming out serially at QD
Parallel In Parallel Out (PIPO):
1. Connections are made as per circuit diagram.
2. Apply the 4 bit data at A, B, C and D.
3. Apply one clock pulse at Clock 2 (Note: Mode control M=1).
4. The 4 bit data at A, B, C and D appears at QA, QB, QC and QD respectively.
RESULT: The entire shift right & shift left operations are verified operations.
PRECAUTIONS:
(i)
(ii)
(iii)
(iv)
Experiment # 5 : Design of seven segment Display driver for BCD code.

AIM: Design of seven segment display driver for BCD code.

APPARATUS REQUIRED: Digital Trainer Kit, IC mc14511, Seven segment display
(common anode), Power Supply and Connecting wires.
THEORY:
In order to produce the required numbers or HEX characters from 0 to 9 and A to F
respectively, on the display the correct combination of LED segments need to be
illuminated and BCD to 7-segment Display Decoders such as the 74LS47 do just
that. A standard 7-segment LED display generally has 8 input connections, one for
each LED segment and one that acts as a common terminal or connection for all the
internal segments.
There are two important types of 7-segment LED digital display.
The Common Cathode Display (CCD) - In the common cathode display, all the
cathode connections of the LED's are joined together to logic "0" and the
individual segments are illuminated by application of a "HIGH", logic "1" signal
to the individual Anode terminals.
The Common Anode Display (CAD) - In the common anode display, all the
anode connections of the LED's are joined together to logic "1" and the
individual segments are illuminated by connecting the individual Cathode
terminals to a "LOW", logic "0" signal.
7-Segment Display Format
Truth Table for a 7-segment display

Individual Segments Display
a b c d e f g

0

1

3

4

6

7
Individual Segments Display

a b c d e f g

8

9

A

b
7-Segment Display Elements for all Numbers.
Binary Coded Decimal (BCD or "8421" BCD) numbers are made up using just 4 data
bits (a nibble or half a byte) similar to the Hexadecimal numbers we saw in the
binary tutorial, but unlike hexadecimal numbers that range in full from 0 through to F,
BCD numbers only range from 0 to 9, with the binary number patterns of 1010
through to 1111 (A to F) being invalid inputs for this type of display and so are not
used as shown below.
Decim
al
0
1
2
3
4
5
6
7
Binary Pattern
8
4
2
1
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
BCD
Decim
al
0
1
2
3
4
5
6
7
8
9
Binary Pattern
8
4
2
1
1
0
0
0
1
0
0
1
10
11
12
13
14
BCD
8
9
Invali
d
Invali
d
Invali
d
Invali
d
Invali
d
15
Invali
d
BCD to 7-Segment Display Decoders A binary coded decimal (BCD) to 7-segment

display decoder such as the TTL 74LS47 or 74LS48, have 4 BCD inputs and 7 output
lines, one for each LED segment. This allows a smaller 4-bit binary number (half a
byte) to be used to display all the denary numbers from 0 to 9 and by adding two
displays together, a full range of numbers from 00 to 99 can be displayed with just a
single byte of 8 data bits.
BCD to 7-Segment Decoder
The use of packed BCD allows two BCD digits to be stored within a single byte (8-bits)
of data, allowing a single data byte to hold a BCD number in the range of 00 to 99.
An example of the 4-bit BCD input (0100) representing the number 4 is given below.
In practice current limiting resistors of about 150 to 220 would be connected in

series between the decoder/driver chip and each LED display segment to limit the
maximum current flow. Different display decoders or drivers are available for the
different types of display available, e.g. 74LS48 for common-cathode LED types,
74LS47 for common-anode LED types, or the CMOS CD4543 for liquid crystal display
(LCD) types.
RESULT: Output are observe on the 7-segment display for various combinations.
PRECAUTIONS:
1) Connect the circuit as shown fig.
2) Switch on the power supply & observe the output on 7-segment
display for different BCD input.
Experiment # 6 : To study BCD Adder.

AIM: To study of BCD Adder.
APPARATUS REQUIRED: Digital Trainer Kit, IC -7483 , 7408 , 7432, Connecting
wires and Power supply ( 5v, Vcc )
Theory:
A BCD adder is a circuit that adds two BCD digits in parallel and produces a sum digit
which is also in BCD adder must include the
correction logic in its internal
construction. This adder has two 4 bit BCD inputs X3 X2 X1 X0 , Y3 Y2 Y1 Y0 and a
carry input (Cin). It also has a 4 bit sum output (S3 S2 S1 S0) and a carry output
(Cout). Here the sum output is also in BCD form.
A BCD adder circuit must be able to do the following:
1. Add two 4-bit BCD numbers using straight binary addition.
2. If the 4-bit sum is equal to or less than 9, the sum is in proper BCD form and no
Correction is needed.
3. If the 4-bit sum is greater than 9, or if a carry is generated from the sum, the
sum is not in the BCD form. Then the digit 6 (0110) should be added to the sum
to produce the BCD results. The carry may be produced due to this addition and
it is added to the next decimal position.
LOGIC DIAGRAM OF BCD ADDER

K MAP
Y = S4 (S3 + S2)
TRUTH TABLE:
BCD SUM
S4
0
0
0
S3
0
0
0
CARRY
S2
0
0
1
S1
0
1
0
C
0
0
0

0
0
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
RESULT: Operation of BCD adder is verified.
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
1
1
1
1
1
1
PRECAUTIONS: 1) Connections were given as per circuit diagram.

2) Logical inputs were given as per truth table
3) Observe the logical output and verify with the truth tables.
Experiment # 7 : Implementation of Arithmetic Algorithm and perform

ALU operations.
AIM: Implementation of Arithmetic Algorithm and perform ALU operations.
APPARATUS REQUIRED:
Digital Trainer Kit
IC 74181 and connecting wires
PROCEDURE:
1. Connections are made as shown in the Circuit diagram.
2. Change the values of the inputs and verify at least 5 functions given in the
Function table.
Pin detail & Function table:
Pin Diagram of IC 74181
RESULT: Hence function of ALU is verified.
Experiment # 8 - 8085 assembly Language programming.

AIM: 8085 assembly Language programming.
APPARATUS REQUIRED: 8085 Microprocessor Kit.
PROCEDURE:
1. Enter the program from location 2000 onward using EXMEM Command. Also
enter the data at locations 2009 and 200A.
2. Execute the program from 2000 using GO key and examine the result at location
200B.
PROGARM: (FOR ADDITION)

ADDRES
S
OPCOD
E
2000
2003
2004
2005
2006
2007
2008
2009
200A
200B
21 09
20
7E
23
86
23
77
EF
EXAMPLE:
Address
2009
200A
200B
RESULT:
LABEL
MNEMONI
C
LXI
MOV
INX
ADD
INX
MOV
RST
OPRAND
H 2009
A,M
H
M
H
M,A
5
COMMENTS
Point to 1st no.

Load it in to accumulator
Point to 2nd number
Add the two numbers
Point to storage
Store it
DATA
DATA
Two HEX nos. to be added.
RESULT
Result
Data
23 Data in decimal
32 Data in decimal
55 Answer in decimal
23H+32H=55H
PROGARM: (FOR SUBTRACTION)

ADDRES
S
OPCOD
E
2000
2003
2004
2005
2006
2007
2008
2009
200A
200B
21 09
20
7E
23
96
23
77
EF
LABEL
MNEMONI
C
LXI
MOV
INX
SUB
INX
MOV
RST
DATA
DATA
OPRAND
H 2009
A,M
H
M
H
M,A
5
COMMENTS
Point to 1st no.

Load it in to accumulator
Point to 2nd number
Subtract the two numbers
Point to storage
Store it
Two HEX nos. to be
subtracted.
RESULT
Result
EXAMPLE:
Address
2009
200A
200B
RESULT:
Data
32 Data in decimal
12 Data in decimal
20 Answer in decimal
32H-12H=20H

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BUDDHA INSTITUTE OF TECHNOLOGY

Department of Computer Science & Engineering

LOGIC DESIGN LAB

Buddha Institute of Technology, Gorakhpur -Department of Computer Science & Engg.

TTL TRANSFER CHARACTERISTICS AND TTL IC

CMOS GATE TRANSFER CHARACTERISTICS

IMPLEMENTATION OF A 3-BIT SIPO AND SISO

IMPLEMENTATION OF A 3-BIT PIPO AND PISO

DESIGN OF SEVEN SEGMENT DISPLAY DRIVER

BCD ADDER & SUBTRACTOR

8085 ASSAMBLY LANGUAGE PROGRAMMING

Session: July- Dec. 2012

Lab Manual Logic Design Page 0

Buddha Institute of Technology, Gorakhpur -Department of Computer Science & Engg.

Session: July- Dec. 2012

Lab Manual Logic Design Page 1

Buddha Institute of Technology, Gorakhpur -Department of Computer Science & Engg.

Experiment # 1 : To study TTL transfer characteristics.

IC 74LS00 (TTL Based Quad 2-Input NAND Gate) and

Current & Voltage parameters:

Session: July- Dec. 2012

Lab Manual Logic Design Page 2

Buddha Institute of Technology, Gorakhpur -Department of Computer Science & Engg.

1) Connect the circuit as per circuit diagram for TTL IC.

RESULT: Thus transfer characteristics of TTL IC is studied.

Connections were given as per circuit diagram.

Session: July- Dec. 2012

Lab Manual Logic Design Page 3

Buddha Institute of Technology, Gorakhpur -Department of Computer Science & Engg.

Logical inputs were given as per truth table.

Session: July- Dec. 2012

Lab Manual Logic Design Page 4

Buddha Institute of Technology, Gorakhpur -Department of Computer Science & Engg.

Experiment # 2 : To study TTL transfer characteristics.

Session: July- Dec. 2012

Lab Manual Logic Design Page 5

Buddha Institute of Technology, Gorakhpur -Department of Computer Science & Engg.

RESULT: Thus transfer characteristics of CMOS IC is studied.

Connections were given as per circuit diagram.

Session: July- Dec. 2012

Lab Manual Logic Design Page 6

Buddha Institute of Technology, Gorakhpur -Department of Computer Science & Engg.

Experiment # 3 : Bread board implementation of a 3-bit SIPO & SISO

Serial-in, serial-out (SISO)

Serial-in, parallel-out (SIPO)

4-Bit SIPO Shift Register

Lab Manual Logic Design Page 7

Buddha Institute of Technology, Gorakhpur -Department of Computer Science & Engg.

Connections were given as per circuit diagram.

Session: July- Dec. 2012

Lab Manual Logic Design Page 8

Buddha Institute of Technology, Gorakhpur -Department of Computer Science & Engg.

Experiment # 4 : Bread board implementation of a 3-bit PIPO & PISO

Parallel In Serial Out (PISO):

Session: July- Dec. 2012

Lab Manual Logic Design Page 9

Buddha Institute of Technology, Gorakhpur -Department of Computer Science & Engg.

Experiment # 5 : Design of seven segment Display driver for BCD code.

Lab Manual Logic Design Page 10

Buddha Institute of Technology, Gorakhpur -Department of Computer Science & Engg.

AIM: Design of seven segment display driver for BCD code.

7-Segment Display Format