COMBINATIONAL CIRCUIT

OBJECTIVES
 To design a combinational circuit in accordance with a given set of conditions.
 To obtain the truth table of the combinational circuit and simplify the corresponding
output function.
 To design and construct the combinational circuit, using NAND gates with a minimum
number of ICs.
 To test the circuit for proper operation by verifying the given conditions.

MATERIALS
 Alexan Digital Trainer
 one 7400 quad two-input NAND gate
 one 7410 tri three-input NAND gate
 insulated connecting wires
 cutter or scissors

PROBLEM ANALYSIS
The task at hand is to design a combinational circuit with four inputs 𝐴, 𝐵, 𝐶, and 𝐷. The single
output, 𝐹 is to be equal to 1 when:
(i) 𝐴 = 1, provided that 𝐵 = 0;
(ii) 𝐵 = 1, provided either 𝐶 or 𝐷 is also equal to 1.
Otherwise, the output is to be equal to 0.

In determining a Boolean function that represents this combinational circuit, we can

start by deriving a truth table based on the given conditions. Doing so gives us Table 10-1 from
which, we see that the desired combinational circuit has a total of ten 1’s in its output.
Specifically, the 1’s correspond to the following states: 0101, 0110, 0111, 1000, 1001, 1010,
1011, 1101, 1110, and 1111. Therefore, in sum-of-products form, the combinational circuit
can be represented by the Boolean function

𝐹 𝐴, 𝐵, 𝐶, 𝐷 = 𝐴′ 𝐵𝐶 ′ 𝐷 + 𝐴′ 𝐵𝐶𝐷′ + 𝐴′ 𝐵𝐶𝐷 + 𝐴𝐵 ′ 𝐶 ′ 𝐷′
+𝐴𝐵 ′ 𝐶 ′ 𝐷 + 𝐴𝐵 ′ 𝐶𝐷′ + 𝐴𝐵 ′ 𝐶𝐷 + 𝐴𝐵𝐶 ′ 𝐷
+𝐴𝐵𝐶𝐷′ + 𝐴𝐵𝐶𝐷 .

Alternatively, the function can be expressed in sum-of-minterms form as

𝐹 𝐴, 𝐵, 𝐶, 𝐷 = 𝑚5 + 𝑚6 + 𝑚7 + 𝑚8 + 𝑚9 + 𝑚10 + 𝑚11 + 𝑚13 + 𝑚14 + 𝑚15

 Laboratory Activity No . 10| 2

or in short-hand notation, 𝐹(𝐴, 𝐵, 𝐶, 𝐷) = Σ 5, 6, 7, 8, 9,10, 11, 13, 14, 15 .

Table 10-1. Truth Table of the

Desired Combinational Circuit

INPUT OUTPUT
m 𝑨 𝑩 𝑪 𝑫 𝑭
0 0 0 0 0 0
1 0 0 0 1 0
CD
2 0 0 1 0 0
AB 00 01 11 10
3 0 0 1 1 0 𝑚0 𝑚1 𝑚3 𝑚2
4 0 1 0 0 0 00
5 0 1 0 1 1 𝑚4 𝑚5 𝑚7 𝑚6
01 1 1 1
6 0 1 1 0 1
𝑚12 𝑚13 𝑚15 𝑚14
7 0 1 1 1 1 11 1 1 1
8 1 0 0 0 1 𝑚8 𝑚9 𝑚11 𝑚10
10 1 1 1 1
9 1 0 0 1 1
10 1 0 1 0 1 𝑩𝑪
11 1 0 1 1 1 𝑩𝑫
𝑨𝑩′
12 1 1 0 0 0
Figure 10-1. Karnaugh map for 𝐹
13 1 1 0 1 1
14 1 1 1 0 1
15 1 1 1 1 1

There are several methods of simplifying the derived Boolean function so that the
number of gates or ICs needed to implement the combinational circuit is minimized. The most
convenient and least time-consuming way to do this, however, is to use a Karnaugh map. That
is, by plotting the 1’s of 𝐹 into the appropriate boxes of a four-variable map, and then
combining them into valid adjacent squares as shown in Figure 10-1, we easily arrive at the
simplified expression for 𝐹 in sum-of-products form:

𝐹 𝐴, 𝐵, 𝐶, 𝐷 = 𝐴𝐵′ + 𝐵𝐶 + 𝐵𝐷 .
The derived Boolean function, which originally consists of 10 terms with 4 literals each, is now
reduced to an equivalent function consisting of three terms with two literals each.
 Laboratory Activity No . 10| 3

PROCEDURE
Figure 10-2 below shows the logic diagram of a combinational circuit that can implement the
function 𝐹 = 𝐴𝐵 ′ + 𝐵𝐶 + 𝐵𝐷 using four two-input and one three-input NAND gates.

Figure 10-2 Circuit diagram—with pin assignments and logic gate analysis—for
the implementation of 𝐹 = 𝐴𝐵 ′ + 𝐵𝐶 + 𝐵𝐷 using a 7400 and a 7410 IC

7400 7410

Figure 10-3. Connection diagram of the circuit in Figure 10-2

 Laboratory Activity No . 10| 4

With all data switches initially turned OFF, the circuit of Figure 10-2 is constructed on
the digital trainer as illustrated in Figure 10-3. Power is then supplied to the digital trainer after
double-checking all pin connections. The logic level output of the combinational circuit for
each of the 16 possible states is determined and illustrated in Figure 10-4.

RESULTS AND DISCUSSIONS

SWITCHES DATA STATUS SWITCHES DATA STATUS

INPUT INPUT OUT INPUT INPUT OUT
S1 S2 S3 S4 LED1 LED2 LED3 LED4 LED5 S1 S2 S3 S4 LED1 LED2 LED3 LED4 LED5

0 8

1 9

2 10

3 11

4 12

5 13

6 14

7 15

D1 D2 D3 D4 IN1 IN2 IN3 IN4 IN5 D1 D2 D3 D4 IN1 IN2 IN3 IN4 IN5

Figure 10-4. Output diagram of the combinational circuit 𝐹 = 𝐴𝐵 ′ + 𝐵𝐶 + 𝐵𝐷

If we compare the ON-OFF status of LED5 shown in Figure 10-4 to the output column of
Table 10-1, it becomes clear that the circuit whose logic diagram is shown in Figure 10-3 is
indeed the desired combinational circuit because it satisfies the given conditions (i) and (ii). In
other words, if we express the ON-OFF output states of the Boolean function 𝐹 = 𝐴𝐵 ′ + 𝐵𝐶 +
𝐵𝐷 into 1’s and 0’s, we obtain a truth table that is exactly the same as that of Table 10-1.

Furthermore, we can verify theoretically that the simplified Boolean function

𝐹 = 𝐴𝐵 ′ + 𝐵𝐶 + 𝐵𝐷 is equivalent to the desired function 𝐹 = Σ 5, 6, 7, 8, 9,10, 11,13,14,15
by generating the truth table of the former and comparing the truth values to that of the
 Laboratory Activity No . 10| 5

latter. Well, as shown in Table 10-2, the truth table of 𝐹 = 𝐴𝐵 ′ + 𝐵𝐶 + 𝐵𝐷 is identical to that
of 𝐹 = Σ 5, 6, 7, 8, 9,10, 11,13,14,15 and so, the two functions are equivalent.

Table 10-2. Truth Table for 𝐹 = 𝐴𝐵 ′ + 𝐵𝐶 + 𝐵𝐷

𝑨 𝑩 𝑪 𝑫 𝑨𝑩′ 𝑩𝑪 𝑩𝑫 𝑭 = 𝑨𝑩′ + 𝑩𝑪 + 𝑩𝑫
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 0
0 0 1 0 0 0 0 0
0 0 1 1 0 0 0 0
0 1 0 0 0 0 0 0
0 1 0 1 0 0 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 1 1
1 0 0 0 1 0 0 1
1 0 0 1 1 0 0 1
1 0 1 0 1 0 0 1
1 0 1 1 1 0 0 1
1 1 0 0 0 0 0 0
1 1 0 1 0 0 1 1
1 1 1 0 0 1 0 1
1 1 1 1 0 1 1 1

CONCLUSION
The combinational circuit that gives a logic-1 output when 𝐴 = 1 and 𝐵 = 0, or when 𝐵 = 1
and either 𝐶 or 𝐷 is equal to 1, is represented by the Boolean function

𝐹 𝐴, 𝐵, 𝐶, 𝐷 = 𝐴𝐵 ′ + 𝐵𝐶 + 𝐵𝐷 .
In sum-of-minterms form, this function can be expressed as

𝐹 = Σ 5, 6, 7, 8, 9,10, 11,13,14,15 .