Design and Simulation of a 4.

0 GHz Low-Noise RF
Amplifier with Avago MGA-665P8 MMIC
Sahand Noorizadeh
School of Electrical and Computer Engineering
Georgia Institute of Technology
Atlanta, Georgia 30332–0250
Email: sahand@gatech.edu

Abstract—To achieve a desired gain or noise figure at a specific
frequency, a two-port RF amplifier network requires an appro-
priate input and output matching network. More often than not,
optimum gain and noise figure cannot be reached simultaneously
and depending on design specifications, a compromise must be
made. Any two-port amplifier network can be characterized
by its S-parameters and noise parameters. This information is
usually given over a wide range of frequencies in the datasheet
of ready-to-use commercial amplifiers. These parameters also
can be measured with an RF network analyzer. The condition
for maximum power coupling from one stage to another is that
the output impedance of the source stage should be a conjugate
match of the input impedance of the load stage. Input and output
matching networks need to be designed to meet this condition
if the maximum power gain is the goal. Reflection coefficients
and VSWRs at the interface of stages of an amplifier circuit
are the parameters that characterize matching conditions of the
circuit. A general rule in safe and good design is to reduce the
power reflection back to the source as much as possible but again
this rarely translates into having an optimum noise figure. The
design process of an RF amplifier requires monitoring multiple
parameters simultaneously. By changing one or more parameters
the effect on the circuit performance can be monitored to achieve
a design goal. This process is known as optimization and it
becomes very cumbersome and time-consuming if performed
without the aid of a computer. There many commercial CAD
softwares available that perform optimization and simulate the
circuit. A commonly used software is Agilents Advanced Design
System (ADS.)
I. I NTRODUCTION
MGA-665P8 is an 8-pin low-noise MMIC that contains a
multi-stage amplifier with the frequency range of 0.5 GHz to 6
GHz and voltage bias range of 3V -5V . This MMIC was used
to design an amplifier circuit with input and output matching
networks designed with microsrip lines on a Duroid RO3006
substrate with ϵr = 6.15, the thickness h = 25 mils, and the
metalization thickness t = 0.5 mil. All the design and simula-
tions were done using Agilents ADS software by importing the
ADS model of MGA-665P8 into ADS library. The first step
in the design was determining the S and noise parameters of
MGA-665P8 using the S-parameters simulation tool. This data
was then used to find the reflection coefficients at the input and
output interfaces of MGA-665P8 and the matching networks to
determine their impedances. These impedances were then used
to design the matching networks with microstrip lines. The
design was optimized using ADS optimization tool by varying
the lengths of the microstrip lines. Simulation results included
plots of noise figure, gain, VSWRs, and the S-parameters.
Optimization process resulted in a noise figure only 0.001 dB
above the minimum achievable noise figure and consequently,
the gain was 0.536 dB below the maximum achievable gain.
The only hard toll taken by optimizing for minimum noise
figure was on the output VSWR which was 2.031.
II. I NITIAL C ALCULATIONS
Since a different DC bias network from the one recom-
mended by Avago was used which would result in an slightly
different S-parameters, the S and noise parameters were ob-
tained by ADS simulation tool. A different DC bias network
was used because the recommended circuit in the data sheet
was designed for 5.25 GHz. The simulated device parameters
at 3.0V DC are listed in Tables I and II. For simplicity
TABLE I
S IMULATED S-PARAMETERS OF MGA-665P
S11 S12 S21 S22
0.274̸ -101.65◦ 0.003̸ 116.325◦ 6.808̸ -168.45◦ 0.048̸ -169.737◦
TABLE II
S IMULATED N OISE PARAMETERS OF MGA-665P
Γopt Fmin RN
0.79 dB 0.399 8.481Ω
purposes, the biased circuit was exported to create hierarchy.
The new component became a two-port biased MGA-665P8.
Having obtained the device parameters, the stability of the
amplifier was checked using the Rollets stability factor K and
the ∆ factor that were calculated using (1) and (2).
∆ = S11 S22 − S12 S21 (1)
1 − |S11 |2 − |S22 |2 + |∆|2
K= (2)
2|S12 S21 |2
Using the S-Parameters of Table I, since K = 22.611 ≫ 1
and |∆| = 0.0317 ≪ 1, it was concluded that the biased
MGA-665P8 amplifier was unconditionally stable [1].
In designing for minimum noise figure, ΓS had to be set
equal to Γopt and ΓL = Γ∗OU T . The values of calculated reflec-
tion coefficients and their related impedances normalizedto the
systems intrinsic impedance,Z0 = 50Ω, are listed in Tables III IV. S IMULATION AND O PTIMIZATION
and IV respectively. Equations (3) to (6) were used to generate The design goal for the amplifier of this project was to
the values in these tables. achieve minimum output noise figure at 4.0GHz. The amplifier
TABLE III
with the matching networks that were calculated and designed
C ALCULATED R EFLECTION C OEFFICIENTS was simulated with ADS‘ S-Parameters Simulation tool which
also included noise simulation. The initial results were less
ΓS ΓIN ΓOU T ΓL than optimum. S22 and S11 did have their highest and lowest
0.399̸ 43.43◦ 0.273̸ -101.74◦ 0.04̸ -164.64◦ 0.043̸ 164.64◦ values respectively at 4.0GHz but the plots of the minimum
possible noise figure and the output noise figure showed the
minimum output noise figure at 4.5GHz. To achieve the goal
TABLE IV of this design, the optimization tool of ADS was used to vary
C ALCULATED N ORMALIZED I MPEDANCES the lengths of the striplines with the goal of minimizing the
output noise figure nf (2). This optimization process started
Zs ZIN ZOU T ZL
with the initial calculated lengths of the striplines and was
1.5+j0.9 Ω 0.8-j0.5 Ω 0.9-j0.02 Ω 0.9+j0.02 Ω
repeated two more times with optimized values. Power Gain,
VSWR, and the K-factor measurement tools were added to
monitor the overall performance of the amplifier circuit.
S21 S12 ΓS
ΓOU T = S22 + (3)
1 − S11 ΓS V. R ESULTS AND D ISCUSSION
Optimization process resulted in minimum output noise
figure, nf (2), at 4.0GHz. The plot of the minimum achievable
ΓL = Γ∗OU T (4) output noise figure, N F min, and the output noise figure,
nf (2), is shown in Figure 2. With this result, the design goal
is achieved since the output noise figure is only 0.001 dB more
S21 S12 ΓL than the minimum noise figure. The S-parameter plot, shown
ΓIN = S11 + (5)
1 − S22 ΓL in Figure 3, also shows desired results at 4.0GHz since S22 is
very close to its maximum value and S11 is at its lowest value.
1+Γ Figure 4 that the power gain at 4.0GHz is almost 0.5 dB less
Z= (6) than the maximum achievable stable power gain. This result
1−Γ
shows that the trade off between maximum power gain and
III. I MPLEMENTATION minimum noise figure did not reduce the gain too much. This
is because MGA-665P8 is designed for minimum noise for
The input matching network had to transform the impedance the frequency range of the 0.5GHz to 5GHz and its datasheet
∗
of the source, 50Ω, to ZIN and the output matching network specifies a power gain of 16 dB [2]. Figure 5 shows the plot
∗
had to transform ZOU T to load’s impedance, 50Ω. The Smith
Chart utility and the Line Calc. tool of ADS were used to
design an appropriate matching scheme and calculate width
and length of microstrips used in the input and the output
matching networks based on a Duroid RO3006 substrate with
ϵr = 6.15, the thickness h = 25 mils, and the metalization
thickness t = 0.5 mil. Figure 1 shows the microstrip lines of
the input and output matching networks and their dimensions.

Fig. 2. Plot of the output noise vs. minimum possible noise.

of V SW RIN and V SW ROU T . V SW ROU T ≈ 1 because

the circuit was designed so that ΓL = Γ∗OU T . And since the
circuit was designed so that ΓS = Γopt , which means the
input matching network is conjugate matched to the amplifier’s
input impeddance at 4.0GHz, V SW RIN is larger than 1. This
Fig. 1. Biased amplifier and microstrip line matching networks.
means that a portion of the power is being reflected back to the
source. This design did not have any constraints on VSWR’s
but usually a safe rule of thumb is to keep VSWR’s below
1.5.

Fig. 6. Plot of Rollet’s stability factor K.

Fig. 3. S-parameters of the simulated optimized circuit. damage the source. ADS is a convenient and quick tools for
designing and simulating RF circuits and its optimization tools
allow fine tunning of the design before fabrication.
R EFERENCES
[1] Gonzalez, Guillermo - Microwave Transistor Amplifier Design
[2] http://www.avagotech.com

Fig. 4. Plot of the network gain vs. maximum possible gain.

Fig. 5. Plot of the input and output VSWR’s.

VI. C ONCLUSION
The design of a low-noise RF amplifier requires input and
output matching network to meet the design requirements.
Achieving the minimum noise figure does not always accom-
pany maximum gain and often one or more parameters need to
be sacrificed to meet the design specifications. VSWR values
indicate how much power is being reflected back to the source
(or amplifier’s output.) VSWR’s always have to be monitored
to ensure that a large amount of power will not reflect to