A Nine-Level Inverter System for an Open-End Winding Induction

Motor Drive
K.Chandra Sekhar1 Member, IEEE, Dr.G.Tulasi Ram Das2 Member, IEEE
1

Dept. of Electrical Engg, R.V.R & J.C College of Engg, Chowdavaram, Guntur, -520 019(India)
2
Dept. of Electrical Engg, J.N.T.U College of Engg, Kukatpally, Hyderabad500 072 (India)

Abstract
A nine-level inverter system for an open-end winding
induction motor drive is presented in this paper.
Multilevel inversion is achieved by feeding an open-end
winding induction motor with two symmetrical 3-level
inverters from both ends. The combined inverter system
with open-end winding induction motor produces
voltage space phasor locations identical to a 9-level
inverter. A total of 4096 space phasor combinations are
available in the proposed scheme, distributed over 217
space vector locations. The proposed inverter drive
scheme is capable of producing the phase voltage
ranging from 2-level to 9-level depending on the depth
of modulation. The inverter with the higher DC-link
voltage is switching less frequently, compared to the
inverter with the lower DC-link voltage.

I.

Introduction

Multilevel inverters can produce an output voltage

waveform having a large number of steps with low
harmonic distortion [1]. They can also reduce the stress
on the switching devices as higher levels are
synthesized from voltage sources with lower levels.
These features have made them suitable for application
in large and medium induction motor drives. There are
four main topologies of multilevel inverters relevant for
large induction motor drive applications: the neutralpoint clamped inverters, cascaded H-bridge inverters,
flying capacitor multilevel inverters and open-end
winding induction motor fed by dual inverters.
The neutral point clamped inverters experience
neutral point fluctuations, as the DC-link capacitors
have to carry the load current. Flying capacitor topology
is another scheme proposed for the multilevel inverters.
This structure does not require the neutral clamping
diodes but needs as many capacitors as floating DC
voltage sources. Higher number of levels is obtainable
with series connected hybrid topology are more
complex [2][3].
Dual inverter fed open-end winding induction
motor drives also results in multilevel inverter structure
[4][5]. A Dual inverter scheme with asymmetrical DC
link voltages for the open-end winding induction motor
is capable of producing a 4-level PWM waveform with
reduced switching ripple for the motor phase voltage
[6][7]. A multilevel system that is capable of realizing a
PWM waveform ranging from 2-level to 5-level is

0-7803-9514-X/06/$20.00 2006 IEEE

described in [8]. The topology described in [9] is

capable of realizing a PWM waveform ranging from 2level to 6-level. The topologies described in [8][9]
constituted by a 3-level inverter and a 2-level inverter
feed an induction motor with open-end windings. The
three-level inverter in [9][10] constituted by the cascade
connection of two 2-level inverters with equal DC-link
voltage.
A multilevel system that is capable of
realizing a PWM waveform ranging from 2-level to 8level is described in [11]. In [11] two 3-level inverters
feed an induction motor with open-end windings from
both ends. The asymmetrical three-level inverter in
[8][11] is constituted by the cascade connection of two
2-level inverters with unequal DC-link voltage.
In the present work, an inverter system to
produce a multilevel PWM waveform ranging from
2-level to 9-level for an open-end winding induction
motor drive is proposed. In the proposed scheme, an
open-end winding induction motor is fed with two
symmetrical three-level inverters from both ends. In the
present work, symmetrical three-level inversion is
obtained by connecting two 2- level inverters with equal
DC-link voltage in cascade. The inverter scheme
proposed in this paper produces 217 voltage space
vector locations. A total of 4096 voltage space vector
combinations are possible in this scheme. The total
number of constituent triangular sectors in this scheme
is enhanced to 384. This results in a reduction of the
switching ripple in the motor phase waveform. The
inverter with the higher DC-link voltage is switching
less frequently, compared to the inverter with the lower
DC-link voltage.
II.

Proposed Power Circuit

Configuration

This paper proposes a topology to realize a

multilevel phase voltage is depicted in Fig.1. In this
circuit configuration, an open-end winding induction
motor is fed with two 3-level inverters A & B (two 2level inverters are connected in cascade-inverter-1 &
inverter-2 and inverter-3 & inverter-4 of Fig.1) from
both ends. The DC-link voltages of inverter-1, inverter2, inverter-3 and inverter-4 are (3/9)Vdc, (3/9)Vdc ,
(1/9)Vdc and (1/9)Vdc respectively, where Vdc is the DClink voltage of an equivalent conventional single 2-level
inverter drive.

ICIEA 2006

Fig.1 Schematic circuit diagram of the proposed 9- level inverter drive scheme.
The pole voltage, of any phase for inverter-2 for
example VA2o (Fig.1) attains a voltage of (3/9)Vdc, if the
following conditions are satisfied:
(i)
The top switch of that leg in inverter-2, in this
case S21, is turned on (Fig.1).
(ii)
The bottom switch of the corresponding leg in
Inverter-1, in this case S14, is turned on
(Fig.1).
Similarly the pole voltage of any phase in inverter-2,
for example VA2o attains a voltage of (6/9)Vdc, if the
following conditions are satisfied:
(i)
The top switch of that leg in inverter-2, in this
case S21, is turned on (Fig.1).
(ii)
The top switch of the corresponding leg in
inverter-1, in this case S11, is turned on (Fig.1).
Thus, the DC-input points of individual phases of
inverter-2 may be connected to a DC-link voltage of
either (6/9) Vdc or (3/9) Vdc by turning on the top switch
or the bottom switch of the corresponding phase leg in
inverter-1. Additionally, the pole voltage of a given
phase in inverter-2 attains a voltage of zero, if the bottom
switch of the corresponding leg in inverter-2 is turned
on. Thus, the pole voltage of a given phase for inverter-2
is capable of assuming one of the three possible values0, (3/9)Vdc and (6/9)Vdc, which is the characteristic of a
three level inverter. This configuration of 3-level inverter
eliminates the neutral point fluctuations associated with
the conventional neutral clamped 3-level inverter [1] as
the capacitors C1 and C2 do not carry the load current but
only the ripple currents. Also, the fast recovery neutral
clamping diodes are eliminated in this topology of 3level inverter. This 3-level inverter can be synthesized by
reconnecting two existing 2-level inverters as a retrofit.

The pole voltages of 3-level inverter-B (inverter-3 &

inverter-4, e.g.VA4o ) assume one of the three values 0,
(1/9)Vdc or (2/9)Vdc, depending on whether the top
switch or the bottom switch of a given phase leg is
turned on.
It may be noted that, each of the three phases of the
motor can attain nine distinct voltage levels (Table-1).
Fig.2 depicts the voltage space phasor combinations
from the symmetrical three-level inverter A and the
three-level inverter B respectively. The resultant space
phasor combinations due to the combined action of these
two inverters are also depicted in Fig.3. It can be
observed from Fig.3 that proposed inverter system is
capable of producing a total of 384 sectors, organized
into eight layers, similar to those produced in a
conventional nine-level inverter. It may be noted that the
three-level inverter can assume 64 space phasor
combinations as inverter-1 and inverter-2 can
individually assume 8 states. Also, inverter-3 and
inverter-4 can assume 8 states independently. Thus, the
number of resultant space phasor combinations for the
combined system is equal to4096 (8x8x8x8) distributed
over 217 locations.
The difference in the pole voltages, for example
(vA2O - vA4O) (Table-1), contains harmonic components
of the triplen order. All these components are dropped
across the points O and O (Fig.1) as isolated power
supplies are employed to power the individual inverters.
Consequently, the motor phase voltage does not possess
the harmonic components of the triplen order. The
triplen harmonic currents are absent in the motor phases
for the lack of a return path.

In the proposed PWM scheme, only three level

inverter B (i.e. inverter-3 & inverter-4) is switched in
the lowest speed range (with v/f mode operation) with
three level inverter A (i.e. inverter-1 & inverter-2 ) is
clamped to a state of 8(---)8(---). The motor phase
voltage can be (2/9)Vdc, (1/9)Vdc, and 0 are obtained
when inverter A is clamped to zero while inverter B is
switched to (2/9)Vdc, (1/9)Vdc, and 0. In the middle speed
range (i.e. fourth, fifth and sixth levels) inverter A is
clamped to its second level (3/9)Vdc,( i.e. inverter-1 is
clamped to a state 8(---) ) while inverter B is switched to
(2/9)Vdc, (1/9)Vdc, and 0. In the higher speed range (i.e.
seventh, eighth and ninth levels ) inverter A can be
clamped to its third level (6/8)Vdc while inverter B is
switched to (2/9)Vdc, (1/9)Vdc, and 0. Since inverter-1 and
inverter-2 are not switched in the lowest speed range, the
switching losses are entirely due to the switching of
inverter-3 and inverter-4. Similarly in the middle range,
the switching losses are due to the switching of
inverter-2, inverter-3 and inverter-4 only. Hence the
inverter A is switched less frequently as the inverter
operates in all these levels.
Fig.3 illustrates the space phasor locations in the
higher speed range, i.e. when all the two level inverters
are switched. It can be observed that a total of 384
sectors are present in Fig.3, organized into eight layers.
III.

Switching Strategy and PWM

Pattern Generation

The 217 voltage space phasor locations form the

vertices of 384 equilateral triangles, which are referred to
as sectors (Fig.2). These sectors are distributed into eight
layers (Fig.3). The equilateral triangles numbered '1'
through '6' in the inner most layers are referred to as
'inner sectors'. Layer-2 consists of the sectors numbered
'7' through '24', layer-3 consists of the sectors numbered
'25' through '54', layer-4 consists of the sectors '55'
through '96', layer-5 consists of the sectors '97' through
'150', layer-6 consists of the sectors '151' through 216,
layer-7 consists of the sectors '217' through '294' and
layer-8 consists of the sectors '218' through '384' (Fig.3).
Pole-voltage Pole-voltage Motor phase voltage
of inverter A of inverter B (vA2A4) vA2A4 = vA2O vA4O'
(vA4O')
(vA2O)
0
(2/9) Vdc
-(2/9) Vdc
0
(1/9) Vdc
-(1/9) Vdc
0
0
0
(3/9) Vdc
(2/9) Vdc
(1/9) Vdc
(3/9) Vdc
(1/9) Vdc
(2/9) Vdc
(3/9) Vdc
0
(3/9) Vdc
( 6/9) Vdc
(2/9) Vdc
(4/9) Vdc
(6/9) Vdc
(1/9) Vdc
(5/9) Vdc
(6/9) Vdc
0
(6/9) Vdc
Table-1: pole voltages of the individual inverters and
the motor phase voltage

Six adjacent sectors constitute a sub-hexagon. One

hundred and sixty -nine such sub-hexagons can be
identified with the present scheme (Fig.3). In addition,
there is one inner sub-hexagon with its center. Each
outer sector can be mapped to the inner sector by shifting
the outer sub- hexagonal center to the inner hexagonal
center.
In this paper, the method employed to determine the
timing periods T0, T1 and T2 to realize the reference
voltage space phasor vsr, involves the following steps:
(i)
Finding the sector in which the tip of the
reference space phasor is situated;
(ii)
Finding the outer sub-hexagon to which the
sector belongs;
(iii)
Shifting the outer sub-hexagonal center to the
inner most hexagonal center using an
appropriate coordinate transformation so that
the reference voltage space phasor is mapped
to the corresponding sector in the inner most
sub-hexagons.
(iv)
Determining the time periods T0, T1 and T2 to
realize the mapped reference voltage space
phasor in the inner most hexagon [5];
(v)
Employing these time periods to switch the
space vector combinations available at the
vertices forming the sector in which the tip of
the reference space phasor is situated [5] [7].
Thus, this procedure is conceptually equivalent to
realize the mapped reference space phasor in the inner
hexagon and applying a vectored offset to realize the
actual reference space phasor in the outer sector. It may
be noted that this procedure ensures that the reference
space phasor is realized by switching amongst the three
vertices, which are situated in the closest proximity to
the tip of the actual reference space phasor.
Consequently, the switching ripple in the output voltage
waveform is minimized.

IV. Simulation Results and Discussion

The proposed scheme is simulated in open loop with
V/f control. The respective DC-bus voltages are (3/9)Vdc,
(3/9)Vdc, (1/9)Vdc and (1/9)Vdc for inverter-1, inverter-2,
inverter-3 and inverter-4. This means that the DC-bus
voltage of an equivalent conventional 2-level inverter
drive is Vdc. Look-up tables are employed for the
generation of PWM signals in each layer. A DC-bus
voltage (Vdc ) of 800v is assumed for simulation studies.
A simulation study was made regarding the space
vector locations for the proposed inverter scheme. The
space vector combinations constituted by the three-level
inverter A are shown in Fig.2A. Similarly the space
vector combinations constituted by the three-level
inverter B are shown in the Fig. 2B. The combined space
vector locations are shown in Fig.3. From Fig.3 it may
be noted that there are 217 space vector locations
organized into 384 sectors. The simulation results for
|Vsr| =0.09Vdc are presented in the Fig.4. In this case, the
tip of the reference voltage space phasor Vsr is confined

to the inner sectors i.e. sectors 1 through 6. The motor

phase voltage shows the familiar 2-level waveform as the
switching confined to the inner hexagon. Similar
experimental results are presented for |Vsr| =0.19Vdc. In
this case, the tip of the reference voltage vector is
confined to the layer-2, which consists of sectors
numbered 7 through 24. In this operating region,
inveter-3 and inveter-4 are switched while inverter-1 and
inveter-2 are clamped to a state of 8(---). In this case
motor phase voltage shows a 3-level waveform Fig.5.
Similarly the experimental results shown in Fig.6
corresponding to the case |Vsr| =0.29Vdc. In this
operating condition the tip of Vsr is situated exclusively
in the sectors of layer-3 ( sectors numbered 25 through
54). In this case motor phase voltage shows a 4-level
waveform. Fig.7 illustrates the simulation results
obtained when the tip of Vsr is forced to be within the
layer-4 (sectors 55 through 96) and corresponds to the
case |Vsr| =0.36Vdc. The motor phase voltage shows a
5-level waveform. Fig.8 shows the simulation results
obtained when the tip of Vsr is situated in the layer-5
(sectors 97 through 150) and corresponds to the case
|Vsr| =0.47Vdc. The motor phase voltage shows a 6-level
waveform. Fig.9 shows the simulation results obtained
when the tip of Vsr is situated in the layer-6 (sectors
151 through 216) and corresponds to the case |Vsr|
=0.58Vdc. The motor phase voltage shows a 7-level
waveform. Fig.10 illustrates the simulation results
obtained when the tip of Vsr is forced to be within the
layer-7 (sectors 217 through 294) and corresponds to
the case |Vsr| =0.68Vdc. The motor phase voltage shows
a 8-level waveform. Fig.11 illustrates the simulation
results obtained when the tip of Vsr is forced to be within
the layer-8 (sectors 295 through 384) and corresponds
to the case |Vsr| =0.78Vdc. The motor phase voltage
shows a 9-level waveform.
It is therefore evident that the proposed inverter
scheme is capable of 9-level inversion depending on the
modulation index.

V.

A controlled AC to DC converter is needed for

the low voltage 2-level inverter to use all the
space vector combinations.
The motor phase voltage in the proposed
inverter PWM scheme can be (2/9)Vdc,
(1/9)Vdc, and 0 are obtained when inverter A is
clamped to zero while inverter B is switched to
(2/9)Vdc, (1/9)Vdc, and 0. For the fourth, fifth
and sixth levels inverterA is clamped to its
second level (3/9)Vdc, while inverter B is
switched to (2/9)Vdc, (1/9)Vdc, and 0. For the
seventh, eighth and ninth levels inverter A can
be clamped to its third level (6/8)Vdc while
inverter B is switched to (2/9)Vdc, (1/9)Vdc, and
0. Hence the inverter A is switched less
frequently as the inverter operates in all these
levels.

Fig.2A The space vector locations for the 3-level

inverter A

Conclusions

A multilevel inverter drive scheme for an open-end

winding induction motor is presented. The salient
features of this scheme are:
Two symmetrical 3-level inverters feed the
open-end winding induction motor from both of
its ends. A total of 4096 voltage space phasor
combinations are present, distributed over 217
space vector locations.
The 3-level inverters used in this scheme are
realized by connecting two 2-level inverters in
cascade. This 3-level inverter eliminates the
neutral point fluctuations, which are present in
the conventional neutral clamped 3-level
inverter. Also, the fast recovery neutral point
clamping diodes are not needed.

Fig.2B The space vector locations for the 3-level

inverter B

Fig.6 Motor phase voltage VA2A4 when |Vsr| = 0.29Vdc

(4-level inverter waveform)

Fig.3 The combined space vector locations for the

proposed 9-level inverter drive scheme

Fig.7 Motor phase voltage VA2A4 when |Vsr| = 0.36Vdc

(5-level inverter waveform)

Fig.4 Motor phase voltage VA2A4 when |Vsr| =0.09Vdc

(2-level inverter waveform)

Fig.8 Motor phase voltage VA2A4 when |Vsr| = 0.47Vdc

(6-level inverter waveform)

Fig.5 Motor phase voltage VA2A4 when |Vsr| = 0.19Vdc

(3-level inverter waveform)
Fig.9 Motor phase voltage VA2A4 when |Vsr| = 0.58Vdc
(7-level inverter waveform)

Induction Motor drive", in Proceedings of the

2001 IEEE APEC Conference,
pp.394
404.

Fig.10 Motor phase voltage VA2A4 when |Vsr| = 0.68Vdc

(8-level inverter waveform)

Fig.11 Motor phase voltage VA2A4 when |Vsr|=0.78Vdc

(9-level inverter waveform)

[6]

E.G
Shivakumar,
V.T
Somasekhar,
K.K.Mohapatra,
K.Gopakumar and
L.Umanand, A Multilevel Space-phasor
based PWM Strategy for an Open End
Winding Induction Motor Drive using two
Inverters with Different DC Link Voltages, in
Proceedings of
the 2001 IEEE PEDS
Conference, pp.169-175.

[7]

Joohn-Sheok Kim and Seung-Ki Sul, "A Novel

Voltage Modulation Technique of the Space
Vector PWM", in Proceedings of the 1995
IPEC Conference, pp.742-747.

[8]

V.T
Somasekhar,
K.Chandra
sekhar,
K.Gopakumar, "A New Five-level Inverter
System for an Induction Motor with Open-end
Winding", in Proceedings of the 2003 IEEE
PEDS Conference, pp.199-204

[9]

V.T.Somasekhar, K.Gopakumar, M.R.Baiju,

K.K.Mohapatra, A Multilevel Inverter system
for an Induction Motor with Open-end
Winding in Proceedings of .IEEE IECON
2002 pp.973-978

[10]

V.T Somasekhar, K.Gopakumar, Three-level

inverter configuration cascading two-level
inverter IEE Transaction on Electr.Power
Appl.Vol.150, No.3 may 2003,pp.245-254.

[11]

K.Chandra sekhar, G.Tulasi Ram Das, "An

Eight-level Inverter System for an Induction
Motor with Open-end Windings", in
Proceedings of
the 2005 IEEE PEDS
Conference, pp.219-223

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