A New Five-level Inverter System for an Induction Motor with

Open-end Windings
V.T. Somasekhar', K. Chandrasekhar*,K. Gopakumar3
'Department of Electrical Engineering, National Institute of Technology, Warangal, India
'Department of Electrical Engineering, RVR & JC College of Engineering, Guntur, India
'Center for Electronics Design & Technology, Indian Institute of Science, Bangalore, India

Abstract In this paper, a new 5-level inverter system for an

open-end winding induction motor drive is described.
Multilevel inversion is achieved by feeding an open-end
winding induction motor with an asymmetrical 3-level
inverter from one end and a 2-level inverter, from the other
end. The combined inverter system with open-end winding
induction motor produces voltage space vector locations
identical to a 5-level inverter. A total of 512-space vector
combinations are distributed over 61 space vector locations
in the proposed scheme. The proposed inverter drive scheme
is capable of producing a multilevel PWM waveform for the
phase voltage ranging from a 2-level waveform to a 5-level
waveform depending on the depth of modulation.

Keywords-

Multilevel inversion, Open-end winding

Induction motor drive

of the constituent 2-level inverters such an

underutilization is avoided in the present work.
In the scheme proposed in this paper, an open-end
winding induction motor is fed with an asymmetrical
three-level inverter at one end and a two-level inverter at
the other end. In the present work, asymmetrical threelevel inversion is obtained by connecting two 2-level
inverters with unequal DC-link voltages (in the ratio 1:2)
in cascade. The inverter scheme proposed in this paper
produces 61 voltage space vector locations. A total of 512
voltage space vector combinations are possible in this
scheme. The total number of constituent sectors in this
scheme is enhanced to 96. This results in a reduction of
the switching ripple in the motor phase voltage waveform.
11. PROPOSED POWER CIRCUIT CONFIGURATION

1. INTRODUCTION

Multilevel inversion with 5-levels and above is still on the

anvil and is a topic of extensive research though 3-level
inverters [ 11 are now being used for various applications.
Higher number of levels is obtainable with series
connected hybrid topology though these schemes are more
complex [2] [3]. It is shown in [4] and [5] that a dual
inverter drive system constituted by two-level inverters of
equal DC-link voltages feeding an induction motor with
open-end windings is capable of producing identical space
vector locations compared to a conventional three-level
inverter.
Reference [6] shows that a 4-level PWM waveform is
obtained from a dual inverter scheme with asymmetrical
DC link voltages, which are in the ratio 2: 1. The number
of triangular sectors with the topology described in [6] is
enhanced to 54, compared to a 3-level scheme, which
produces 24 sectors. A multilevel system that is capable
of realizing a PWM waveforms ranging from 2-level to 6level is described in [8]. In the topology described in [8], a
symmetrical 3-level inverter and a 2-level inverter feed an
induction motor with open-end windings. The three-level
inverter in [8] is constituted by the cascade connection of
two 2-level inverters with equal DC-link voltages [9].
In this paper, a multilevel topology that is capable of
.producing a PWM waveform ranging from 2-levels to 5levels for the motor phase voltage for an open-end
winding induction motor drive is proposed. Though the
scheme reported in [8] is capable of 5-level inversion in a
certain range of modulation, underutilization of DC-link
voltages takes place only when operation up to 5-levels is
required. With the redistribution of the DC-link voltages

The circuit topology proposed to realize a multilevel

phase voltage is depicted in Fig.1. In this circuit
configuration, a 3-level inverter realized by the cascade
connection of two 2-level inverters (inverter- 1 and
inverter-2 in Fig. 1) feeds an open-end winding induction
motor, while a 2-level inverter (inverter-3, Fig.1) feeds it
at the other end. The DC-link voltages of inverter-1,
inverter-2 and inverter-3 respectively are VJ4, VdJ2 and
vdc/4, where Vdc is the DC-link voltage of an equivalent
conventional single 2-level inverter drive. The pole
voltage, of any phase for inverter-2, for example
V A I 0 (Fig. 1) attains a voltage of Vd& if the following
conditions are satisfied: (i) The top switch of that leg in
inverter-2, in this case Szl, is tumed on, (ii) The bottom
switch of the corresponding leg in inverter-1, in this case
S14,is tumed on (Fig. 1).
Similarly the pole voltage of any phase in inverter-2, for
example vAZO
attains a voltage of 3Vdc/4, if the following
conditions are satisfied: (i) The top switch of that leg in
inverter-2, in this case Szl, is turned on, (ii) The top
switch of the corresponding leg in inverter-1, in this case
S II , is turned on (Fig. 1).
Thus, the DC-input points of individual phases of
inverter-2 may be connected to a DC-link voltage of either
3Vd& or vd,/2 by turning on the top switch or the bottom
switch of the corresponding phase leg in inverterl.
Additionally, the pole voltage of a given phase in inverter2 attains a voltage of zero, if the bottom switch of the
corresponding leg in inverter-2 is tumed on.

199

Fig. I Sehcmatie circuit diagram of the proposed 5-level inverter drive sehemc

and inverter-2 can individually assume 8 states. Also,

inverter-3 can assume 8 states independently of the 3level inverter. Thus, the number of resultant space vector
combinations for the combined system is equal to 5 12 i.e.
(64 x 8) distributed over 61 locations.
The difference in the pole voltages, for example ( v A ~-o
vA30.) (Table l), contains harmonic components of the
triplen order. All these components are dropped across the
points 0 and 0 (Fig.1) as isolated power supplies are
employed to power the individual inverters.
Consequently, the motor phase voltage does not possess
the harmonic components of the triplen order. The triplen
harmonic currents are absent in the motor phases for the
lack of a return path.

Thus, the pole voltage of a given phase for inverter-2 is

capable of assuming one of the three possible values- 0,
Vdc/2 and 3Vdc14,which is the characteristic of a three
level inverter. It may be noted that the switching levels of
this inverter are asymmetrical. This configuration of 3level inverter eliminates the neutral- point fluctuations
associated with the conventional neutral clamped 3-level
inverter [ l ] as the capacitors C, and Cz do not carry the
load current but only the ripple currents but only the
ripple currents. Also, the fast recovery neutral clamping
diodes are eliminated in this topology of 3-level inverter.
This 3-level inverter can be synthesized by reconnecting
two existing 2-level inverters as a retrofit. However, three
switching devices - SZ2,S24 and S 2 6 are to be rated for a
DC-link voltage of 0.75 Vdc. The pole voltages of the 2level inverter (inverter-3, e.g. v A 3 O q ) assume one of the
two values - either 0 or Vdc/4, depending on whether the
top switch or the bottom switch of a given phase leg is
tumed on. Thus, it is evident that, each of the three phases
of the motor can attain five distinct voltage levels as
shown in Table- 1.
Fig.2a depicts the voltage space vector combinations
from the asymmetrical three-level inverter (left) and the
two-level inverter (right) respectively. The resultant
space vector combinations due to the combined action of
these two inverters are also depicted in Fig.2b. It can be
observed from Fig.2b that proposed inverter system is
capable of producing a total of 96 sectors, organized into
four layers, similar to those produced in a conventional 5level inverter. It may be noted that the three-level inverter
can assume 64 space vector combinations as inverter-1

TABLE I
POLE VOLTAGES OF THE INDIVIDUAL INVERTERS AND
THE MOTOR PHASE VOLTAGE
Pole-voltage of
Polc-voltage of
3- level inverter (vA~o) 2-lcvl inverter (vA;o,)

200

VdJ4

VdJ2

VdJ4

VdJ2

3Vd4

Motor phase voltage

VAZA; =VAIO. V A ; ~
(VAZA;)

300

200
1OQ

Q
-1 013
-200

-300

-200

200

-200

200

Fig.Za Thc spacc vcctor locations for thc asymmctrical 3-lcvcl invcrtcr (Icft) and thc 2-lcvcl invcrtcr (nght)

400
I

. .

300

-400

-200

200

Fig.Zb Thc combined spacc vcctor locations for thc proposcd 5-lcvcl invcrtcr drivc schcmc i.e. thc rcsultant of both thc invcrtcrs

inverters in the lower and the middle speed range. When

inverter-1 is clamped to a state of 8(---), the DC-input
points for inverter-2 are all connected to the DC-link
voltage of ~,,,/2.Hence the pole voltage of inverter-2, v A ~ o ,
can assume one of the states - 0 or v d 2 . The pole voltage
of inverter-3, vA30, can assume one of the states - 0 o r .
v,,,/4. Thus, the ratio of the DC-link voltages connected at
either end of the open-end winding induction motor is
equal to 2:l and up to the middle speed range of
operation, the proposed power circuit configuration
behaves exactly similar to the four-level drive described
in [6].

In the proposed PWM scheme, only inverter-3 is switched

in the lowest range of modulation (or speed with Vlf
mode of operation), while inverter- 1 and inverter-2 are
both clamped to a state of 8(---). In the middle range of
modulation (speed), inverter-2 and inverter-3 are
switched, while in the higher range of modulation, all the
three inverters are switched. Since inverter- 1 and inverter2 are not switched in the lowest speed range, the
switching losses are due entirely to the switching of
inverter-3. Similarly in the middle speed range, the
switching losses are due to the switching of inverter-2 and
inverter-3 only.
Fig.3 shows the voltage space vector locations and the
voltage space vector combinations of the individual

20 1

Fig.) Thc voltagc space vcctor locations for thc proposcd 5-lcvcl invcrtcr topology with invcrtcr-l clampcd to a statc of S(---).
Ill. SWITCHING STRATEGY AND PWM PATTERN GENERATION

The 61 voltage space vector locations form the vertices

of 96 equilateral triangles, which are referred to as sectors
(Fig.2b and Fig.3). These sectors are distributed into four
layers (Fig.2b and Fig.3). The equilateral triangles
numbered 'I' through '6' in the inner most layer are
referred to as 'inner sectors' (Fig.3). Layer-2 consists of
the sectors numbered - '7' through '24' and layer-3 consists
of the sectors numbered - '25' through '54' (Fig.3). The
rest of the sectors constitute layer-4 (Fig.2b).
Six adjacent sectors constitute a sub-hexagon. Thirtyseven such sub-hexagons can be identified with the
present scheme (Fig.2, bottom). In addition, there is one
inner sub-hexagon with its center at 0 (Fig.3). Each outer
sector can be mapped to the inner sector by shifting the
outer sub- hexagonal center to the inner hexagonal center,
i.e. '0' in Fig.3.
In this paper, the method employed to determine the
timing periods To, TI and T2 to realize the reference
voltage space vector vSr,using space vector modulation
involves the following steps:
(i)
(ii)
(iii)

(iv)
(v)

corresponding sector in the inner most subhexagon .

Determining the time periods To, T I and T2 to
realize the mapped reference voltage space
vector in the inner most hexagon [ 5 ] ;
Employing these time periods to switch the
space vector combinations available at the
vertices forming the sector in which the tip of
the reference slpace vector is situated [5] [7].

Thus, this procedure is (conceptually equivalent to realize

the mapped reference slpace vector in the inner hexagon
and applying a vectored offset to realize the actual
reference space vector in the outer sector. It may be noted
that this procedure ensuires that the reference space vector
is realized by switching amongst the three vertices, which
are situated in the closest proximity to the tip of the actual
reference space vector. Consequently, the switching ripple
in the output voltage waveform is minimized.

Finding the sector in which the tip of the

reference space vector is situated;
Finding the outer sub-hexagon to which the
sector belongs;
Shifting the outer sub-hexagonal center to the
inner most hexagonal center using an
appropriate coordinate transformation so that the
reference voltage space vector is mapped to the

IV. SIMULATION RESULTS AND DISCUSSION

The proposed scheme is simulated in open loop with

V/f control. The respective DC-bus voltages are vd,/4, vd,/2
and v,,J~ for inverter-1, inverter-2 and inverter-3. This
means that the
DC-bus voltage of an equivalent
conventional 2-level inverter drive is Vdc. Look-up tables

202

are employed for the generation of PWM signals in each

layer. A DC-bus voltage (V,,) of 400V is assumed for
simulation studies.
The motor phase voltage waveform for Iv,, I = 0. 15Vdc
are presented in Fig.4. In this case, the tip of the reference
voltage space vector v,, is confined to the sectors of the
inner hexagon i.e. 1 to 6. As mentioned in section-2, only
inverter-3 is switched in this case. Similar simulation
results are presented for Iv,, I = O.375Vdc. In this case, the
tip of the reference voltage vector is confined to the layer2, which consists of sectors numbered '7' through '24'.
In this operating region, inverter-2 and inverter-3 are
switched while inverter-1 is clamped to a state of 'ST(---).
Fig5 shows the waveforms of the motor phase voltage. In
this case, the motor phase voltage shows a 3-level
waveform.

Similar conclusions can be drawn from the simulation

result shown in Fig.6 corresponding to the case lvsr[
=0.6Vd,. In this operating condition, the tip of v,, is
situated exclusively in the sectors of layer-3 (sectors
numbered '25' through '54', Fig.3). In this region also,
inverter-1 is clamped to a state of '8'(---). In this case, the
motor phase voltage shows a 4-level waveform. Fig.7
illustrates the simulated result obtained when the tip of v,,
is forced to be within the layer-4 (Fig.2b) and corresponds
to the case of lvsrl = O.8Vdc. Unlike the three previous
cases, all the inverters are switched in this speed range.
The motor phase voltage is further refined, showing a
waveform similar to the one obtained in a conventional
five-level voltage source inverter.

100
80

m
40

g o
20
-10
60
80

100

005

0.1

0.15

023

02

Time in Seconds

Tinie in Seconds

Fig 6 llic motor phasc voltagc vA2Aj

whcn lvsrl= 0 6 Vdc
(4-lcvcl invcrtcr wavcform)

Fig 4 The motor phasc voltagc vAzA; whcn lvsrl= 0 15 Vdi

(2-lcvcl invcrtcr wavcform)

i-..-..--.A".--".--

~~

OM

0%

0.w

3wI0 D l w s 0.01 OBt5

8.1

Om

0.03 0.03

O
h 0.b

0.65 0.k

Time ia Peeends

Tima In Semnds

Fig7 Thc motor phasc voltagc VA2Aj whcn ivsrl = 0.8 Vdc
(5-lcvcl invcrtcr wnvcform)

Fig 5 Thc motor phasc voltagc vA?Ajwhcn lvsrl= 0 375 VdL

(3-lcvcl invcrtcr wavcform)

203

V. CONCLUSION

A 5-level inverter drive scheme for an open-end

winding induction motor is presented. An asymmetrical 3level inverter feeds the open-end winding induction motor
from one end and a 2-level inverter from the other end. A
total of 512 voltage space vector combinations are
present, distributed over 61 space vector locations. The 3level inverter used in this scheme is realized by
connecting two 2-level inverters in cascade. The fast
recovery neutral point clamping diodes are not needed in
this 3-level inverter. Connecting two existing two-level
inverters as a retrofit can easily constitute this 3-level
inverter.
If it is intended to obtain motor phase waveforms ranging
from 2-level to 5-level in PWM operation, this scheme is
to be preferred to the one proposed in [8] as it would
result in a better DC bus utilization.
A controlled AC to DC converter is needed for the low
voltage 2-level inverter to use all the space vector
combinations. The motor phase voltage in the proposed
inverter scheme shows a 2-level PWM phase voltage
waveform in the lowest modulation range, a 3-level or a
4-level PWM phase voltage waveform in the medium
range and a 5-level PWM phase voltage waveform in the
higher modulation range.

[SI V.T. Somasckhar , K. Gopakumar, M.R. Baiju,

K.K. Mohapatra, "A Multilcvcl lnvcrtcr Systcm for an
Induction Motor with Opcri-cnd Windings",
Proc. IEEE IECON - 2002.
[9] V.T. Somasckhar, K.Gopakumar, " Thrcc-lcvcl invcrtcr
configuration cascading two two-lcvcl invcrtcrs",
IEE Proc.- Elcctr. Powcr Appl. Vol. 150, No.3, May
2003, pp.245 - 254.

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I

204