Introductory Lectures in VLSI Physical Design Algorithms

Jens Lienig, Springer Verlag Berlin Heidelberg New York, 2006

Introduction

1.1
1.2
1.3
1.4
1.5

Electronic Design Automation (EDA)

About this Book
Impact of Electronic Design Automation
History of Electronic Design Automation
VLSI Design Cycle
1.5.1
System Specification
1.5.2
Architectural Design
1.5.3
Functional Design
1.5.4
Logic Design
1.5.5
Physical Design
1.5.6
Layout Verification
1.5.7
Fabrication
1.5.8
Packaging, Testing
1.6
Layout Design Styles
1.6.1
Full-Custom
1.6.2
Standard Cells
1.6.3
Macro Cells
1.6.4
Gate Arrays
1.7
Layout Layers
1.8
Design Rules
1.9
Optimization Problems of Physical Design
1.10
Computational Complexity of Physical Design
1.11
Classification of Physical Design Algorithms
1.12
Solution Quality
1.13
Basic Terms and Definitions in Graph Theory
1.14
Terminology
Bibliography

3
4
6
7
9
9
10
10
10
11
12
13
13
14
14
15
17
17
19
20
21
23
25
27
27
30
34

37

Partitioning

2.1
2.2
2.3

Introduction
Terminology
Objective Functions
2.3.1
External Wiring
2.3.2
Bounded Size Partitioning
2.4
Partitioning Algorithms
2.4.1
Kernighan-Lin (KL) Algorithm
2.4.2
Extensions of Kernighan-Lin Algorithm
2.4.3
Fiduccia-Mattheyses (FM) Algorithm
2.4.4
Simulated Annealing (SA) Algorithm
Exercises
Bibliography

37
38
39
39
40
40
41
45
46
54
60
60

Floorplanning

63

3.1
3.2

Introduction
Objective Functions
3.2.1
Area of the Bounding Box
3.2.2
Overall Wirelength
3.2.3
Area and Overall Wirelength
3.2.4
Signal Delays
Terminology
Floorplanning Algorithms
3.4.1
Floorplan-Sizing Algorithm
3.4.2
Cluster Growth
3.4.3
Other Floorplanning Algorithms

63
65
65
65
66
66
66
70
70
76
80

3.3
3.4

3.5

Pin Assignment
3.5.1
Problem Definition
3.5.2
Concentric Circle Mapping
3.5.3
Topological Pin Assignment
Exercises
Bibliography

81
81
82
84
86
88

91

Placement

4.1
4.2

Introduction
Objective Functions
4.2.1
Overall Weighted Wirelength
4.2.2
Maximum Cut
4.2.3
Local Density
4.2.4
Signal Delays
4.3
Placement Algorithms
4.3.1
Min-Cut Placement
4.3.2
Min-Cut Placement with Terminal Propagation
4.3.3
Force Directed Placement
4.3.4
Simulated Annealing
4.3.5
Quadratic Assignment
4.3.6
Other Placement Algorithms
Exercises
Bibliography

91
92
93
95
97
98
99
100
104
106
110
114
117
123
124

129

Global Routing

5.1

Introduction
5.1.1
General Routing Problem
5.1.2
Global Routing
5.2
Terminology
5.3
Objective Functions
5.3.1
Full-Custom
5.3.2
Standard Cells
5.3.3
Gate Arrays
5.4
Routing Regions Representation
5.5
Outline of Global Routing
5.6
Global Routing Algorithms
5.6.1
Steiner Tree Routing
5.6.2
Graph-based Global Routing by Maze Running
5.6.3
Path Search with Dijkstra Algorithm
Exercises
Bibliography

129
129
130
131
135
135
136
138
138
140
141
142
146
150
155
156

Detailed Routing

159

6.1
6.2
6.3

Introduction
Terminology
Constraint Graphs
6.3.1
Horizontal Constraint Graph
6.3.2
Vertical Constraint Graph
Objective Functions
Algorithms for Channel Routing
6.5.1
Left-Edge Algorithm
6.5.2
Dogleg Left-Edge Algorithm
6.5.3
Greedy Channel Router
Switchbox Routing
6.6.1
Problem Formulation
6.6.2
Algorithms for Switchbox Routing
OTC Routing
6.7.1
Problem Formulation

159
159
163
163
164
167
167
167
169
172
176
176
177
178
178

6.4
6.5

6.6
6.7

6.7.2
Exercises
Bibliography

Algorithms for OTC Routing

Area Routing

7.1
7.2
7.3
7.4
7.5
7.6
7.7

180
182
183

187

Introduction
Terminology
Ordering of Nets
Manhattan and Euclidean Metrics
Routing of Power and Ground Nets
Objective Functions
Sequential Routing Algorithms
7.7.1
Lee Algorithm
7.7.2
Maze Routing with Weighted Paths
7.7.3
Line Search Algorithms
7.8
Semi-Parallel Routing
7.8.1
Hierarchical Routing
7.8.2
Rip-Up and Reroute
7.9
Three-Dimensional Routing
7.9.1
Maze Routing
7.9.2
Multiple Stage Routing
7.9.3
Planar Routing
7.9.4
Tower Routing
7.10
X-Routing
7.10.1 Octilinear Minimum Steiner Trees
7.10.2 Octilinear Path Search
Exercises
Bibliography

187
189
191
193
194
196
197
197
203
207
211
211
212
215
216
217
217
218
220
220
222
223
225

229

Compaction

8.1
8.2
8.3
8.4

Introduction
Terminology
Symbolic Layout
Compaction Algorithms
8.4.1
Virtual Grid Compaction
8.4.2
Constraint Graph Compaction
Exercises
Bibliography

229
230
232
233
233
236
242
243

Appendix A Solutions to the Exercises

247

Chapter 2. Partitioning
Chapter 3. Floorplanning
Chapter 4. Placement
Chapter 5. Global Routing
Chapter 6. Detailed Routing
Chapter 7. Area Routing
Chapter 8. Compaction

Appendix B Terminology, Symbols, File Formats

B.1
B.2
B.3
B.4

Abbreviations and Terminology in Physical Design

Schematic Symbols of Devices and Cells
Layout Examples of CMOS Standard-Cells
Layout File Formats

Subject Index

247
249
251
253
254
257
259

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270