Combinational Circuits- 1

Combinational Circuits
Two classes of logic circuits:
Combinational Circuits
Sequential Circuits
A Combinational circuit consists of logic gates
Output depends only on input
A Sequential circuit consists of logic gates and memory
Output depends on current inputs and previous output
(stored in memory)
Memory defines the state of the circuit.

Combinational Circuits

n inputs

Combinational
Circuits

m outputs

A combinational circuit has:

n Boolean inputs (1 or more)
m Boolean outputs (1 or more)
logic gates mapping the inputs to the outputs

Designing Combinational Circuits

How to design a combinational circuit?
Use all the information and tools you learned
Binary system, Boolean Algebra, K-Maps, etc.

Follow the step-by-step procedure given next

Design Procedure
1. Specification
Write a specification for the circuit if one is not
already available
Specify/Label input and output
2. Formulation
Derive a truth table or initial Boolean equations that
define the required relationships between the inputs
and outputs, if not in the specification
Apply hierarchical design if appropriate
3. Optimization
Apply 2-level and multiple-level optimization
(Boolean Algebra, K-Map, software)
Draw a logic diagram or provide a netlist for the
resulting circuit using ANDs, ORs, and inverters

Design Procedure (Cont.)

4.

Technology Mapping
Map the logic diagram or netlist to the implementation
technology selected (e.g. map into NANDs)
5. Verification
Verify the correctness of the final design manually or
using simulation

Practical Considerations:
Cost of gates (Number)
Maximum allowed delay
Fanin/Fanout

Example 1
Question: Design a circuit that has a 3-bit input and a
single output (F) specified as follows:
F = 0, when the input is less than (5)10
F = 1, otherwise

Solution:
Step 1 (Specification):
Label the inputs (3 bits) as X, Y, Z
X is the most significant bit, Z is the least significant bit

The output (1 bit) is F:

F = 1 (101)2, (110)2, (111)2
F = 0 other inputs

Example 1 (cont.)
Question: Design a circuit that has a 3-bit input and a
single output (F) specified as follows:
F = 0, when the input is less than (5)10
F = 1, otherwise
Solution:
Step 1 (Specification):
Label the inputs (3 bits) as X, Y, Z
X is the most significant bit, Z is the least significant
bit
Output (1 bit) is F:
F = 1 (101)2, (110)2, (111)2
F = 0 other inputs

Example 1 (cont.)

Step 3 (Optimization)

Step 2 (Formulation)
Obtain Truth table

YZ
X
0

00
0

01
0

11
0

10
0 F = XZ + XY

Circuit Diagram

Example 2
Question (BCD-to-Seven-Segment Decoder)

A seven-segment display is digital readout found in electronic devices

like clocks, TVs, etc.
Made of seven light-emitting diodes (LED) segments; each
segment is controlled separately.

A BCD-to-Seven-Segment decoder is a combinational circuit

Accepts a decimal digit in BCD (input)
Generates appropriate outputs for the segments to display the
input decimal digit (output)

Example 2 (cont.)

Step 1 (Specification):
4 inputs (A, B, C, D)
7 outputs (a, b, c, d, e, f, g)
a b c d e f g

BCD-to-SevenSegment
Decoder

A B C D

Example 2 (cont.)
Step 2 (Formulation)
BCD Input

7 Segment Decoder

Decimal

10-15

All Other Inputs

Invalid
BCD
codes
=
No Light

Example 2 (cont.)
Step 3 (Optimization)

Example 2 (cont.)

Step 3 (Optimization) (cont.)

a = AC + ABD + ABC + BCD

b = AB + ACD + ACD + BC
c = AB + BC + AC + AD
d = ACD + ABC + BCD+ABC+ABCD
e = ACD + BCD
f = ABC + ACD + ABD + ABC
g = ACD + ABC + ABC + ABC
Exercise: Draw the circuit

Arithmetic Circuit

Arithmetic Logic Unit (ALU) is main component that

performs arithmetic and logical operations on data in a
digital computer

Inside ALU circuit, arithmetic operations like addition and

subtraction are done by using adders and gates
Half adder circuit is used to add two number of single
binary bit
A full adder circuit is used to add three number of single bit
2s complement addition-subtraction circuits are basically
used to perform addition-subtraction function

Arithmetic Circuit
Half Adder
A

Truth Table

Input
Output
Augend Addend Sum Carry
A
B
S
Co
0
0
1
1

0
1
0
1

0
1
1
0

A
B

The circuit realization

B
1
1

0
0
0
1

K-Map for SUM

Equation for sum =AB+AB
=AB
Equation for Carry out, Co=A.B

CO

CO

Symbol for HA

Arithmetic Circuit
Full Adder
A full adder circuit has 3 inputs.
The extra input into this adder circuit is called carry in input corresponding to
the carry out from the previous bit position.
A2A1A0=111
B2B1B0= 101
1100

A0 + B0=1+1=1 0
Carry in
A1 +B1+1 =1+0+1=1 0
A2 +B2+1

Carry out=CO

=1+1+1=1 1

Arithmetic Circuit
Full Adder
A BCin
Input

Output

A B Cin

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

Sum()

0
1
1
0
1
0
0
1

1
Carry out
Co
0
0
0
1
0
1
1
1

Equation for Sum

=ABCin+ABCin +ABCin+ABCin
= ABCin
A BCin
1
1

Equation for Carry out, CO= AB+ACin+BCin

Arithmetic Circuit
Full Adder
A B
Cin

CO

Full Adder Circuit realization

A
B
C

F.A

Full Adder symbol

CO

Arithmetic Circuit
Full Adder using half adder
Full Adder can be constructed using two half adders
First half adder adds the two bits of the number and their sum is
added to the carry in bit in another half adder
Input

Output
HA#1
HA#2
Carry Out
A B Cin 1 CO1 2 () CO2 CO
AB AB 1Cin 1Cin CO1+CO2
00
00
01
01
10
10
11
11

0
1
0
1
0
1
0
1

0
0
1
1
1
1
0
0

0
0
0
0
0
0
1
1

0
1
1
0
1
0
0
1

0
0
0
1
0
1
0
0

0
0
0
1
0
1
1
1

Cin
A
B

1 HA#2
HA#1

CO1

2
()
CO2
CO

A Full Adder Circuit using two Half

Adder

Arithmetic Circuit
Full Adder using half adder
= ABCin
CO= CO1+CO2= AB+ (AB)Cin
=AB+(AB+AB) Cin
=AB(1+ Cin)+ABCin +AB Cin where 1+Cin=1
=AB+AB Cin+ABCin +AB Cin
=AB+AB Cin+ AB Cin +ABCin +AB Cin where AB Cin
=AB+ACin(B+B) +B Cin(A+A) where B+B=1
=AB+ACin+B Cin

Arithmetic Circuit

Binary Parallel Adder

1 0 0 0

Carry in

0101
+ 0110
1011
To add n-bit numbers:
Use n Full-Adders in parallel
The carries propagate as in addition by hand
This is an example of a hierarchical design
The circuit is broken into small blocks

Parallel Adders
C5

C 4 C3 C2 C1
A 4 A3 A2 A1
B 4 B3 B2 B1

CARRIES

S4

SUM

S3 S2 S1

Arithmetic Circuit
Binary Parallel Adder
To add n-bit numbers:
Use n Full-Adders in parallel
carries propagate as in addition by hand

This adder is called ripple carry adder

Arithmetic Circuit
Ripple Adder Delay
Assume gate delay = T, 8T to compute the last carry

Total delay = 8 + 1 = 9T, 1 delay form first half adder

Delay = (2n+1)T

Arithmetic Circuit
Parallel Adder
A 4 B4

A3 B3

FA #3

FA #2

Cout

S4

A2 B2

A1 B1

FA #1

HA #1

S2

S1

S3

A - 4 bit Parallel Adder

A 4 B4

A3 B3

FA #3

FA #2

Cout

S4

A2 B2

A1 B1

FA #1

FA#1

S2

S1

S3

A - 4 bit Parallel Adder

C1

Arithmetic Circuit
Parallel Adder
B4
16

S4 COUT Cin GND B1 A1

15

14

13

12

11

S1

10

IC-7483
1

A4

S3

A3

B3

+5V S2 B2

A2

Fig.6: IC-7483
B8 B7 B6 B5 A8 A7 A6 A5
+5V 5

16 4 7 11 1 3 8 10
13 Cin
IC-7483
12
14
15 2 6 9
Cout

S8 S7 S6

B4 B3 B2 B1 A4 A3 A2 A1
+5V 5

16 4

7
Cin
13

12

S5
A 8-bit Adder using IC-7483

14
Cout

15
S4

11 1 3 8
IC-7483
2
6 9
S3 S2

S1

10
13

Cin

Arithmetic Circuit
Subtraction (2s Complement)
How to build a subtractor using 2s
complement?

S = A + ( -B)

Arithmetic Circuit
Half subtractor
Consider A is minuend, B is subtrahend, Di is difference and Bo is borrow.
Case-I
Case-II
Case-III
Case-IV
Bo
0
1
0
0
A
0
0
1
1
B
0
1
0
1
0
-1
1
0
Di
Minus sign in case II indicates that a borrow from next higher is required

A B
Inputs Output
A B Di Bo
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0

A
B

Di
BO

1
Di =AB+AB
=AB

BO=AB

A
B

H.S

Di
BO

Arithmetic Circuit
Full Subtracter
A
0
0
0
0
1
1
1
1

B
0
0
1
1
0
0
1
1

Bin
0
1
0
1
0
1
0
1

A B
Bin

D
0
1
1
0
1
0
0
1

BO
0
1
1
1
0
0
0
1

BBin

A BBin
1

B = AB +A Bin + BBin

A
B
Bin
BO

1
1

D = ABBin + ABBin
+ABB0n+ ABBin
=ABBin
D

F.S

D
BO

Arithmetic Circuit
Full Subtracter
Bin

Di =ABBin

HS
A

HS
Bo

Bin(AB)

D
A B

Bin
FS
A
B

Di
Bo

Symbol for full adder

Bo

AB+Bin(AB)

Arithmetic Circuit
Adder/Subtracter
Invert

Input
Output
A Invert
Y
0
0
0
1
0
1

Controlled Inverter
1. when Invert=0 , then Y=A
2. When Invert=1, then Y= A.

0
1

AB

S or Di =AB
Invert

Y
A Half Adder/Half Subtracter

1
1

1
0

Remark
Y=A

Y=A

If Invert=0, then Y= AB and the

circuit performs addition function.
If Invert=0, then Y= AB and the
circuit performs subtraction.

Arithmetic Circuit
Subtraction (2s Complement)
How to build a subtractor using 2s
complement?

S = A + ( -B)

Arithmetic Circuit
2's Complement Adder/Subtracter
A4

A3

A2

A1
INVERT

A4

A3

A4

A3

A 4 B4

A2 A1
A2
A3 B3

A1

If
If

INVERT input =1
INVERT input =0

A2 B2

A1 B1
INVERT

Cin
FA #4

Cout

S4

FA #3

S3

FA #2

S2

FA #1

S1

A - 4 bit 2's complement Adder/Subtracter

Arithmetic Circuit
2's Complement Adder/Subtracter
A4 A3 A2 A1 B4

B3

B2

B1

1 2 4 5 9 10 12 13

INVERT
IC-7486

3
+5V 5

11

1 3 8 Cin
10 16 4
13
IC-7483

13

12
14
Cout

15

S4 S3 S2

11

Cin

9
S1

2's complement Adder/Subtracter using IC-7483 and IC-7486

Combinational Circuits-II

Functional Blocks
Digital systems consists of many
components (blocks)
Useful blocks needed in many designs

Arithmetic blocks
Decoders
Encoders
Multiplexers

Examples
of
MSI devices

Decoder

n inputs

n-to-2n
.

Decoder

.
.

2n outputs

Information is represented by binary codes

Decoding - the conversion of an n-bit input code to an
m-bit output code with n <= m <= 2n such that each
valid code word produces a unique output code
Circuits that perform decoding are called decoders
A decoder is a minterm generator

Decoder (Uses)
Decode a 3-bit op-codes:

op0
op1
op2

3-to-8
Decoder

Add
Sub
And
Xor
Not
Load
Store
Jump

Home automation:

C0
C1

2-to-4
Decoder

Light
A/C
Door
Light-A/C

Decoder with Enable

A decoder can have an additional input signal called the
enable which enables or disables the output generated by
the decoder

n inputs

n-to-2n
.

Decoder
Enable bit

.
.
.

2n outputs

2-to-4 Decoder
A 2-to-4 Decoder
2 inputs (A1, A0)
22 = 4 outputs (D3, D2, D1, D0)

2-to-4 Decoder
A 2-to-4 Decoder
2 inputs (A1, A0)
22 = 4 outputs (D3, D2, D1, D0)

Truth Table

A1

A0

D0

D1

D2

D3

2-to-4 Decoder
A 2-to-4 Decoder
2 inputs (A1, A0)
22 = 4 outputs (D3, D2, D1, D0)

Truth Table

A1

A0

D0

D1

D2

D3

2-to-4 Decoder with Enable

Truth Table
EN

A1

A0

D0

D1

D2

D3

2-to-4 Decoder with Enable

Truth Table
EN

A1

A0

D0

D1

D2

D3

3-to-8 Decoder

A0
A1
A2

D0
D1
D2
3-to-8 D3
Decoder D4
D5
D6
D7

3-to-8 Decoder
A2 A1 A0 D0 D1 D2 D3 D4 D5 D6 D7

A0
A1
A2

D0
D1
D2
3-to-8 D3
Decoder D4
D5
D6
D7

3-to-8 Decoder

A0
A1
A2

D0
D1
D2
3-to-8 D3
Decoder D4
D5
D6
D7

3-to-8 Decoder (using 2 2-to-4 decoders)

A0
A1
A2

D0
D1
D2
3-to-8 D3
Decoder D4
D5
D6
D7

A0
A1

2-to-4
Decoder
E

D0
D1
D2
D3

A2

A0
A1

2-to-4
Decoder
E

D4
D5
D6
D7

Encoder
2n inputs

.
.
.

2n-to-n
Encoder

n outputs

Encoding - the opposite of decoding - the conversion of an mbit input code to a n-bit output code with n m 2n such that
each valid code word produces a unique output code
Circuits that perform encoding are called encoders
An encoder has 2n (or fewer) input lines and n output lines
which generate the binary code corresponding to the input
values
Typically, an encoder converts a code containing exactly one
bit that is 1 to a binary code corresponding to the position in
which the 1 appears.

8-to-3 Encoder
D0
D1
D2
A0
D3 8-to-3
D4 Encoder A1
A2
D5
D6
D7

Description:
23 = 8 inputs, 3 outputs
one input =1, others = 0s
Each input generate unique
binary code

8-to-3 Encoder (truth table)

inputs
D0
D1
D2
A0
D3 8-to-3
D4 Encoder A1
A2
D5
D6
D7

outputs

D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0
0

8-to-3 Encoder (truth table)

inputs
1
0
0
0
0
0
0
0

D0
D1
D2
A0
D3 8-to-3
D4 Encoder A1
A2
D5
D6
D7

outputs

D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0
0
0
0

8-to-3 Encoder (truth table)

inputs
0
1
0
0
0
0
0
0

D0
D1
D2
A0
D3 8-to-3
D4 Encoder A1
A2
D5
D6
D7

outputs

D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0
1
0
0

8-to-3 Encoder (truth table)

inputs
0
0
0
0
0
1
0
0

D0
D1
D2
A0
D3 8-to-3
D4 Encoder A1
A2
D5
D6
D7

outputs

D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0
1
0
1

8-to-3 Encoder (truth table)

inputs
0
0
0
0
0
0
0
1

D0
D1
D2
A0
D3 8-to-3
D4 Encoder A1
A2
D5
D6
D7

outputs

D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0
1
1
1

8-to-3 Encoder (equations)

inputs
D0
D1
D2
A0
D3 8-to-3
D4 Encoder A1
A2
D5
D6
D7

Output equations:
A0 = ?
A1 = ?
A2 = ?

outputs

D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0
0

8-to-3 Encoder (equations)

inputs
D0
D1
D2
A0
D3 8-to-3
D4 Encoder A1
A2
D5
D6
D7

Output equations:
A0 = D1 + D3 + D5 + D7
A1 = ?
A2 = ?

outputs

D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0
0

8-to-3 Encoder (equations)

inputs
D0
D1
D2
A0
D3 8-to-3
D4 Encoder A1
A2
D5
D6
D7

Output equations:
A0 = D1 + D3 + D5 + D7
A1 = D2 + D3 + D6 + D7
A2 = ?

outputs

D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0
0

8-to-3 Encoder (equations)

inputs
D0
D1
D2
A0
D3 8-to-3
D4 Encoder A1
A2
D5
D6
D7

Output equations:
A0 = D1 + D3 + D5 + D7
A1 = D2 + D3 + D6 + D7
A2 = D4 + D5 + D6 + D7

outputs

D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0
0

8-to-3 Encoder (circuit)

D0
D1
D2
A0
D3 8-to-3
D4 Encoder A1
A2
D5
D6
D7

Output equations:
A0 = D1 + D3 + D5 + D7
A1 = D2 + D3 + D6 + D7
A2 = D4 + D5 + D6 + D7

D1
D3
D5
D7

A0

D2
D3
D6
D7

A1

D4
D5
D6
D7

A2

Multiplexers

A combinational circuit
Has a single output
Directs one of 2n input to the output
Choosing which input is done using n select lines

2n inputs

2n x 1
MUX

n select lines

one output

2x1 MUX
A 2x1 multiplexer (MUX) has 2 inputs, 1 output and 1
select line
D0
D1

2x1
MUX

S0

Y=D0 for S0=0, and Y=D1 for S0=1

Minimizing will result in: Y = S0.D0 + S0.D1
Exercise: Draw the circuit?

2x1 MUX
A 2x1 multiplexer (MUX) has 2 inputs, 1 output and 1
select line
D0
D1

2x1
MUX

S0

Y=D0 for S0=0, and Y=D1 for S0=1

Minimizing will result in: Y = S0.D0 + S0.D1
Exercise: Draw the circuit?

4x1 MUX

A 4x1 MUX has 4 input lines (D0, D1, D2, D3) , 1 output Y, and 2 Select
Lines (S0, S1)
The output for different select values is defined as:
D0
S0S1 = 00, Y = D0
S0S1 = 01, Y = D1
D1
4x1
S0S1 = 10, Y = D2
D2
MUX
S0S1 = 11, Y = D3
D3

Y = S1S0D0 + S1S0D1 + S1S0D2 + S1S0D3

The output Y depends on the minterms of the Select lines
Exercise: Draw the circuit?

S1 S0

4x1 MUX

A 4x1 MUX has 4 input lines (D0, D1, D2, D3) , 1 output Y, and 2 Select
Lines (S0, S1)
The output for different select values is defined as:
D0
S0S1 = 00, Y = D0
S0S1 = 01, Y = D1
D1
4x1
S0S1 = 10, Y = D2
D2
MUX
S0S1 = 11, Y = D3

Y = S1S0D0 + S1S0D1 + S1S0D2 + S1S0D3

The output Y depends on the minterms of the Select lines

Exercise: Draw the circuit?

D3

S1 S0

4x1 MUX

Quad 2x1 MUX

A MUX for two 4-bit
numbers.
Has a 4-bit output and a
single select line
Y = A If S0 = 0
Y = B if S0 = 1

A0
A1
A2
A3
B0
B1

QUAD
2X1
MUX

B2
B3

S0

Y0
Y1
Y2
Y3

Quad 2x1 MUX

Can be built using four 2x1 MUXes
A0
B0

2x1
MUX

Y0

A1
B1

S0
A2
B2

2x1
MUX
S0

2x1
MUX

Y1

S0
Y2

A3
B3

2x1
MUX
S0

Y3

DeMultiplexer
Performs the inverse operation of a MUX
It has one input and 2n outputs
The input is passed to one of the outputs based on the n
select line

one input

1 x 2n
DeMUX

n select lines

2n outputs

1x2 DeMUX
E

1x2
DeMUX

D0
D1

The circuit has an input E, the outputs are given by:

D0 = E, if S=0
D1 = E, if S=1

D0 = S E
D1 = S E

1x4 DeMUX
E

1x4
DeMUX

D0
D1
D2
D3

S1 S0

The circuit has an input E, the outputs are given by:

D0 = S1S0 E

D0 = E, if S0S1=00
D1 = S1S0 E

D1 = E, if S0S1=01
D2 = S1S0 E

D2 = E, if S0S1=10
D3 = S1S0 E

D3 = E, if S0S1=11

DeMUX vs Decoder
E

1x4
DeMUX

D0
D1
D2
D3

S1 S0

A 1x4 DeMUX is equivalent to a 2x4 Decoder with

an Enable
Think of S1S0 a the decoders input
Think of E as the decoders enable

In general, a DeMux is equivalent to a Decoder

with an Enable

DeMUX vs Decoder
2x4 Decoder Truth Table
EN

A1

A0

D0

D1

D2

D3

DeMUX vs Decoder
2x4 Decoder Truth Table
EN

A1

A0

D0

D1

D2

D3 Data/

S1/

S0/

To convert a 2x4 Decoder with an

Enable to a 1x4 DeMux:
Assign DeMuxs input (actual data) to EN
Assign DeMuxs selection lines (S1,S0) to
the inputs A1, A0

Summary
Useful Functional Blocks

Decoders
Encoders
Multiplexers
DeMultiplexers

All are examples of MSI devices

Can be used to build bigger systems