Comprehensive SoC Power Grid Verification

Using VoltageStorm

Authors:Navneet Mohindru, Lalit Garg

DFM, Cadence Design Systems, Inc.

1
Introduction:
Lower power supply voltages put todays large SoC designs at increased risk of voltage (IR) drop-related
failures due to the unpredictable power flow in and around embedded IP, analog and mixed signal blocks.
Currently the methodology for comprehensive SoC power grid verification at chip level is only accurate for
digital blocks as there is no accurate solution available for power grid characterization of analog and mixed
signal blocks.
This paper explains the new methodology in the VoltageStorm family of tools where user can run block
level IR drop analysis for the analog and mixed signal blocks using Virtuoso Analog VoltageStorm Option
(VAVO) inside the Custom IC environment. User can then create a VoltageStorm compatible powergrid
view for this block. This power grid view will provide user with an accurate characterization of analog and
mixed signal blocks for power analysis and can be used at the top level where user can analyze the power
grid for both the digital and analog/mixed signal blocks in a single run. This methodology will help user in
leveraging the speed and capacity advantages of the VoltageStorm hierarchical flow and accurate modeling
of analog/mixed signal block. In addition to this, user can do both static and dynamic IR drop analysis at
the top level.
The proposed methodology involves the following steps:
1.
2.
3.
4.

Characterization of standard cells and memories using VoltageStorm-Libgen flow.

Characterization of Analog/Mixed Signal blocks using Assura RCX/Ultrasim and VAVO.
Analysis of digital blocks and creation of hierarchical power grid views.
Full chip power grid analysis by VoltageStorm using power grid views created in steps 1, 2 and 3.

2
Static and dynamic IR drop analysis using VoltageStorm
VoltageStorm supports static IR drop analysis, dynamic IR drop analysis and a mixed flow that supports
both static and dynamic IR drop analysis . The static IR drop flow lets users verify that the power rails are
sufficiently robust before using dynamic IR drop analysis to optimize power rails and de-coupling
capacitance.

Static/Dynamic IR Drop Flow Diagram

2.1 Static IR Drop Flow

The static IR drop flow establishes a baseline for the designer for IR drop analysis before he runs dynamic
IR drop flow. Static power rail verification shows static IR drop and Electromigration problems caused by

open circuits in power rails, missing vias or via arrays, high current densities and insufficient widths of
power rails.
Static IR drop flow takes into account instance based average power calculated by PowerMeter.
PowerMeter calculates the average power consumption for each instance in a digital design as a function of
the switching activity for each net and instance in the design. It uses a probabilistic approach to calculate
the switching of each net in the design. PowerMeter can handle not only standard cell designs but also
designs containing large number of memories, and IP blocks. As output, PowerMeter generates an instancebased power consumption file containing data on leakage power, internal power, and switching power. You
can use this text output to provide VoltageStorm with the required instance-based power consumption.
PowerMeter supports three methods for calculating instance-based power consumption: VCD-based,
AccuraTM-based, or a mixture of the two methods. The VCD-based method assumes that you can provide
switching information in a VCD for each net in the design. The Accura method of calculating instancebased power consumption is based on a probabilistic approach to calculate the switching activity of each
net in the design. PowerMeter starts the calculation at the primary inputs of the design. It uses the
connectivity information between the instances as well as the logic functionality of the cells while
propagating the switching probability throughout the design. For the IP/memory, PowerMeter uses the gate
level netlist in the power grid view to propagate the switching probability. You can also use a mixture of
the two methods. The switching activity at the primary inputs can then be used as seed information for
Accura for the propagation of switching probabilities throughout the design.
2.2

Dynamic IR drop Flow

Dynamic IR drop flow enables designers to check the transient IR drop on top of the baseline established
by static IR drop analysis. For 90nm and sub-90nm technologies leakage power plays important role in
power consumption. Hence optimization of decoupling caps which cause leakage power in design is very
important. The dynamic IR drop analysis also helps designers in determin ing the effectiveness of
decoupling capacitors added to power rails. The designer can use the plots shown by VoltageStorm to
optimize the decaps in design to ensure that both transient IR drop and leakage are minimized.
Dynamic IR drop flow requires the use of dynamic power consumption data for each instance output by
PowerMeter when you perform dynamic power grid analysis. Dynamic power consumption calculation is a
method of analyzing a circuit to obtain operating currents and voltages. It is time based, analyzing the
circuit netlist over a specified period, such as a clock cycle. PowerMeter uses two methods to calculate the
dynamic power consumption
1)
2)

The vector-driven approach uses the full VCD output of a logic simulator to identify the instances
that are switching and when they switch.
The vectorless approach uses timing arrival window information from a static timing analysis tool
to determine when instances switch. A timing arrival window describes when a signal changes
within a clock cycle. An additional algorithm then determines the instances that switch. This
method is called the vectorless or timing windows based or pseudo-dynamic approach.

SoC Hierarchical Analysis Methodology:

VoltageStorm uses power grid views for enabling the hierarchical solution. These power grid views contain
physical and electrical information that is used to model the power grid at the next level of hierarchy.
Different types of power grid views for a SoC design would include views for the standard cell library,
macro blocks, IP blocks, embedded memories, Analog/Mixed-signal blocks and I/O cells.

A power grid view is used to model power rail and power distribution information for each instance of the
design. Each power grid view contains a combination of topology and RC for each of the power rails within
a cell or block and the current distribution for each current tap. To increase capacity and performance of
VoltageStorm IR drop analysis flow a designer can contain multiple types of power grid views. To support
hierarchical static analysis there are four types of power grid views: Detailed, Reduced, Abstract and Port
(a detailed view that is most accurate). Static power grid views model the power routing as an R model and
contain static current sources/sinks to load the power rails. To support hierarchical dynamic analysis there
are three additional power grid views: Detailed Dynamic, Reduced Dynamic and Port. Dynamic power grid
views model the power routing as an RC model and contain dynamic current sources/sinks to load the
power rails.

Static Power Grid Views

Detailed

Reduced

Abstract

Port

Dynamic Power Grid Views

Detailed Dynamic

Reduced Dynamic

Port

For top level IR drop analysis , each block within the design (DEF or GDSII) is analyzed separately and
individual power rail analysis runs using VoltageStorm are executed. Once the power rail within a block is
proven robust, a power grid view of the block is created. Once all block power grid views are created, a
full-chip power rail verification can be executed. In this case, each instance of the SoC design is modeled
by a power grid view. The following sections describe how power grid views are generated for different
type of instances.
3.1

Standard Cells

Since the cells within a standard cell library are not like ly to suffer from any significant IR drop within the
cell, it is only necessary to create Port power grid views for these cells. However for dynamic IR drop
analysis, we need to create a detailed power grid view for CRC modeling of the standard cell. CRC
modeling consists of device capacitance, Ron resistance and load capacitance for that cell. The CRC
models are associated with port views by libgen when detailed views of standard cells are created in libgen
run. A designer can then use these port views for dynamic IR drop analysis as they have CRC models
associated with them.

3.2

Memory and Hard IP

Since memory and hard IP instances can contain complex logic, it is possible for these blocks to suffer
from IR drop within the instance. It is therefore necessary to create Detailed, Reduced, Abstract, Dynamic
Detailed or Dynamic Reduced power grid views for these blocks. To verify the power rails within a
memory or hard IP instance, a Detailed (static) or Dynamic Detailed (dynamic) power grid view should be
used initially. These detailed power grid views enable each instance to be validated for power rail integrity
down to the transistors connected to the power rails. Once the memory or hard IP has been proven to
contain robust power rails, further power rail verification including these instances can be completed using
the Reduced or Abstract power grid views. The use of reduced and abstract power grid views will not
compromise accuracy of the analysis results, but will significantly improve performance and capacity of the
full-chip analysis. There are two ways for creating detailed views for memory and hard IP instances:
1)

Libgen detailed view creation: This is an integrated flow in which device recognition from
Memory/IP GDS, RC extraction of power grids inside memory/IP and current tap calculation for
each transistor is done. This is the most common flow for generating detailed/reduced views.

2)

Transistor level VoltageStorm flow: For dynamic IR drop analysis, sometimes you need to
generate dynamic tap current for memory/IP block for worst case vector. This cannot be done
through the integrated libgen flow. This flow consists of the following steps:

3.3

1.

Device recognition and transistor level spice netlist creation from GDS2.

2.

Run Fire and Ice for RC extraction of power grid in GDS.

3.

Run dynamic transistor level simulation to calculate the dynamic tap currents for each
transistor.

4.

Perform analysis on the power grid extracted by Fire and Ice by using dynamic current
taps.

5.

Create detailed/reduced dynamic power grid views by running pr_pgv libgen flow on
analysis results of step 4.

Digital Blocks

For creating power grid views of digital blocks, static or dynamic IR drop analysis is run at block level first.
Here are the steps required for generating detailed/reduced power grid views for digital blocks.
1)
2)
3)
4)
5)

Calculate instance based average static current for static analysis or instance based dynamic
current for dynamic power analysis .
Run R or RC extraction (depending on whether you are doing static or dynamic analysis) on block
level power grid.
Merge the static or dynamic current with the power grid extracted from step 2.
Run static or dynamic analysis .
Generate detailed/reduced power grid view for the block from the analysis results of step 4.

3.4 Analog/Mixed signal Blocks

One of the key strengths of VoltageStorm is its ability to accurately characterize power consumption and
power distribution inside analog and mixed signal blocks. The VoltageStorm Analog (VAVO) option is
tightly integrated with the Virtuoso Analog Design Environment design creation product. It supports IR
drop and power rail Electromigration verification for analog and mixed signal designs. The VoltageStorm
Analog option combines with Assura LVS, Assura RCX, and Virtuoso Spectre / Ultrasim Circuit
Simulators to perform a full-chip circuit simulation specifically targeted for power grid integrity

verification. Power rail Electromigration is comprehensively checked for all interconnect segments and vias
within the power networks.
VAVO also enables users to create power grid views of analog or mixed signal blocks for full chip analysis
using VSPE or VSDG. The power integrity solution executes a complete circuit simulation taking into
account the impact of IR drop on both power and ground rails simultaneously. The power grid view
generated by VAVO contains a very accurate representation of power grid, current distribution and the port
information for the power nets. VA VO writes out all the required information for power grid view
generation and the LEF for the block as its output. Libgen, the power grid view library generator
application, that is a part of VSPE/VSDG reads VAVOs output and writes out power grid views for the
analog and mixed signal blocks.

Run Assura LVS/RCX to

create parasitic extracted
view

Netlist the design and

simulate using
Spectre/Ultrasim Simulator

Run VAVO PGV to create

the required information to
create a Voltagestorm PGV

Run Libgen to create

detailed power grid view for
the design.
A typical flow for creating a detailed power grid view using VAVO has the following steps:
1. Run LVS using Assura LVS on the analog or mixed signal block. This step is required as the LVS
output is a prerequisite for parasitic extraction using Assura RCX.
2. Extract at least the power and ground nets for power grid analysis using Assura RCX and write out
parasitics in an extracted DFII format. Both decoupled RC and R only extraction modes are
supported.
3.

Run a postlayout transient or DCOP simulation using the testbench and the extracted view within
the ADE environment. Spectre and Ultrasim are the supported simulators in this flow.

4.

VAVO uses the simulation results and the extracted view to dump out all the required data for
creation powergrid views. VAVO can also create a LEF for the block if it is not available. It can
also write out a libgen command file and call libgen in the pr_pgv flow to create the detailed
static/dynamic power grid view for the analog or mixed signal block.

The power grid views created using VAVO are accurate because Assura RCX has all advanced features to
take care of manufacturing effects that results in a very accurate grid inside the power grid view. Current
distribution is calculated using Spectre/Ultrasim simulation resulting in accurate current distribution in the
power grid view.
3.5

Top-level analysis

For top level IR drop analysis of SoC, the power grid view of each digital module /memory /hard IP
/analog-mixed signal is pulled to the top level run. Once the block level grid of digital modules/ memory/
analog is robust, the designer can use reduce views to improve runtime and capacity in the top level run.
The top level analysis in VoltageStorm is explained in the figure below:

4
Results and Observations
The above methodology was run on a customer SoC design. This design contains memories, digital blocks
and analog/mixed signal block (PLL). The results shown in the figures below highlight the integration of
the power grid view of PLL in top level run for the VSS net.

Figure 1: Static IR drop top level run with libgen detailed view of PLL

Figure 2: Static level top level run with VAVO detailed view of PLL

Figure 1 shows the results of top level static run with libgen detailed view. The figure shows a red spot
inside PLL which is a false warning because of incorrect current distribution. In Figure 2, the IR drop
coming from the VAVO power grid view is more uniform. The power grid views generated by VAVO for
the analog block are more accurate because of the following reasons:

1)
2)
3)

Device recognition is more accurate because Assura LVS is used to extract analog devices.
RCX is more accurate in extracting parasitics for non-manhattan geometry.
Tap current in VAVO is calculated from actual Spice-like simulation.

Conclusions

Here are conclusions from this methodology

1)
2)

Voltagestorm can analyze and characterize all types of blocks such as digital blocks, memories,
hard IPs and analog/mixed signal blocks accurately at SoC level.
The hierarchical flow of voltagestorm gives it infinite capacity since designer can create as many
power grid views as required and feed them into top level run.