Timing Issues and Clock Distribution

Lecture 10
18-322 Fall 2003
Textbook: [Sections 7.5, 10.1, 10.3]

Overview
Timing issues & clock distribution
System Performance Determination
Pipelining
Clock skew. Register timing
Counter clock skew

Review: Register Timing

cycle time

clk
setup time

Unstable data

hold time

Q
clk-to-Q (propagation) delay (tpFF)

Prentice Hall 1995

Sequential Systems: The Big Picture

Primary
Inputs

Combinational
Logic

Next
State

Current
State

Clock

Primary
Outputs

Memory
Elements
(Registers)

Maximum Clock Frequency

FFs

Speed of the sequential machine

(how fast can this machine be
clocked)
f = 1/T (clock frequency)
LOGIC
tp,comb

tp,FF + tp,comb + tsetup < T

Example: tp ~ 100ns =>

10MHz (limit on performance)

Setup Time
Required time for input to be stable
BEFORE CLOCK EDGE

Comb.
Logic
Data stable here
before clock here

Setup Time Fix

Data

This violation can be fixed by stretching the clock cycle

Data

OK

Setup Time Fix 2

Data

OR
by accelerating the combinational logic

Data

OK

Hold Time
Required time for input to be stable
AFTER CLOCK EDGE
Comb.
Logic
Data stable here
after clock here

Hold Time Violations

Prop Delay: 1 ns

Hold Time: 2 ns

Hold time violations are caused by short paths

Cannot be fixed by slowing down the clock!!!
Fixed by slowing down fast paths

Timing Analysis
Look for longest path: clock speed
Look for shortest paths: check hold time
Static Timing Analysis:
Attempt to determine longest/shortest path from schematic
Difficult problem
Know

the delay of logic elements, but cannot easily reason about

the entire design

False Paths
Example:

#4
#3
#2

Solutions:
Simulation
False Path Analysis

#3

Speeding up System Performance:

Pipelining

Non-pipelined version

REG

Pipelined version

log

REG

Out

REG

log

REG

REG

REG

a
REG

REG

tp,comb

Out

REG

log

REG

REG

REG

REG

How Good Is This?

Out

Pipelined version

Tmin,pipe = tp,reg + max(tp,ADD,tp,abs,tp,log ) + tsetup,reg

Pipelining is used to implement high-performance data-paths
Adding extra pipeline stages only makes sense up to a certain point

Overview
Timing issues & clock distribution
System Performance Determination
Pipelining
Clock skew. Register timing
Counter clock skew

Synchronous Pipelined Data-Path:

Clock Skew
Clock Rates as High as 1 GHz in CMOS!
A clock line behaves as a
distributed RC line

In

CL1

R1

ti

CL2

R2

CL3

R3
Out

tl,min t r,min

tl,max tr,max

Clock Edge Timing Depends upon Position

Each register sees a local

clock time depending on
their distance from the clock
source -> clock skew

= t t (> 0 or <0)
Clock skew can severely
affect the performance
Note: we assumed here
tsetup = 0

Constraints on Skew

t
R1

t = t +

tr,min + tl,min + ti

R2

data

If the local clock of R2 is delayed

w.r.t. R1, it might happen that the
inputs of R2 change before the
previous data is latched -> race
tr,min + ti + tl,min

earliest time
(a) Race between clock and data.

t + T =
t + T +

tr,max + tl,max + ti

R1

+ T

R2
data

worst-case

(b) Data should be stable before clock pulse is applied.

The correct input data is stable at R2

after the worst-case propagation
delay. The clock period must be
large enough for the computations to
settle.
T tr,max + ti + tl,max -

Clock Constraints in Edge-Triggered Logic

(1)
(2)

t r, min + t i + t l, min
T tr,max + t i + t l,max

Maximum Clock Skew Determined by Minimum Delay between Latches (condition 1)

Minimum Clock Period Determined by Maximum Delay between Latches (condition 2)

Positive and Negative Skew

The clock is routed in the same direction as data

(a) Positive skew

The skew has to satisfy (1)

Data

CL

CL

CL

If it violates (1), then the circuit

malfunction independently of the
clock period
Clock period decreases!!!

The clock is routed in the opposite direction of data

Data

CL

CL

CL

(b) Negative skew

(1) is satisfied implicitly. The
circuit operates correctly
independently of the skew
Clock period increases by | |

Overview
Timing issues & clock distribution
Pipelining
Clock skew. Register timing
Counter clock skew

Countering Clock Skew

REG

REG

In

REG

REG

Negative Skew

log

Out

Positive Skew

Clock Distribution

Data and Clock Routing

Goal: clock skew between registers is bounded!

(What matters is the relative skew between communicating registers.)

Clock Distribution: H-Trees

clk

Every branch sees the same wire length and capacitance

The clock skew is theoretically zero
The sub-blocks should be small enough s.t. the skew within the block is tolerable
It is essential to consider clock distribution early in the design process

Clock distribution is a major design problem!

Clock Network with Distributed Buffering

Local Area

Module

Module
secondary clock drivers

Module

Module

Module

Module

main clock driver

CLOCK

Reduces absolute delay, and makes Power-Down easier

Sensitive to variations in Buffer Delay

DEC Alpha 21164

Clock Drivers

9.3 M Transistors, 4 metal layers, 0.55m

Clock Freq: 300 MHz
Clock Load: 3.75 nF
Power in Clock = 20W (out of 50W)
Two Level Clock Distribution:
oSingle 6-stage driver at center
oSecondary buffers drive left and right
side
o Max clock skew less than 100psec
oRouting the clock in the opposite
direction
oProper timing

Clock Skew in Alpha

Clock driver

Timing & Race Conditions: Example

Source
Destination

32-bit adder

Cin

Sum

32-bit
reg

32-bit
reg

32-bit
reg

R3

R4

R5

Cout

32-bit
reg

32-bit
reg

R2
R1

Cout

Cin

Cout

Cin

Sum

Sum

v
v

300fF

clk driver
150

~1mm wire
200, 100fF

Example (contd)
150

600fF

Find the skew between the source register

clock () and the destination ()

Check race condition

Find minimum clock period

model
200
50fF

50fF

900fF

t = 0.69 (150) (650) = 67ps

t = 0.69 [(150) (650) + (150 + 200)(950)] = 297ps
= t t = 230ps
tr,min + ti + tl,min
condition (1)
thold + tclk-Q + tsum
100 + 230 50 + 300 TRUE => No race problem
T tr,max + ti + tl,max -
condition (2)
T tclk-Q + 31 tcarry + tsum - + tsetup
T 50 + 31(250) + 300 230 + 150 => T 8.2 ns