10

A/D AND D/A CONVERTERS

o--

To A

INTRODUCTION

The advantages of processing signals using digital systems have been discussed in Chapter L Because of these
advantages, digital systems are widely used for control, communication computers, instrumentation, etc.
In many such applications of digital systems, the signals it* not available in the digital form.

An along voltage to be processed using digital techniques may be a fixed (d.c.) voltage art, time

varying voltage v (t). The process of converting an analog signal to a digital form
four processes, 'rhese are

Sampling

Holding

Quantizing

Encoding

imohifl

a sequence of

These processes are not performed as separate operations. Sampling and holding openflH are done
simultaneously using a circuit known as sample-and-hold (S/H) circuit. These tions are required to be
performed for the conversion of time varying analog signals andljH d.c signals. Quantizing and encoding
processes are done simultaneously using a circuit refaP to as an analog-to-digital converter (A/D

converter or ADC). The process of conversion of an tfl| signal to digital signal is referred to as an analogto-digital conversion.

The output of the system may be required to be in the analog form and, therefore, the J|P output has to be
converted back to the analog fonn. The process is referred to as a analog conversion and the system used
for this purpose is referred to as a digital-to-anahltM (D/A converter or DAQ. Some of the examples
where A/D and D/A converters are uao^

A/D and D/A Converters 4

1. FA digital system can be used to monitor the ambient temperature of an oven and if it exceeds a
certain limit, it should reduce the fuel input Here, an A/D converter is required to convert the
output of the sensor (which converts temperature to an analog electrical signal) to digital form.
If the temperature exceeds the specified limit, some digital output is produced which is to be
converted to analog form in order to control the device which reduces the fuel input.

2. A digital voltmeter is used to measure an analog voltage and display the voltage in numerical
form. In this, an A/D converter is required to convert the analog voltage into a digital signal.
The required processing consists of determining its v alue. The output, in this case, is not
required to be converted back to the analog form and hence a I)/A converter is not needed.

3. A digital communication system is used to transmit messages which are in the form of analog
electrical signals. This requires an A/D converter at the transmitting end and a D/A converter at
the receiving end.

In microprocessor based process control systems, A/D and D/A converters are often used and are
referred to as peripherals or I/O devices.

A/D and D/A Converters 5

Since D/A converters are used as sub systems in many A/D converters, D/A converters will be discussed
first.

To 2 DIGITAL-TO-ANALOG CONVERTERS

fin' input to a D/A converter is an Abit binary signal, available in parallel form. Normally, digital signals
are available at
the output of the latches
orregisters
and thevoltages, cone

[ponding to logic 0 and

logic 1, available to diive

precisely

theconverter

are ingeneral

not

v l voltages. Therefore, these voltages are not applied directly to the converter but are used pc rate
digitally controlled switches. The switch is thrown to one of the two positions Spending upon the
digital signal (1 or 0) which connects precisely fixed voltages HI) or HO) the converter input,
corresponding to 1 or 0, respectively.

The analog output voltage V0 of an Abit straight binary D/A converter is related to the I input
by the equation

A/D and D/A Converters 6

F0= K (2N

bN_ i + 2*"

bN_

+ . + 2 2 b2 + 2bl + bj)

(10.1)
V ------,

h is a proportionality factor.
=

1 if tin ;rth bit

of die digital input is 1

I LSB,
o O'----------(,
A/

Digitally
controlled
electronic
switches

~ if the nth bit

erters 369

of the digital input is 0

pie 10.1 Find

output voltage of
converter for all
possible inputs,
^ume K ~ 1.

the analog
a 4-bit D/A

(10.4)
button

H0

T Eq. (10.1),
we obtain the
output voltage
for each input
and these are
Table'straight

given in

binary input, ^0) = 0

~VR, and the output voltage V0 is given by [ = _ ( rr \ Rp 1 Rf 1
W(

and DMConv

^ ( R b" x + 2RbN-i+j2RbN-A+"-+^TJbii

*bch is oi the same forai as Eq. (10.1)

and F(l) =

dtp

Rp '

A/D and D/A Converters 7

vR

(10.5)

output sw ings in only one direction and therefore is unipolar. If it is required to convert
Pdata in bipolar format such as in sign-magnitude, ls complement or 2s complement t then
HO; * (). in such cases, F(0) is used to offset the output swing.
^1) and F(0) as the voltages applied to the resistor network for 1 and 0, respectively, Put
voltage V0 of Fig. 10.1 is given by

VN_,

(10.6)

Li

2n~'1

Vn_2

+...

+21

Vx

+2

V0)

also be produced in the output voltage V0 by using the circuit of Fig. 10.2. The ^ produced in this
circuit is

USB D/A _

"""network

V(0) = 0 V.
and

0000 to 1D1
0 V tor a
digit*
he
digital inputs
MSB
is
compten

Ckcuit tised to offset th

1(b) MiusUhjI
1(

J ^ 1
(cl With the oils.
before a|
lin(putl

Therefore

Using t(

mented
TablelO
Without
,

obtain .he analog

offset rr
Solution

I,put voltage Vo * *^ i
voltage of - D
Table 10.2 [Conti)

/.. = -8V

g analog
ie 10.3converts

trample 10.3 Consider a 4-bit digital input in 1s complement format. Design a D/A con verter for this.

Solution
Since the 1s complement representations of the positive numbers + 0 to + 7 are same as the representations of the unipolar binary numbers, no offset voltage is required for these inputs

for the negative numbers 1111 to 1000, the output analog voltage is to be offset by -15 V This can be achieved by operating a switch with MSB of input to introduce proper aijeof K*.
An alternative circuit is given in Prob. 10.2.

The weighted resistor D/A converter has the problem of having a wide range of resistor vakjes (R t o 2N' 1 R ) with required precision and which track over a wide temperature *n9- " lS difficult to
fabricate such a wide range of resistance values in a monolithic 1C. fctf#culty is eliminated by R - 2 R ladder D/A converter discussed below.

A/D and D/A

Conv,erters 373

10.2.2 R-2R Ladder D/A Converter

Ail R -2R ladder D/A converter is shown in Fig. 10.3. It uses resistors of only two values, R and 2R. Ihe inputs
R
to the resistor network are applied through
2 controlled switches. A switch is in position 0 or 1
2 R digitally
corresponding to the digital input for that bit position
R being 0 or 1, respectively. To analyse this circuit, for
:2 R
2 R R-2R
2
simplicity we consider a 3-bit
ladder D/A network shown in
Fig.
2R 10.4. In this circuit, we have
2R
assumed the digital input as 001.
V
T VR

\MV-

TTTTT

The circuit is simplified using Thevenins theorem. Applying Thevenins theorem at AX*' obtain fy-10.5
^aplifi
the
Similarly, applying Thevenins theorem at YY and * obtain the circuits of Fig.
Fig.circuit
10.4 of Fig. 10.5a.
________________________________________________________
3-bit
D/A network.
c
10
.5bR-2R
and c,ladder
respectively.
Here, LSB has been assumed as * equivalent voltage obtained is VR/2*.
iU,,

n (10.7) shows that the analog output voltagj for an A-bit

D/A converln^^bfMrt^^^H

Similarly, for the digital input of 010 and 100, the equivalent voltages are VR' *
"Jitage
is proportional
to case
theofdigital
J the
otors
required
an A-bit
D/Acan
converter
is 2A in
R-2R
converter,
thefor
output
voltage
be similarly
-
respectively. The value of the equivalent resistance is 3 R in each case. Therefore, equivalent
is nnt * U"!t'^M^convener,
spread in the resistance
for A
large
A, case
the weighted-re
whereas values
it is only
in the
of a weighted-resistor D/A converter.
r
, rrcigmea-iesistor
D/A resistor network of Fig.
I suitable. However, the weighted-resistor
circuit of Fig. 10.4 which is given in Fig. 10.5</. For the circuit of DfF output analog voltage
r of
10.2 can
N
milarly
detemined
and be
fc modified
A
resistors
(10 .8 )
anlo ~l
} L + 2 y.2
n*
1
d Vp=
V() is given by
N-2^ + 2 A; + 2 b\ + 2
)
by

12

Modem Digital Electronics

ccommodate a large number of bits without consequent spread in resistor

values. One such circuit is shown in Fig. 10.6. Here, the bits are divided
into groups of four. The most-significant four bits are applied in a manner
similar to the one used in weighted-resistor D/A converter. The leastsignificant four bits are applied through an additional resistor r, in addition
to weighted resistors. This is done to produce input currents of OP AMP due
to least-significant group of 4

A/D and D/A Converters

13

Modem Digital Electronics

A/D and D/A Converters
(b\ b\)

and the most-significant group of 4-bits in the ratio of 1: 16 [ ^

= - = - = 1/1 g

VWV 2 R

vws.
vYYY
8R m

(10.10)

fig-10.7
ZR

' portion
--- -me currents due to b2, b{, and b0 will be l/16th of the
of modified weighted-resistor D/A converter.
r=8 R

resistor r is determined in the following way:

-VWY

10.6
- .c 10 e, b5, and respectively (Problem 10.3).

given

dified weighted-resistor D/A converter.

Wife this value of r, it can be verified that the
Wfnts due to b,. hr *

Let the bA bit be 1 and b2, and b() bits be all 0. The portion of the circuit correspond^ this is shown
in Fig. 10.7a and its simplified version is shown in Fig. 10.7b.
(r + 8/7 R)
1

7 R)

R+

VR

32RRpb^mR,bl + 128
R

This current must be 1/16th of the current due to by, which is VK/R- Ihereioie.

A
)

(10.11)
output analog voltage V0 of the modified D/A converter of Fig. 10.6 for r = 87? is (if Rh b}+jR R? A* + 1TE

The
From Fig. 10.7b, we obtain Iin assuming virtual short at the input of the OP AMP.

A,

_JL R / VR

F k + SR

14

Modem Digital Electronics

A/D and D/A Converters

om Eq. (10.11) that the analog output voltage is proportional to the digital input.

0 r s st

^ ' rs in this circuit is less and also tire spread in the resistor values is configuration can be used for
any number of bits

376 Modem Digital Electronics -------------------------------------------------------------Example 10.4 Design a 2-decade BCD D/A converter.

Solution
The circuit of Fig. 10.6 can be used for BCD D/A converter. The binary inputs corresponding to the leastsignificant digit are applied at ^, b 2, b ,, and b 0 and those corresponding to the next digit, at b y, b6, b 5 ,
and b A . The value of r is chosen so as to make the input current of OP AMP corresponding to LSD as
1/1 Oth of that of current due to MSD, and is given by

( B )
or

r - 4.8 R

(10.12)

10.2.3 Specifications for D/A Converters

The characteristics of a D/A converter, which are generally specified by the manufacturers are

1.

Resolution,

2. Linearity,

3. Accuracy,

4. Settling time, and

5. Temperature sensitivity.
These are discussed below:
Resolution
This is tlie smallest possible change in output voltage as a fraction or percentage of the full sale output range. For example, for an 8-bit
converter, there are 28 or 256 possible values of analog output voltage, hence the smallest change in the output voltage is l/255th of the
full scale output range. Its resolution is described as one part in 255, or 0.4 per cent. Alternatively, the number of bits accepted at the
input can itself be used as the resolution. For example, an H-bft D/A converter has an 8-bit resolution.
Linearity
In a D/A converter, equal increments in the numerical significance of the digital input shod result in equal increments in the analog output
voltage. In an actual circuit, the input y>ut^ relationship is not linear. This is due to the error in resistor values and voltage across M
switches. The linearity of a converter is a measure of the precision with which the linear upt output relationship is satisfied.

n that

The output voltages of a 3-bit unipolar D/A converter are shown in Fig. 10.8. The ho^H axis represents the input bit combinations with
fixed-interval separations in order of nuaw* significance and the vertical axis represents the analog output voltage. The output voltage^
each input is indicated by a dot. If the converter were ideal, the dots would fall on the* line, as shown in Fig. 10.8
.

i<f1

1Output vs input of a D/A converter.

The linearity error for a digital input is the difference between the voltage corresponding to the dot and die voltage obtained from the
straight line (expected output). T his is indicated by The normal analog output voltage change corresponding to a digital input change
equivalent to least-significant bit is indicated by A.
2 he linearity of a D/A converter is generally specified by comparing with A. For example, he linearity of a commercial D/A
converter unit is specified as less than LSB. This 1
kcuttcy
The accuracy of a D/A converter is a measure of the difference between the actual output kagf and the expected output voltage. It is
specified as a percentage of full-scale or maxi- -.an output voltage. For example, if a D/A converter has 10 V full-scale (maximum)
output fege and an accuracy of 0.2%, then the maximum error for any output voltage will be >U x 10 = 20 mV.
Itttling Time
Ifa die digital input to a D/A converter changes, the analog output voltage does not change B^HBecause of the presence of switches,
active devices, stray capacitance, and inductance t with the passive circuit components, the transients appear in the output voltage and
may also occur. Typically, a plot of a change in tire output voltage might be as
Fig. 10.9. The time required for the analog output to setde to within ^ LSB of the

Fig. 10.

tar a change in the digital input is usually specified by the manufacturers and is l settling time.
This imposes a limit on the frequency at which the digital input can

378 Modem Digital Electronics

of DAC 80.
Final value

Converters

le pins of the voltage and current

Initial
value

+ Vs (+15 V)
/ 12-BIT I
with two functions haveResistor
the
first it model.
ladder

Fig. 10.9

tal Input Codes

Settling time of a D/A converter.

network an,
current
switches

accepts complementary digital i

Common
Summing junction/scaling network 20

V Range /scaling network

0 V Range/scaling network
ipolar offset

change. If it is operated at too high a frequency, it may not have time to setde to the correct output voltage
before being switched on to the next digital input
12 bits (binary) or 3 digits
Temperature Sensitivity
(BCD)
The analog output voltage for any fixed digital input
varies
temperature.
ThisV,is due
theV,
temperature
12-bit
CBI with
or 3-digit
CCD 2.5
5 V,to
10
0
sensitivities of the reference voltage source, resistors,
to +OP
5 V,AMP,
0 to etc. It is specified as ppm/C.
The CBI code may be any one
'"'tonal block
+ 10 V (CBI), or 0 to + 10 V (CCD)
0.12%
(max)
5 nrA (min)
10.3 AN EXAMPLE OF D/A CONVERTER 1C
Resolution
The AD DAC 80 is a 12-bit D/A converter, available in 24-pin DIP. It consists of matchei bipolar switches,
a precision
resistor
network,
a low-drift, high-stability voltage reference an optional output
Output
current
Output
LinearityThe
erroroptions
Maximum gain drift
amplifier.
impedance
(dc) available are 12-bit complementary binary (CBI) three-digit BCD
Power
dissipation
(complementary-coded
decimal,Maximum
CCD) input codes, as well as current or age output modes. Its
converston time (Settling time to
important performance characteristics are:
LI
0.05
30 ppm/C
925 mW (max)
0.01% of full scale range)

have the same ' ,tage

The
model on.
an
second,
nentary offset binary (COB), or (

i in Table 10.4. The 12-hit A-~

1/

Analog output current ranges

Output impedance

1 nrA, 0 output)
t 2 in A1(CHI)
ps (voltage
//s or "to-2*^ 3.2 kD
Digital input format Analog output
(bipolar)
or (>.<> Id2 (unipolar)
voltage
(current
output)
The functional
blockranges
diagram of DAC 80 is shown in Fig.
10.10.

converter

Ful Scale

2
l
scale

Fu sca
ll le

Cain Adjustment
Modem *******
analog output votutge .( )- Tble 10'5 P He

10.3.2 Analog OutputRR

\pply the digital input that would give the maximum positive voltage output. Adjust the gain potentiometer for
this positive hill scale voltage.

voltage is available in different full-scale ranges

nutDut ranges.
Connect pin
Digital input
15 to pin
Output
code
19
range, 1
s
~
10V +COB or COB
or COB
18
5
V

2.5
nections to be made for various output ranges.
or
arc
18
V 0 to Oto
arc
18
+10
18
V +5
19

The

10.3.3

V
+10
Calibration
V

in Fig-

CCD

Connect pin
19 to pin
15

17 t o p t n
20
20
20
21
21

The gain and offset adjustments for unipolar and bipolar D/A converters are illustrated in
Gain adj. rotates
the line
Range of offset
adj.

used for calibration.

20

+Vs
100 MU i 10 kl to Qaln ad).Fig.
' 10.12.
NC
100 ki

MS

B7-

All bits = 0

All bits = 1
Offset adj. translates the
line

-Vs

0.01 fiF 1

04-

Range
of
gain adj.

NC

REF

BC

1 LSB

NC

10.11 are
tiometers
shown voltage range 24
Table
10.5 Output
connections

offset and gain Poten

+
Full
scale

10 kft to offset 100

kft
1 LSB

12-BIT
Resistor

ladder
network
and
current
switches

5kSi;

Control
circuit

Connect-rpin

*-

+ Full scale

+Vs

1
vrF

20
15

Gain adj. rotates

the line

16

O for CCD mode's

A for CBI models

All bits = 1

HAII bits = 0

-55H

B10

Bn

:1

1 (tF

B i z'

Range of

adj.

offset
- Full scale

Offset Adjustment

Offset adj. translates

the line

(b)

For unipolar configurations, apply the digital input code that should potential and adjust the offset
atoandoffseiadiustments.
potentiometer for zero output. For bipolar c o the digital input code that would
vodceproduce the
maximum negative output vo age,
ad

offset potentiometer for maximum negative output voltage.

Range
of
gain adj.

iustments for (a) Unipolar, (b) Bipolar, D/A converter.

10.4 SAMPLE-AND-HOLD

me-varying analog signal can have any value in a given range. For example, v(t) Fsin shown in Fig. 10.13 will have different value of voltage between the range + V and -Fat different instants of time.

10.13

me varying analog signal v(t) = V sin at

If this signal is to be converted into digital form, we may think that the value of the signal i every instant of time is required to be converted into a group of n number of bits. This proem will yield an
infinite number of analog voltage values and thus is not at all practicable. On ti* other hand, if we take the samples of v(t) at regular intervals, that is the signal is sampled regularly every Zj, then according
to the sampling theorem, the signal can be uniqueh dew mined and reconstructed from these samples with no error. The time Ts is called the sampiiiy

and fs = j is sampling rate.

According to the sampling theorem,

f>2f

1011

re /is the frequency of the analog signal. From Eq.(10.13), we conclude that the samplf rate be rapid enough for atleast two samples to be taken during the course of the time peridUj the analog signal.

The constant voltage corresponding to each sample is obtained using a sample amttt" (S/H) circuit. The output of the S/H circuit is converted to digital signal by means ofanifldl to-digital (A/D) converter
circuit.

10.4.1 Sample-and-Hold Circuit

basic sample-aitd-hold circuit is

during the time switch S is closed.
opened. Thus for every T s, the

________________ 1-4

Fig. 10.14

Basic sample-and-holddrt

shown in Fig. 10.14. In this circuit the voltage across the capacitor follows the input signal voltage ,
The capacitor holds the instantaneous value of the signal voltage attained just before the switch is
switch is closed for a short duration and then opened.

d.c voltage across the capacitor gives the value of the

signal at the instant the switch is opened. This d.c voltage represents a sample of the signal and is converted to digital signal using A/D converter circuit during the hold period.

Figure 10.15 shows a practical S/H circuit. An enhancement mode MOSFET is used as a switch which is controlled by a control voltage Vs.

An OP AMP is used to avoid discharge of capacitor due to the loading effect of A/D I inner. During the positive values of Vs (higher than the threshold voltage), the MOSFET I relucts, i nput voltage
appears across C and at the output. When Vs is less than the threshold I itage, the MOSFET is cut-off (.S' open) and the voltage across C is retained because the i nput I nance of the OPAMP is very high.

Hie accuracy of the circuit depends upon the holding of the charge in the capacitor, there- I .a capacitor with a very low leakage must be used. A capacitor with polycarbonate, poly .dene, or Teflon
dielectric is prefered. Most of the other capacitors do not retain the stored I arge for a sufficiently long duration due to polarization phenomenon.
loY ANAY6G-TO- DIGITAL cdNVERTERS
VI Quantization and Encoding

digjtal-to-analog converter, the possible number of digital inputs is fixed. For example, in a ,J- D/A conv erter, there are 8 possible inputs. In contrast, in an analog-to digital converter, ^ put analog
voltage can have any value in a range, but the digital output can have only 2 A values for an A-bit A/D converter. Therefore, the whole range of analog voltage is ted to be represented suitably in 2N intervals.
This process is known as quantization. Each is then assigned a unique A-bit binary code, which is referred to as encoding.

I A/JPW an analog voltage in the range of 0 to Vand a 3-bit digital output for any voltage in tinge. Let us divide the whole range of analog voltage in 8 intervals (3-bit output) of the I Midi
assigned a 3 bit binary value. The intervals of the analog voltage

^^gMponding digital values assigned are shown in Fig. 10. Hi. From this, we observe pie range of voltage in an interval is represented by only one digital value. There
quantization error, involved in t hi s proc ess of quantization.

is

interval

an error rein

red

is

to ns