LOW-POWER DIGITAL VLSI DESIGN

CIRCUITS AND SYSTEMS

LOW-POWER DIGITAL VLSI DESIGN

CIRCUITS AND SYSTEMS

by

Abdellatif Bellaouar
University of Waterloo
and

Mohamed I. Elmasry
University of Waterloo

1IiI...

"

SPRINGER SCIENCE+BUSINESS MEDIA, LLC

ISBN 978-1-4613-5999-9

ISBN 978-1-4615-2355-0 (eBook)

DOI 10.1007/978-1-4615-2355-0

Consulting Editor: Jonathan Allen, Massachusetts Institute of Technology

Library of Congress Cataloging-in-Publication Data

A c.I.P. Catalogue record for this book is available

from the Library of Congress.

Copyright

1995 Springer Science+Business Media New York

Originally published by Kluwer Academic Publishers in 1995

Softcover reprint ofthe hardcover lst edition 1995

AlI rights reserved. No part of this publication may be reproduced, stored in

a retrieval system or transmitted in any form or by any means, mechanical,
photo-copying, recording, or otherwise, without the prior written permission of
the publisher, Springer Scie:noe+Business Media. LLC.

Printed on acid-free paper.

CONTENTS

PREFACE
1 LOW-POWER VLSI DESIGN: AN OVERVIEW
1.1
1.2
1.3

1.4

Why Low-Power?
Low-Power Applications
Low-Power Design Methodology
1.3.1 Power Reduction Through Process Technology
1.3.2 Power Reduction Through Circuit/Logic design
1.3.3 Power Reduction Through Architectural Design
1.3.4 Power Reduction Through Algorithm Selection
1.3.5 Power Reduction in System Integration
This Book
1.4.1 Low-Voltage Process Technology
1.4.2 Low-Voltage Device Modeling
1.4.3 Low-Voltage Low-Power VLSI CMOS Circuit Design
1.4.4 Low-Voltage VLSI BiCMOS Circuit Design
1.4.5 Low-Power CMOS Random Access Memory Circuits
1.4.6 VLSI CMOS SubSystem Design
1.4.7 Low-Power VLSI Design Methodology

1
1

3
4
4

6
7
7
7
7
8
8
9
9
10
10
10

REFERENCES

11

2 LOW-VOLTAGE PROCESS TECHNOLOGY

13

2.1

CMOS Process Technology

2.1.1 N-well CMOS Process
2.1.2 Twin-Tub CMOS Process
2.1.3 Low-Voltage CMOS Technology

13
14
16
17

LOW-POWER DIGITAL VLSI DESIGN

VI

2.2
2.3

2.4
2.5

2.6
2.7
2.8
2.9

Bipolar Process Technology

Isolation in CMOS and Bipolar Technologies
2.3.1 CMOS Device Isolation Techniques
2.3.2 Bipolar Device Isolation Techniques
CMOS and Bipolar Processes Convergence
BiCMOS Technology
2.5.1 Example 1: Low-Cost BiCMOS Process
2.5.2 Example 2: Medium-Performance BiCMOS Process
2.5.3 Example 3: High-Performance BiCMOS Process
Complementary BiCMOS Technology
BiCMOS Design Rules
Silicon On Insulator
Chapter Summary

REFERENCES
3 LOW-VOLTAGE DEVICE MODELING
3.1
3.2

3.3

3.4
3.5

MOSFET Structure and Operation

SPICE Models of the MOS Transistor
3.2.1 The Simple MOS DC Model
3.2.2 Semi-Empirical Short-Channel Model (LEVEL 3)
3.2.3 BSIM Model (LEVEL 4)
3.2.4 MOS Capacitances
CMOS Low-Voltage Analytical Model
3.3.1 Threshold Voltage Definitions
3.3.2 Subthreshold Current
3.3.3 Low-Voltage Drain Current
CMOS Power Supply Voltage Scaling
Modeling of the Bipolar Transistor
3.5.1 BJT Structure and Operation
3.5.2 Ebers-Moll Model
3.5.3 Bipolar Models in SPICE
3.5.4 Chapter Summary

REFERENCES

21
27
27
31
34
36
37
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40
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44
52
56
57
63
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89
91
91
94
101
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111

Contents

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4 LOW-VOLTAGE LOW-POWER VLSI CMOS

CIRCUIT DESIGN
4.1

CMOS Inverter: DC Characteristics

Transfer Characteristics
Effect of /3
Noise Margins
Minimum Power Supply
Example of Noise Margins
CMOS Inverter: Switching Characteristics
4.2.1 Analytic Delay Models
4.2.2 Delay Characterization with SPICE
Power Dissipation
4.3.1 Static Power
4.3.2 Dynamic Power of the Output Load
4.3.3 Short-Circuit Power Dissipation
4.3.4 Other Power Issues
Capacitance Estimation
4.4.1 Estimation of Gin
4.4.2 Parasitic Capacitances
4.4.3 Wiring Capacitance
4.4.4 Example
CMOS static Logic Design
4.5.1 NAND/NOR Gates
4.5.2 Complex CMOS Logic Gates
4.5.3 Switching Activity Concept
4.5.4 Switching Activity of Static CMOS Gates
4.5.5 Glitching Power
4.5.6 Basic Physical Design
4.5.7 Physical Design Methodologies
4.5.8 Conventional CMOS Pass-Transistor Logic
4.5.9 CMOS Static Latch
CMOS Logic Styles
4.6.1 Pseudo-NMOS CMOS Logic
4.6.2 Dynamic CMOS Logic
4.6.3 Design Style Comparison
4.6.4 Clock Skew in Dynamic Logic

4.1.1
4.1.2
4.1.3
4.1.4
4.1.5
4.2

4.3

4.4

4.5

4.6

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127
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LOW-POWER DIGITAL VLSI DESIGN

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4.7

Clocking
4.7.1 Storage Elements
4.7.2 Single-Phase Clocking
4.7.3 Two-Phase Clocking
4.8 Pass-Transistor Logic Families
4.8.1 CPL
4.8.2 DPL
4.8.3 Modified CPL
4.8.4 Pass-Transistor Logics Comparison
4.9 I/O Circuits
4.9.1 Input Circuits
4.9.2 Schmitt Trigger
4.9.3 CMOS Buffer Sizing
4.9.4 Clock Drivers and Clock Distribution
4.9.5 Output Circuits
4.9.6 Ground Bounce
4.9.7 Low-Swing Output Circuit
4.10 Low-Power Circuit Techniques
4.10.1 Low Static Power Techniques
4.10.2 Low Dynamic Power Techniques
4.11 Adiabatic Computing
4.12 Chapter Summary

REFERENCES

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210
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214
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236
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239
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247
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251

5 LOW-VOLTAGE VLSIBICMOS CIRCUIT

DESIGN
5.1

5.2

Conventional BiCMOS Logic

5.1.1 DC Characteristics
5.1.2 Transient Switching Characteristics
5.1.3 CMOS and BiCMOS Comparison
5.1.4 Power Dissipation
5.1.5 Full-Swing with Shunting Devices
5.1.6 Power Supply Voltage Scaling
BiNMOS Logic Family
5.2.1 BiNMOS Gate Design

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274

Contents

5.3

5.4

5.5

IX

5.2.2 CMOS and BiNMOS Comparison

5.2.3 BiNMOS Logic Gates
5.2.4 Power Supply Voltage Scaling
Low-Voltage BiCMOS families
5.3.1 Merged and Quasi-Complementary BiCMOS Logic
5.3.2 Emitter Follower Complementary BiCMOS Circuits
5.3.3 Full-Swing Common-Emitter Complementary BiCMOS
Circuits
5.3.4 Bootstrapped BiCMOS
5.3.5 Comparison of BiCMOS Logic Circuits
5.3.6 Conclusion
Low-Voltage BiCMOS Applications
5.4.1 Microprocessors and Logic Circuits
5.4.2 Random Access Memories (RAMs)
5.4.3 Digital Signal Processors
5.4.4 Gate Arrays
5.4.5 Application Specific ICs (ASICs)
Chapter Summary

REFERENCES

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298
299
299
300
303
304
306
307
309

6 LOW-POWER CMOS RANDOM ACCESS

MEMORY CIRCUITS
6.1

6.2

Static RAM (SRAM)

6.1.1 Basics of SRAMs
6.1.2 Static RAM Cells
6.1.3 Read/Write Operation
6.1.4 Low-Power Techniques
6.1.5 Address Transition Detector (ATD) Circuit
6.1.6 Decoders
6.1.7 Bit-line Conditioning Circuitry
6.1.8 Sense Amplifier
6.1.9 Output Latch
6.1.10 Hierarchical Word-Line for Low-Power Memory
6.1.11 Low-Voltage SRAM Operation and Circuitry
Dynamic RAM

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356

LOW-POWER DIGITAL VLSI DESIGN

6.3

6.4

6.2.1 Basics of a DRAM

6.2.2 DRAM Memory Cell
6.2.3 Read/Write Circuitry
6.2.4 Low-Power Techniques
6.2.5 Decoder
6.2.6 Sense Amplifier
6.2.7 Bit-Line Capacitance Reduction
6.2.8 Multi-Divided Word-Line
6.2.9 Half-voltage Generator
6.2.10 Back-Bias Generator
6.2.11 Boosted Voltage Generator
6.2.12 Self-Refresh Technique
6.2.13 Low-Voltage DRAM Operation and Circuitry
On-Chip Voltage Down Converter
6.3.1 Driver Design Issues
6.3.2 Reference Voltage Generator
Chapter Summary

358
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363
364
366
367
367
367
371
373
377
377
381
389
394
395
399

REFERENCES

403

7 VLSI CMOS SUBSYSTEM DESIGN

409
409
410
412
420
423
425
428
429
432
434
442
450
450
451
454

7.1

7.2

7.3

Parallel Adders
7.1.1 Ripple Carry Adders
7.1.2 Carry Look-Ahead Adders
7.1.3 Carry-Select Adder
7.1.4 Conditional Sum Adders
7.1.5 Adder's Architectures Comparison
Parallel Multipliers
7.2.1 Braun Multiplier
7.2.2 Baugh-Wooley Multiplier
7.2.3 The Modified Booth Multiplier
7.2.4 Wallace Tree
7.2.5 Multiplier's Comparison
Data Path
7.3.1 Arithmetic Logic Unit
7.3.2 Absolute Value Calculator

Contents

Xl

7.3.3 Comparator
7.3.4 Shifter
7.3.5 Register File
7.4

7.5

7.6

Regular Structures
7.4.1 Programmable Logic Array
7.4.2 Read Only Memory
7.4.3 Content Addressable Memory
Phase Locked Loops
7.5.1 Charge-Pumped PLL
7.5.2 PLL Circuit Design
7.5.3 Low-Power Design
Chapter Summary

REFERENCES
8

LOW-POWER VLSI DESIGN

METHODOLOGY
8.1

8.2

8.3

8.4

8.5

LP Physical Design
8.1.1 Floorplanning
8.1.2 Placement and Routing
LP Gate-Level Design
8.2.1 Logic Minimization and Technology Mapping
8.2.2 Spurious Transitions Reduction
8.2.3 Precomputation-Based Power Reduction
LP Architecture-Level Design
8.3.1 Parallelism
8.3.2 Pipelining
8.3.3 Distributed Processing
8.3.4 Power Management
Algorithmic-Level Power Reduction
8.4.1 Switched Capacitance Reduction
8.4.2 Switching Activity Reduction
Power Estimation Techniques
8.5.1 Circuit-Level Tools
8.5.2 Gate-Level Techniques
8.5.3 Architecture-Level Power Estimation

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LOW-POWER DIGITAL VLSI DESIGN

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8.6

8.5.4 Behavioral-Level Power Estimation

Chapter Summary

522
522

REFERENCES

523

INDEX

527

PREFACE

A major creative challenge facing today circuit and system VLSI designers is to
design new generation products which consume minimum power. Power saving
must be achieved without compromising high performance or minimum area.
This has created a new design culture within the design community which we
have just seen its preliminary results. The essence of this culture must be
accessible to the new generation of designers.
The concern of power dissipation has been part of the design process since the
early 1970s, but was less visible. High speed operation, and designing with
minimum area, specially in memories, were the main design constraints. The
state-of-the-art was driven towards lower delays and smaller chip area. Design
tools were all geared towards achieving these two goals. Major milestones on
chip integration and clock rates have been reported in technical conferences
(e.g., IEEE International Solid-State Circuits Conference) and journals (e.g.,
IEEE Journal of Solid-State Circuits) from the late fifties till the early nineties.
Power dissipation has taken a back seat as a figure of merit. However, as
we approach the end of this century, power dissipation has become the main
design concern in many applications. Two contributing factors were the area
of portable electronics and the area of high-performance chips exceeding power
dissipation limits.
This book addresses the design of low-power VLSI digital circuit and system
design. The book starts with an introduction to the topic of low-power design.
Followed with two supporting chapters on low-power process technology and
device modeling. Circuit design for low-power is addressed in two chapters;
one on CMOS and the other on BiCMOS. Low-power design applications are
covered in subsequent chapters; one on low-power RAMs and the other on lowpower subsystem designs. The subsystems include adders, multipliers, data
path, regular structures and phase locked loops. The last chapter deals with
overall low-power VLSI design methodology. The book addresses many design
issues related to low-power; the concept of switching activity, the use of passtransistor logic, designing using multi-and-Iow threshold voltage CMOS logic,
the integration of on-chip voltage down converters, etc.

XlV

LOW-POWER DIGITAL VLSI DESIGN

We hope that students and instructors find this book useful in their class-room
instruction and also hope that it will be valuable to researchers working in this
area.
Abdellatif Bellaouar
Mohamed I. Elmasry
Waterloo, Ontario
Canada

Preface

xv

Acknowledgements
Firstly we would like to acknowledge the countless blessings of God Almighty
throughout our lives. During the course of writing this book we have developed a greater appreciation for God's created biological processing circuits and
systems in terms of low-power and low-energy design. Such systems provides a
great aspiration to VLSI designers. The brain, with 30 Watts of active power
and processing information at less than 0.01 pJ, is an excellent example of
low-power processing/memory design. More research is needed to abstract
low-power concepts from the brain and apply them to VLSI circuits and systems.
We would also like to thank our families whose support and endurance helped
us to complete writing this book. A. Bellaouar, would like to acknowledge his
wife. She was very patient and helpful when he spent over 16 hours/day to
complete this manuscript.
We also extend our thanks to Mr. Carl Harris from Kluwer Academic Publishers
for encouraging us to work on this new era of VLSI design.
We would like to thank our colleagues at the VLSI Research Group of the Department of Electrical and Computer Engineering at the University of Waterloo
for their encouragement and support, in particular, Issam S. Abu-Khater. We
are grateful to Joan Pache for carefully proof reading the book.
We appreciate the financial support to our research provided in part by NSERC,
MICRONET, ITRC, CMC, BNR and NTE.
Finally, we appreciate the effort of those who assisted us in preparing the
manuscript and the figures, in particular, Kamel Benaissa, Muhammed Elrabaa,
Ahmed R. Fridi and Phil Regier. Also, we thank Dave Bartholomew from
Graphic Services at the University of Waterloo for helping in the design of the
book front cover.

To
My parents, my wife G hania and my son
Mouaadh Bellaouar
Elizabeth, Carmen, Samir, Nadia and Hassan
Elmasry