The goal of this project is to design and layout a test chip with various Physical

Unclonable Functions (PUFs) using IBM 0.18um CMOS process. The design
should be optimized for robustness, reliability, and area. The project will consist
of two phases. In the first phase, the schematic of the project will be designed
and the functionality must be verified using SPICE simulations.
The students will form groups of up to three students per group for this project.
Make sure that the work is divided equally between the members of each group. I
highly recommend that each group has no more than one undergraduate student.
In the second phase, the layout of the test chip will be completed and the
extracted netlists will be verified with original spice file using LVS. In addition, the
extracted netlist need to be simulated and compared with that from the original
spice file from schematic.

Design Requirements:
1. Physical unclonable functions (PUFs) are an innovative primitive that are used
for authentication and secret key storage without the need for secure EEPROMs
and other expensive hardware. A PUF is based on the idea that even though the
mask and manufacturing process is the same among different ICs, each IC is
actually slightly different due to normal manufacturing variability. PUFs leverage
this variability to derive secret information that is unique to the chip (a silicon
biometric). In addition, due to the manufacturing variability that defines the
secret, one cannot manufacture two identical chips, even with full knowledge of
the chips design [1]. The conceptual diagram of PUF is shown below. There are
many diffrent methods of implementing PUFs, including: ring oscillator,
arbitrator, and SRAM based circuitries. The goal of this project is to design the
layout of a PUF circuit, ready to be taped out for manufacturing.

In your design consider the robustness, area, testability, and functionality from
the beginning of the design. We will submit one design to MOSIS for
manufacturing. The group is chosen for fabrication (the best functionality and
robustness) will obtain 10% bonus credit for the project.
2. In order to be able to compare and evaluate different PUF circuits, you are
required to design at least three types of PUF circuits in your design. The PUF
circuits should have minimum overhead on the design. Therefore, you are also
required to use as minimum number of pads as possible for each PUF circuit. In
addition, try to minimize the area of your PUF design. Keep the center area of the
chip empty (for an imaginary ASIC) and only use the periphery of the core for
your PUF design. Make sure that your design have enough number of bits to
resolve the variations needed for PUF. For example, if you are using ring
oscillator PUF, make sure that you have enough bits for teh counter to be able to
resolve the variations.
3. Design and test each block individually. Combine the blocks, once you confirm
the simulation results for each block.
4. Use wide metal layers for the VDD and GND lines.
5. For your layout design using L-Edit, and SPICE simulations, please download
the SPICE model, L-Edit setup file, and Extraction setup file for IBM 0.18um CMOS
process. Using S-Edit is not required for this project, but a schematic must be
presented in your reports.
6. The L-Edit setup file contains all the DRC rules needed for IBM 0.18um CMOS
process. To simplify the layout for this project, we will be using the
scalable SCMOS rule from MOSIS. The rules are shown in column DEEP. Also,
Lambda is set to be 0.09um in the L-Edit setup file. Although the IBM process has
up to 6 metal layers, use only Metal 1 and Metal 2 to layout your design.

6. In addition, the L-Edit setup file contains a pad frame cell that you will be using
in this project. Please try to design your final layout inside the pad frame (in the
chip cell) and make the connections to appropriate pads. The pad frame that has
been created for you in this file consists of 26 I/O, and one GND, and one VDD
pads. The VDD pad is located to the right and GND pad is located to the left of the
frame. The I/O pad terminals are on Metal 2, but the VDD and GND pad terminals
are in Metal 1. The I/O pads are all the same, with only ESD protection devices.
You can simply use it as an input, but if you want to use it as an output, you need
to design appropriate driver for it. Consider 20pF load for the regular output pads.
7. Make sure to have a plan for diagnosis. If your chip doesn't work, how can you
debug and identify the problem?
8. The goal of the project is to be able to evaluate various PUF circuits. Therefore,
you should aim for designing PUF circuits with minimal area and pad count
overhead.
9. Follow the naming convention and input output characteristics as below. When
performing simulations for the PUF circuit in the project, make sure that you
consider a 20pF load capacitor on each output pin.

Item

Pins

Descriptions

Input

Challenge pins

Input capacitance should not cause more than 50fF load to its previous stage.

Output

Response pins

Output ports should have loads of 20pF when performing simulation

Supply voltage VDD and GND

1.8V

Due Dates:
Phase one: schematic and SPICE simulation results due in class on Wednesday
April 15, 2015
Phase two: layout and post-layout simulations due in class on Wednesday April
29, 2015

Deliverables:
A written report that contains, but not limited to, the following items. Only
electronic copies for the project reports are accepted. Please email your report
(doc or pdf) to me(payman@ece.unm.edu) before class on the due date.
1. The schematic and associated SPICE file (circuit netlist).
2. Give some bullet points explaining how you designed each block (for example,
schematic, logic style, sizing, etc).
3. Waveforms from simulations on each block independently. Clearly show all the
data (inputs and outputs) on the waveforms.

4. Waveform that shows the functionality of the PUF circuit. Using SPICE,
measure the delay, rise and fall time of the designed circuits.
(5-12 applies to phase two only)
5. Brief explanation on your circuits (circuit type, optimization and changes since
phase1)
6. Waveforms for the whole block functionality (simulated from extracted layout)
7. Layout (.tdb file for L-Edit users)
8. LVS and DRC reports showing there are no violations
9. Delay, rise and fall times (simulated from extracted layout)
10. A brief description of testing strategy. How would you test your PUF circuit
after it will be manufactured?
11. A table showing the hour spent for each task by each member of the group.
12. E-mail your layout (.tdb) and circuit netlist extracted from layout attached with
your report.

Reference:
I highly recommend that you try new and clever ideas to simplify your design or
minimize the area, power, or delay. However, if you would like to review standard
techniques, you are welcome to use techniques published in IEEE proceedings