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DEVELOPMENT TOOL FOR CONVERTING SPICE TO IBIS 4.1

(SPICE TO IBIS 4.1)
J.Pandikumar1, T.Kalavathi Devi 2
1
II ME (VLSI Design)
2
Lecturer, Department of ECE-PG
Kongu Engineering College, Perundurai, Erode.
palacepandi@yahoo.co.in, kalasakthi2003@yahoo.com
ABSTRACT
Traditionally SPICE models S2IBIS 3.2 have been developed. This
have been used for waveform and timing proposed project is an another
analysis. However this SPICE analysis development tool for converting SPICE
is inaccurate for high speed design to IBIS 4.1 model , which extends the
challenges such as onboard data rates, maximum number of points permitted in
cross talk, signal interference etc. There V-I and V-T tables (1000 Vs 100),
is no Protection of proprietary inclusion of independent validation data
information process parameters, circuit tables, external models that supports
design in SPICE. These limitations are VHDL AMS, Verilog AMS ,SPICE
overcome by the use of IBIS.IBIS models 3F5,which are not available in earlier
provide detailed signal integrity, versions like IBIS 3.2,IBIS2.1,IBIS 1.1.
timing analysis and large number of OVERVIEW OF AN IBIS FILE
simulations. It also used to simulate IBIS stands for I/O Buffer
processing variations due to R, L, C Information Specification. IBIS models
components, voltage, temperature, provide a standardized way of
effects of simultaneous switching output representing the electrical characteristics
noise and cross talk. Generating good of a digital IC’s pins (input, output, and
IBIS models is tedious and requires I/O buffers) behaviorally, i.e., without
significant effort. Correctly converting revealing the underlying circuit’s
transistor level models to IBIS is a structure or process information. The
complicated process. In recent years basic behavioral information in an IBIS
some SPICE to IBIS conversion tools model can be obtained either by direct
such as S2IBIS 1.1, S2IBIS 2.1 and measurement of the component or

transistor level simulation of
component’s buffers. An IBIS file
contains, in a human readable ASCII
format, the data required to model
behaviorally a component’s input, output
and I/O buffers. Specifically, the data in
an IBIS file is used to construct a buffer
model useful for performing signal
integrity (SI) simulations and timing
analysis of printed circuit boards. The
fundamental information needed
perform these simulations is the buffer’s
V-I (voltage versus current) and
switching V-T (output voltage versus
time) characteristics. The
specification does not define
executable simulation model, it is a
standard for the formatting and transfers
of data. IBIS models are component-
centric. That is, an IBIS file allows one
to model an entire component, not just a
particular buffer. Therefore, in addition
to the electrical characteristics of a
component’s buffers, an IBIS
includes the component’s pin-to-buffer
mapping, and the electrical parameters
of the component’s package.
In recent years some versions
of IBIS models such as IBIS 1.1, IBIS
1.2, IBIS 2.1, IBIS 3.2, IBIS 4.0 and
IBIS 4.1 have been developed.
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the SPICE to IBIS conversion tools
for the IBIS model 1.2, .2.1 and 3.2 were
developed .Conversion tool for the
version above 3.2 is not available.
Additional features of IBIS 4.1over IBIS
3.2.
1. Extends the maximum number of
points permitted in V-T tables (1000
Vs 100).
2. Inclusion of independent validation
to data tables.
3. External models that supports VHDL
AMS, Verilog AMS, SPICE 3f5.
STEPS TO CREATING AN IBIS
IBIS MODEL
an There are five basic steps to
creating an IBIS model of a component:
1. Perform the pre-modeling activities.
These include deciding the model’s
complexity, determining the voltage,
temperature and process limits over
which the IC operates and the buffer
model will be characterized, and
file obtaining the component related
(electrical characteristics and pin-
out) and use information about the
component.
2. Obtain the electrical (I-V and
switching response) data for output
or I/O buffers either by direct
measurement or by simulation.
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3. Format the data into an IBIS file.

S2IBIS TOOL
PREMODELING An IBIS model can be generated
either 1) by measurement, which
requires having a well-controlled
EXTRACTING THE DATA environment and measurement devices
or 2) by using the SPICE generated
PUTTING DATA INTO AN IBIS netlist running multiple SPICE
FILE
simulations to get the necessary IV and
VT table data.
CREATING AN IBIS FILE SPICE to IBIS is software
written in C or java language that uses
the SPICE netlist of a buffer and
VALIDATING MODEL
generates its IBIS model. S2IBIS
conforms to IBIS specification. The user
CORRELATING THE DATA sets up an S2IBlS command file that
accepts the required user inputs to
generate the IBIS model of the buffer.
Figure 1 Steps to create IBIS
S2IBIS supports HSpice, PSpice, Spicel,
4. Check the file using IBISCHK4. If
Spice2, Spice3 and Spectre.
the model is generated from
S2IBlS generates the required VI
simulation data, validate the model
curves for the model these are the
by comparing the results from the
pullup, pulldown, power clamp and
original analog (transistor level)
ground clamp curves. The pullup and
model against the results of a
pulldown curves are for output models.
behavioral simulator that uses the
The clamp curves are derived for both
IBIS file as input data.
output and input models. It also
5. When the actual silicon is available
generates the VT curves for all output
(or if the model is from measured
models. These are the rising waveforms
data), compare the IBIS model data
and the falling waveforms. To derive all
to the measured data.
these curves, S2IBIS makes SPICE runs

with different settings and extracts the
relevant information from the SPICE
output.
For each component that needs to be
evaluated, the command file has a
header that provides all the default
values such as the temperature range,
voltage range, all the reference values
and the packaging details. The command
file also provides the pin list that
describes which models connect to
which pins and which pins serve as
inputs or enables for output pins. The
command file also describes each model
specified in the pin list with the
exception of the reserved model names
POWER, GROUND and NC.
Figure 2 S2IBIS TOOL FLOW
Above figure shows a block
diagram of the S2IBIS tool flow. The
parser grabs all the information that has
been passed by the user. The program
then sets up all the file names and the
SPICE files that are run once SPICE is
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invoked. As soon as the SPICE output
files are created, they are examined for
any errors or aborts. If there is no error,
the VI and VT tables are extracted from
their respective files and formatted
according to IBIS specification. The last
step is to print the IBIS model into a file.
EXISTING TOOLS
S2IBIS2 was written in C
programmable language along with
Lex and Yacc (for the purpose of
parsing the command file).As such,
different operating systems needed
different versions of the tool.
Moreover, S2IBIS2 could only
generate IBIS V2.1 or lower generation
models only whereas IBIS itself had
evolved to Version 3.2. As such,
S2IBIS3 was developed. The
programming language used to develop
S2IBIS3 is Java which makes it platform
independent. S2IBIS3 is also backward
compatible to all versions of IBIS. The
next section describes how the VI and
VT tables are obtained using S2IBIS.
EXTRACTING I-V DATA FROM
SIMULATIONS
The first step to extracting the
required I-V tables understands the
buffer’s operation. Analyze the buffer
schematic and determine how to put the

buffer’s output into a logic low, logic
high and (if applicable) high impedance
(3-state) state. The schematic should
include any ESD or protection diodes.
Also, understand the buffer’s power
supply voltage reference (Vcc)
requirements and connections. The
schematic should also indicate if the
power clamp and/or ground clamp diode
structures are tied to voltage rails
(voltage references) different from those
used by the pullup and/or pull down
transistors.
SIMULATION SETUP
A typical I-V table simulation
setup for an output or I/O buffer is
shown in Figure3. For this example, the
buffer being analyzed is a standard 3-
state buffer with a single push-pull
output stage. The buffer uses
electrostatic discharge protection devices
in addition to its parasitic driver diodes.
Figure 3 Standard 3-state buffers (pull
down I-V Table Extraction)
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Clamp curves
Power and ground clamp curves
are derived for input models and the
output models with enable inputs. To
find the power and ground clamp
curves for input models, S2IBIS
attaches a voltage source to the
associated pin and sweeps the voltage
source. The current at each voltage point
is recorded.
The sweep range for ground
clamp curves is (Vgnd - Vcc) to (Vgnd +
Vcc), and Vcc to 2*Vcc for power clamp
curves.
Pullup and Pulldown curves
Pullup and pulldown curves are
derived for output models only. For
pullup and pulldown curves, S2IBIS
attaches an input voltage source and an
output voltage source. The input voltage
is set so the output tries to drive high
(for the pullup curve) or low (for the
pulldown curve). The output voltage is
swept from (Vgnd - Vcc) to 2* Vcc, and
the output current at each output voltage
is recorded.
Ramp rate Curves
Ramp rates are derived for all
output models. To find the ramp rates,
S2IBIS attaches the output pin of the

driver to the appropriate termination
voltage through the resistor Rload, and
provides the appropriate stimulus at the
input.
Rising and Falling waveform
Rising and Falling waveforms
are produced for output models when
they are requested with the [Rising
Waveform] and [Falling waveform]
commands.
CONCLUSION
Generating good models is
difficult and requires significant effort.
Correctly converting transistor level
models to IBIS is a complicated process.
In recent years some SPICE to IBIS
conversion tools such as S2IBIS 1.1,
S2IBIS 2.1 and S2IBIS 3.2 have been
developed. This SPICE to IBIS 4.1
model conversion tool which is under
development includes advantages like
maximum number of points permitted in
V-T tables (1000 Vs 100), inclusion of
independent validation data tables,
external models that supports VHDL
AMS, Verilog AMS ,SPICE 3f5 ,which
are not available in earlier versions like
IBIS 3.2,IBIS2.1,IBIS 1.1.
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REFERENCES
1. Nandakumar G.N , Nirav Patel,
Raghunatha Reddy and Makeshwar
Kothandaraman (2005), ‘Application
of Douglas-Peucker Algorithm to
Generate Compact but Accurate IBIS
Models’, Proceedings of the 18th
International IEEE Conference on
VLSI Design held jointly with 4th
International Conference on
Embedded Systems Design
(VLSID’05).
2. Peivand F. Tchrani, Yuzhe Chen,
Jiayuan Fang (1996), ‘Extraction of
Transient Behavioral Model of
Digital I/O Buffers from IBIS’, 46th
IEEE Electronic Components &
Technology Conference, Orlando, pp
1009-1015.
3. The IBIS Open Forum (2005). ‘IBIS
modeling cookbook for IBIS version
4.0’.
4. Ambrish Varma. Alan Glaser. Steve
Lipa, Michael Steer, Paul Franzon
(2003), ‘The development of a
Macro-modeling tool to develop
IBIS models’, International IEEE
Conference on VLSI Design.