Lab 11

Date: /

Digital Circuits I: CIRD 1131

Lab experiment 11: J-K Flip-Flop Circuits
Objectives
1.
2.
3.
4.

Verify the function table and the operation of a JK flip-flop.

Study the and asynchronous and synchronous operations of the J-K flip flop
Connect a JK FF to perform the D Flip-Flop operation.
Connect a JK FF to perform the T Flip-Flop operation.

Information

Read sections 10.6, 10.7, and 10.8 on J-K flip flops in the textbook
The block diagram of the J-K Latch flip flop is shown below:

Positive Triggered JK

Negative Triggered JK

T Flip-flop

Another versatile and widely used flip-flop is the J-K type. The basic JK FF has two inputs (J
and K) and complementary (Q and Q). When both the J and K inputs are tied HIGH, the JK FF
acts as a T, or toggle, flip-flop. As such it performs as a frequency divider. The JK FF is another
solution to the problem of a set of indeterminate or illegal conditions. The clock input of JK FlipFlops may be positive triggered, negative triggered, or level triggered. .
In this lab, we will experiment with the J-K flip-flop and examine its asynchronous and
synchronous operations. You will also configure the J-K flip-flop as a D flip-flop and toggle flipflop.
Components
1. Logic switches and LEDs
2. 1 K Ohm resistor package
3. 220 Ohm resistors
4. 74SL76 latch IC Chip
5. 7404 NOT IC chip
6. Function generator

Pre Lab Tasks

1.
2.
3.

Draw a truth table for the type of J-K flip flop 7476 chip. Include the operating mode
comments for each line of the truth table.
Explain the advantages of the J-K flip flop over other types of Flip-flops.
Give two differences between the SR flip-flop and the D type of flip-flop.

Lab Tasks
1.
With power off, connect the clock input (function generator) to the chip and also an
LED/resistor between the function generator and the clock input of the chip to
indicate the clock pluses
Asynchronous Operation
Test the asynchronous operation of the J=K flip-flop by indicating the status of Q and Q
for each of the following conditions:
(a) Asynchronous Set = 0, Asynchronous Reset = 1, J=X, K=X, CLK=X
(b) Asynchronous Set = 1, Asynchronous Reset = 0, J=X, K=X, CLK=X
(c) Asynchronous Set = 0, Asynchronous Reset = 0, J=X, K=X, CLK=X
3.
Draw a timing diagram to explain the results of step 5. Show both outs Q and Q
2.

4.

Explain the asynchronous operation in detail.

Synchronous Operation
5.
Test the synchronous operation of the J=K flip-flop by indicating the status of Q and Q for
each of the following conditions with Asynchronous Set = 1, Asynchronous Reset = 1:
(d) Clock pulse present, J =1, K=0
(e) Clock pulse present, J =0, K=0
(f) Clock pulse present, J =0, K=1
(g) Clock pulse present, J =0, K=0
(h) Clock pulse present, J =1, K=1
6.
Draw a timing diagram to explain the results of step 9. Show both outs Q and Q
7.
Explain the synchronous operation in detail.
D Flip-flop Operation with J-K flip
8.
Draw a logic diagram of a D Flip-flop circuit using J-K type of flip-flop. Label it
completely.
9.
Connect and test the circuit of step 8. Initially reset the flip-flop circuit.
10. Draw a timing diagram for the step 8.
11. Explain the operation of the circuit in detail
Toggle type Operation with J-K flip

12.
13.
14.
15.

Draw a logic diagram of a toggle Flip-flop circuit using J-K type of flip-flop. Label it
completely.
Connect and test the circuit of step 12. Initially reset the flip-flop circuit.
Draw a timing diagram for the step 12.
Explain the operation of the circuit in detail

Problems (short answer)

1. Problems from the textbook: Pages (476 477)
(a) Problem 10.27

(b) Problem 10.28 Include waveforms for Q and Q

(c) Problem 10.29 Include waveforms for Q and Q

2. To which transition of the input clock signal will the 74LS76 JK FF respond?
It responds to the negative side of the clock because it is inverted.
3. What will the outputs of a 7476 FF do if both J and K are HIGH when it is clocked?
J and K are synchronous with each down pulse of the clock.
4. What will the output of the 7476 do if the J or K input is changed while the clock is high?

5. How will the 7476 JK FF respond to a LOW on the Set (preset) or Reset (clear) inputs?