Thermal Modelling of a MOSFET in Pspice

Mr Aziz Ahmed, Dr Ian Kennedy, Mr Keith Heppenstall, Philips

Semiconductors Hazel Grove (UK).

Abstract
The trend toward higher power density requires greater attention to heat
transfer for the device to stay within its area of safe operation. Thermal
limitations have always been posing constraints on the reliability of power
semiconductor devices. Manufacturers can provide simulation models that
can imitate the operation of a device in actual circuits. This paper presents a
Pspice model for a MOSFET where there is a link between the electrical and
thermal equivalent models of the device. The proposed model incorporates
the self-heating of the MOSFET that modifies the electrical characteristics of
the device depending on the junction temperature. The proposed model has
been validated by lab measurements.

1. Introduction
Circuit simulators play an important role in the development of modern
electronic systems. Pspice is one of these simulators. When it comes to
power devices it fails to simulate the inherent self-heating effect of the device
where Power dissipation results in a rise in junction temperature. To
overcome this , we developed a model that can adjust temperature
dependent parameters.
D

Interactive
coupling

Figure 1

2. Electrical equivalent Model

The MOSFET chosen is Philips BUK7907-55ATE. This device is a Trench
MOSFET with an integrated polysilicon temperature sensing diode that can
be used to validate the model. The MOSFET is first tested and certain
information like Transfer characteristics, reverse diode characteristics, RDS
(ON), threshold voltage, leakage current, gate charge characteristics etc
obtained. This information is then used to create the electrical equivalent
model in PSPICE.

3. Thermal equivalent model

The thermal model represents the impedance to the heat flow from the
junction of the device to its case. Power is dissipated in the junction of the
device and heat flows through the back of the package. To replicate the
impedance in the path an RC chain is used. This simulates the Zth curve of
the device shown in Fig2. All data sheets contain a Zth curve to enable the
designers to determine the cooling needed for their applications. Table1
shows the equivalence between the thermal and electrical variables that
forms the basis for thermal modeling.

Figure 2

Table 1

Fig 3 shows the thermal equivalent model, the device is divided into seven
different sections between the junction and the case. This represents the
thermal impedance to the heat flow (current). Current equal to the amount of
power dissipated in the device is delivered to the model through an ABM
(explained later) in Pspice. The voltage at node Tj is then the electrical
equivalent of the Junction Temperature of the device.
Rth1
Tj

1.03E-3

Gth
IN+ OUT+
IN- OUTGVALUE

Rth2
t1

8.98E-5
CZth1

Rth3

2.91E-3
2.37E-4
CZth2

Rth4

Rth5

t3

t2

8.98E-3
7.25E-4
CZth3

Rth6

2.74E-4
2.33E-3
CZth4

t4

7.80E-2
7.90E-3
CZth5

Rth7
t6

t5

Tcase

0.173
3.17E-2
CZth6

0.209
0Vdc
0Vac
Vcase

2.62E-1
CZth7

{V(D,S)*-I(VId)}

Tamb

Vamb
25Vdc

Figure 3

4. Level3 model
A dynamic link between the electrical and thermal equivalent models is
established. Following the calculation of junction temperature the thermal
equivalent model can interact with the electrical equivalent model to modulate

its drain current and threshold voltage as a function of junction temperature.

Analogue Behavioral Model (ABM) in Pspice has been used to accomplish
this (Fig 4). ABM allows a flexible description of the electronic components in
terms of transfer function. The expression gives the relation between the input
and output. The expression can be written as a table or a formula. The
expressions in ABMs are specified to allow the definition of the parameter
interdependencies. These provide a link between the thermal and electrical
circuits.

Id(Tj)=Idi(TEMP).[Tj/TEMP]-3/2
Vth=(V(Tj)-{TEMP}*0.0015)
Rd

VId1

Rdgd

VId

Rlsd
0.1

Dgd

3
M2

Rcgd

X3

Rg

2 1

EVALUE

EVTH

IN+ OUT+
IN- OUT-

7nH

V1 = 0
V2 = 10
TD = 5us
TR = 100ns Vgate
TF = 100ns
PW = 50us
PER = 200us

E14
+
-

Cgd

M1
Vg
V

+
G1

OUT+ IN+
OUT- INGVALUE

S
2

Vbatt

Rcgs

Cgs

X2
5nH

Figure 4

5 Device descriptions
As seen in fig5 a seven-pin part is created by joining together both the
thermal and electrical equivalent models (with ABMs attached). On the left
hand side are the three basic pins any MOSFET would have i.e. for the drain,
gate and source connections. On the right hand side we have a floating pin
Tj for monitoring junction temperature, another floating pin Vf to monitor the
forward voltage drop across the tempsense diode and two extra pins Tcase
and Tamb between which the thermal equivalent model for the heat sink can
be attached. In this work a new concept has been introduced which uses the
linear relationship between temperature and forward voltage drop of the
tempsense diode to monitor Vf at a constant current of 1mA through the
temperature sensing diode. This will mirror the rise in junction temperature. A
typical example of both Tj and Vf is shown in fig 6 for a 100s pulse.

Junction Temp

Drain Connection

U?
Gate
Connection

Source
Connection

0
1
2

D
G
S

TJ
TCASE
VF
TAMB

BUK7907-55ATE

4
3
6
5

Case
Temp
Vf diode

Ambient
Temp

Figure 5

Tj Vs Vf
120

0.76
0.74

100
80

0.7

Tj(degC)

Vf(V)

0.72
60

0.68
0.66

40

0.64
20

0.62
0.6
0.0E+00

5.0E-05

Vf

1.0E-04

1.5E-04

Tj

0
2.0E-04
Time(sec)

Figure 6

6. Addition of heat sink and simulation setup

The thermal model for the heat sink used in the test is produced. For the heat
sink used the calculated thermal resistance is further divided into 3 separate
thermal resistances to account for the material between the case of the
device and heat sink and the structure of the heat sink itself (Fig 7). Also seen
in figure 7 is the simulation setup for the model. The gate drive is a pulsed
power supply, whereas the drain source potential is DC power supply. Vamb
is used to set the ambient temperature. R3 is the load resistance.

R3
0.14

U14
0
1
2

D
G
S

TJ
TCASE
VF
TAMB

4
3
6
5

BUK7907-55ATE_NEW

Rhs1

Rhs2

Rhs3

9.332E-02

2.951E-01

2.563E+00

Chs1
4.608E-02

Chs2
1.457E-01

Chs3
0.878

Vbatt

V1 = 0
V2 = 10
TD = 5ns
TR = 100ns Vgate
TF = 100ns
PW = 500us
PER = 4s

13Vdc

Vamb
23Vdc

Figure 7

7. Simulation and Experimental Results

Experiments were carried out on BUK7907-55ATE. The Experimental setup is
identical to the Simulation setup (Fig 7). The rise in junction temperature Tj
using the tempsense diode and the power dissipated in the MOSFET was
recorded. After optimizing the heat sink thermal capacitance values for pulse
duration >1ms and inside the MOSFET thermal capacitance values for <1ms
pulses a close match between the simulations and experimental results
exists.

Dissipated power for 20ms pulse

1200

Power(Watts)

1000
800
600
400
200
0
-0.02

-0.01

Power(meas)

0.01

0.02

Power(sim)

0.03

0.04

Time(sec)

Figure 8a

Tj for 20 ms pulse
35
30
Temp(C)

25
20
15
10
5
0
-0.02

-0.01
Tj(meas)

0.01
Tj(sim)

0.02

0.03

0.04

0.05

Time(sec)

Figure 8b

Fig 8 compares the experimental and simulated values for a 20ms pulse. Fig
8a shows the dissipated power for a 20ms pulse, whereas 8b shows the
corresponding rise in junction temperature. No self-heating is seen in both the
actual and simulation model.
Fig 9a and 9b shows the same results for a 200s pulse. A 50s lag between
when heat is actually dissipated in the device and when the temp sense diode
begins to respond to this lag is seen at both ends when the device turns on
and after the device is turned off. This is because of the spatial separation
between the tempsense diode and active device junction where heat
dissipation takes place. The dip in the dissipated power seen in the
experimental value is because of the large capacitors used in the power
supply to deliver big currents in small pulse durations and not because of the
self-heating effect of the device.

Dissipated Power for 200us pulse

6000

Power(watts)

5000
4000
3000
2000
1000
0
-0.0003

-0.0001

0.0001

Power(meas)

0.0003

Power(sim)

0.0005

0.0007

Time(sec)

Figure 9a

Tj for 200us pulse

50

Temp(C)

40
30
20
10
0
-4E-04 -2E-04

Tj(meas)

0.0002 0.0004 0.0006 0.0008 0.001

Tj(sim)
Time(sec)

Figure 9b

8. To demonstrate the self-heating effect of the model

If we deliver a current of about 800Amps to the mosfet for a pulse duration
200s from an ideal power supply. The developed model (level 3 model) will
show a decrease in the drain current with increasing junction temperature i.e.
there is a feedback path between the thermal and electrical equivalent
models. Whereas a level 2 model (without self heating) does not show this
capability as seen in Fig 10.

900
140
800
Figure 9a
120
700
100
600
500
80
400
60
300
200
40
100
20
0
-100
0
-5.00E-06 9.50E-05 1.95E-04 2.95E-04

Id(with
selfheating)
TJ(degC)

Id(Amp)

100 us pulse

Id(without
selfheating)

Tj

Time(sec)

Figure 10

9. Conclusion
In this work a level 3 MOSFET model in Pspice has been presented. To
validate the model some experiments were carried out and an excellent fit
between the two down to ms pulses was seen. Shorter timescales are limited
by 50s lag in Temperature-Sensor. A new approach was introduced where
the interested designers can monitor the forward voltage drop of the
Temperature sensing diode at 1mA and thus can compare it against the rise
in junction temperature.

References.
1) Power Semiconductor applications handbook. Philips semiconductors
2) Or cad Pspice reference manual.
3) A new Pspice Power MOSFET sub circuit with associated thermal
model by Filippo Di Giovanni, Gaetano Bazzano, Antonio Grimaldi
STMicroelectronics Catania (Italy)
4) Thermal modelling of power electronic systems Dr. Martin Mrz, Paul
Nance Infineon Technologies AG, Munich