1 Material On Embedded Systems

Definitions
An Embedded System is a computer based

system for an application(s) or product with
dedicated software embedded in it. It may be
an independent system or part of large system
Definitions
It is any device that includes a
programmable computer but is not itself
intended to be a general purpose
computer. Wayne Wolf
Definitions
Embedded Systems are the electronic systems

that
contain
a
microprocessor
or
a
microcontroller, but we do not think of them as
computers- the computer is hidden or
embedded in the system. Todd D. Morton
Introduction
Embedded System:
A digital system with at least one processor that
implements a hardware function that is a part or all of the
digital system
Facilitates designer to use a C or C++ program for
description and design of complex hardware functions
HLL programs replaces the writing of synthesizable HDL
code for detailed design of hardware
Embedded Processors: Processor(s) of an embedded
system
4
Introduction
Embedded Systems vs Micro-controllers:
Offer more flexibility and design customization
Offer the methodologies that include the use of hardware
and software in the same integrated design environment
Offer higher level design methods for integrating hardware
components with embedded processor
Evolution of digital devices

1945 1950 1955 1960 1965 1970 1975 1980 1985 1990 1995 2000
Transistors
ICs (General)
SRAMs & DRAMs
Microprocessors
SPLDs
CPLDs
ASICs
FPGAs
Source : The Design Warriors guide to FPGAs by Clive Maxfield,

Elsevier 2004
6
Classes of the Embedded Systems

1.
2.
Small scale system Single 8 or 16 bit microcontroller, little

hardware and software complexities Usually C/Assembly is
used for development of the system eg. C is compiled to
assembly then to executable codes to place in memory
Medium Scale System - Single or few 16 or 32 bit
microcontrollers or DSPs or RISCs, may also employ the
readily available ASSPs and IPs in the hardware, use
complex software design tools. Source code engineering
tool, RTOS, IDE (Integrated Development Environment) as
the development platform,
Classes of the Embedded Systems

3. Sophisticated system enormous hardware and
software
complexities,
may
also
employ
configurable processors with PLDs, hardware and
software co-design is used for the cutting edge
applications, for example, an iPod or Smart mobile
phone
Look at this
sunflower, a
natures gift
How does the
nature embed its
software? The
flower rotates its
face continuously
towards the Sun.
9
Processing Element in Embedded Systems
Example of Embedded System Hardware Elements
10
Processor in the Embedded Systems

1. GPPs
1.
2.
3.
4.
5.
Micro Processors
Micro Controllers
Embedded Processors
DSPs
Media Processors
11
General purpose microprocessor

ExampleMotorola
Intel
Sun
IBM
ARM
- 68HCxxx
- 80x86
- i860
-SPARC
-Power PC 601, 604
- Nios
CISC
CISC
CISC & RISC
RISC
RISC
RISC
12
Commonly used Microcontrollers
13
Commonly used Embedded Processors

ExampleAMD
Intel
ARM
- 29050
- i960
- ARM 7, ARM 9
RISC
RISC
RISC
14
Selection of a Processor
Final application requirements

Capabilities of the processor
Limitations of the processor
Knowledge and prior experience of the designer
Availability of tools for designing and debugging
software applications for the processor
15
Main Processor Vendors
16
Main PLD Vendors
17
PLD design tool by Vendors
18
Typical PLD Design Flow
19
Design of Digital systems:

Abstraction Levels
Transistors to Programs
Transistor level : putting transistors to implement a given
hardware function
Gate level: less details; tools were developed for utilization
of gates and verification of design;
RT level (RTL): focus on transfer of data happens
between registers, logic units, and buses
Electronic System level (ESL):
concerned with functionality of the system is to be designed and
the algorithms to be implemented;
System level tools: design entry tools, simulators, hardware
generation programs
20
10
Logic Circuit Design Concepts

Designing Combinational Circuits
Primitive gates and elementary structures (Muxs,
LUTs, etc.) form a set of structures with which any
digital circuit can be designed
Design is thought in terms of functionality
Boolean Algebra is used to make a correspondence
between logic gates and design functions
Boolean algebra postulates and theorems are used
for transformation of functions into gates
21

eg. Consider a three variable function f(a,b,c)
f = a.b + a.c + b.c
= a.b + a.c + b.c(a + a )

= a.b + a.c + b.c.a + b.c.a
= a.b.(1 + c) + a.c.(1 + b)
= a.b + a.c
Reduced function uses fewer gates, have less delay and
consumes less power
22
11

Visual Method to apply Boolean algebra rules
is Karnaugh Map
Iterative Hardware
Minimization of functions using Boolean rules or
by k-maps is only practical for small functions.
Partitioning based on regularity of a structure, or
based on independent functionalities, help in
breaking a circuit into smaller manageable
circuits.
23

Iterative Hardware
e.g. Consider a 4-bit comparator that generates a 1
when its 4-bit A input is greater than its 4-bit B input
The G output becomes 1 if is greater than Logically, this means

that the
product term forms an AND
24
12

Iterative Hardware
25

Many high level designs include multiplexers and decoders.
Single bit Mux
8-bit- 4-to-1 Mux
A multiplexer is like an n-position switch that selects one of its n

inputs to appear on the output. A multiplexer with n inputs is
called an n-to-1 Mux. A multiplexer with n data inputs requires
26
13
Decoder: A combinational circuit

that takes a certain code as input
and generates a different code.
eg. BCD to SSD decoder
A decoder has as many outputs
as it has combinations of inputs
eg. See fig, 2-to-4 decoder with
active low output
27

Enable/Disable inputs
Circuits with three-state
outputs require an OE
input.
if OE is active, the outputs
of the circuit are as
defined by the function of
the circuit.
However when OE is
inactive, all circuit outputs
become high-impedance
or float (Z value).
Fig. shows two 2-to-1
multiplexers with threestate outputs that are
wired to form a 4-to-1
multiplexer.
28
14

High-Level Design
First , the transistors were wired form upper-level
structures (primitive gates) with easier functionalities
that digital designers can relate to.
Then, gates are used in still higher level structures such
as adders, comparators, decoders and multiplexers.
These higher-level structures are useful to design at a
higher functional level, called as RT (Register Transfer)
level.
In today's designs, most design libraries include
configurable RTL components for designers to use
29

High-Level Design
eg. An Absolute Value Circuit:
Circuit uses an array of eight NOT gates, to complement
the input, an adder to add a 1 to this complement to
generate the two's complement of the input. The
multiplexer on the output for selection of output using the
sign-bit of the input.
30
15
Logic Design Concepts

Storage Elements/Memory circuits
To be able to design circuits that can make decisions
not only on present inputs but also based on past
history, we need to have circuits with memory.
This history enters the logic structure of a memory
circuit by way of feedbacks
Basic Latch:
Setting and Resetting the Basic Latch
31
Storage Elements/Memory Circuits

Clocked D Latch:
when clock is 1 a 1 on D causes s to become 1 which causes Q to set to 1,

and a 0 on D causes r to become 1 to reset Q.
when clock becomes 1, the value of D will be stored until the next time
that clock becomes 1.
32
16
Storage Elements/Memory Circuits

aClocked D-latch is used in applications for buffering
the data. For storing multiple bits of data, multiple
latches with a common clock is used.
33
Flip-Flops
Latch Feedback Causes Unpredictable Results
Master-Slave D Flip Flop: isolated input and output
34
17
Flip-Flops Control
The initial value of a flip-flop output depends on its
internal gate delays, and in most cases is
unpredictable. To force an initial state into a flip-flop,
set and reset control inputs can be used should be
used.
Flip-flops with Synchronous and Asynchronous Control
A Set or Preset control input forces a flip-flop into its 1 state, and a Reset or Clear input forces it to 0.
35
Flip-Flops Control / Register

Another control input for flip-flops is
a clock enabling input.
The structure formed by a group of flipflops with a common clock signal and
common control signals is called a
register.
An 8-bit Register
36
18
Designing Sequential Circuits

Finite State Machine (FSM)
The circuits that have memory are also called
sequential circuits and make decisions for a given
input depending on what it has memorized.
The number of states of a sequential circuit is
determined by its memory. A circuit with n memory bits
has 2n possible states.
Signals or variables representing these states (n of
them) are called state variables.
All sequential circuits - from a single latch to a network
of high performance computers - can be regarded as
an FSM.
37

These machines can be modeled as a combinational
circuit with feedback.
If the feedback path includes an array of flip-flops
with a clock for controlling the timing of data feeding
back, the circuit becomes a synchronous sequential
circuit.
Huffman model of synchronous sequential circuits
divides such a circuit into a combinational part and a
register part.
38
19
Huffman Model of a Sequential Circuit
39
Designing State Machines

Problem Description: A sequence detector with one
Input, x and one output, w, is to be designed. The circuit
searches on its x input for a sequence of 1011. If in four
consecutive clocks the sequence is detected, then its
output becomes 1 for exactly one clock period. The
circuit continuously performs this search and it allows
overlapping sequences.
For example, a sequence of 1011011 causes two positive pulses
on the output.
Searching for 1011
40
20

State Diagram: A state diagram is like a flowchart
and it completely describes our state machine for
values that occur on its input. Input events are only
considered if they are synchronized with the clock.
Each state has a name

(A through E) and a
corresponding output
value (w is 1 in E and
0 in the other states).
There are edges out of
each state for all
possible
values
of
circuit inputs.
State Diagram for the 1011 Detector
41

State Table: It enables us to form truth tables and/or
k-maps from circuit behavioral description.
42
21

State Assignment: Hardware
implementation requires all
variables in a circuit description
to be in binary. For this binary
representation, we assign a
unique binary pattern (binary
number) to each of the states
of our state table. This step of
the work is called "state
assignment".
State Variables are y2, y1, y0 .
State Assignment
43

Transition Table: State names in the state table must
be replaced with their corresponding binary values.
This table is called a transition table.
Transition Table for the 1011 Detector
44
22

Excitation Table: The combinational and the register
parts of the design are separated. The register part is
simply an array of flip-flops with a common clock
signal. The combinational part is where present
values of flip-flops (their outputs) are used as input to
generate flip-flop input values that will become their
next state values. Flip-flop input tables are called
Excitation Tables.
Tables for values of D2, D1, D0 and in our 1011
sequence detector are the same as those for y2+,
y1+, y0 + .
45
Flip-flop Excitation Table

46
23

Implementing the Combinational Part The steps of
design of combinational part is completely described by
the excitation table
This table includes values for D2, D1, D0 in terms of x,
y2, y1,and y0 . K-maps can be extracted from the table
47
The four-inputs (x, y2, y1, and

y0) and four-output (w, D2, D1,
D0 combinational circuit is fully
defined by Boolean expressions
48
24

The design of the 1011
sequence detector will be
completed by wiring the
gate-level realization of
the combinational part
with the flip-flops of the
register part. The
implementation is done
according to the Huffman
model.
49
Logic Block Diagram of the 1011 Detector

Mealy and Moore Machines:
If in a state machine output only uses state
variables and does not involve input, the state
machine is called a Moore machine.
In Mealy machine, the output value in each state
are specified on the edge out of the state, along
with input values i.e. the value of input decides
the value of the output.
50
25

Implementation of sequence detector with a Mealy
machine usually requires one state less than the Moore
machine that detects the same sequence.
1011 detector requires four states, two state variables,
and three 3-variable Karnaugh maps for the two state
variables and the output.
Mealy State Diagram
51

One-Hot Realization / Ring Counter Type:
This realization uses one flip-flop per state of the
machine. Since in a state diagram only one state is
active at any one time, only one of the
corresponding flip-flops becomes active
It uses more flip-flops than the binary state
assignment but uses fewer logic gates for activation
of the flip-flops.
52
26
Designing State Machines: Implementation
One-hot Implementation of Mealy Machine
Output of the AND gates on the outputs of the flip-flops

correspond to the edges that come out of the states of the state
diagram.
AND gates are conditioned by x=0 or x=1.
Flip-flops use four states (1000, 0100, 0010 and 0001) out of 24
53
possible states.
Designing State Machines: One-hot Realization

Initialization of a one-hot machine should be done
such that it is put into one of its valid states. Starting
the machine in 0000 is wrong because it will never
get out of this state.
Advantages of one-hot machines : ease of design,
regularity of their structure, and testability.
54
27
Designing Sequential Circuits

Sequential Packages
As there are commonly used combinational
packages, like adders, decoders and multiplexers,
there are commonly used sequential packages like
registers, counters and shifters.
Counter : A sequential circuit that counts a certain
sequence in ascending or descending order. An n-bit
binary up-counter counts n-bit numbers in the
ascending order.
55
Sequential Packages: Counters
State Diagram of a 2-bit up/down Counter
With each clock pulse, when UD is 1 it counts up and when UD is 0 it

counts down.
In the count-up mode the next count after 11 is 00, and in the countdown mode the next count after 00 is 11.
56
28
Excitation K-maps for a 2-Bit Up-Down Counter with D flip-flops
Implementation of Two-Bit Up-Down Counter
57

Counters with additional features:
Resetting :
Asynchronous resetting forces the counter into its initial state and acts
independent of the clock.
Synchronous resetting loads the initial state of the counter through the Dinputs of counter flip-flops,
Parallel loading: To start counting from a given state, the counter

is put into parallel-load mode and the designated start state is
loaded into the flip-flops of the counter.
Enabling :An enable input for a counter makes it count only
when this input is active.
Carry in and Carry out : carry-in and carry-out input and output
signals that are used for cascading
58
29
Mode
m1
m0
Operation
Disable the counter
Counter is reset to 0
Counter counts up
Parallel loading with P1, P0
Counter only counts if carry_in is 1, otherwise it is disabled.

When carry_in is 1 and counter reaches 11, the carry_out becomes 1.
Cascading counters can be done by connecting carry_out of one to the carry_in of another.59
Sequential Packages: Shifters

Shifters: The registers with the property to shift data
right or left with the edge of the clock. These are
used for serial data collection, serial to parallel, and
parallel to serial converters.
A 4-bit Shift Register

60
30
Memories:
Memories are twodimensional arrays of
flip-flops,
or
onedimensional arrays of
registers.
A 2n m-bit Memory
61
RTL Design with HDLs

Combinational Circuits
GATE-LEVEL COMBINATIONAL CIRCUIT
Behavioral Description:
Eg. 1-bit comparator: Use basic logic gates, which include not, and, or,
and xor cells, to implement the circuit with logic expression
eq = i0 . i1 + i0 . i1 (SOP form)
l i b r a r y ieee;
use ieee.std-logic-ll64.all;
e n t i t y eq1 i s
p o r t ( i 0 , il: in std-logic;
eq: out std-logic) ;
end eql;
a r c h i t e c t u r e sop-arch of eql i s
s i g n a l p0, p 1 : std-logic;
begin
eq <= p0 or pl;
p0 <= ( not i0) and ( not i1);
pl <= i 0 and il;
end sop-arch ;
62
31

Eg. Gate-level implementation of a 2-bit comparator
libraryieee;
use ieee . std-logic-1164.all;
entity eq2 is
port ( a , b : in std -logic - vector ( 1 downto 0 ) ;
a e q b : out s t d - l o g i c ) ;
end e q 2 ;
architecture sop-arch of eq2 is
signal p0, pl, p2, p3 : s t d - l o g i c ;
begin
a eq b <= p0 or p l or p2 or p 3 ;
p0 <= ( ( n o t a ( 1 )) and ( n o t b ( 1 ) ) ) and
p l <= ( ( n o t a ( 1 )) and ( n o t b ( 1 ))) and ( a ( 0 ) and b ( 0 )) ;
p2 <= ( a ( 1 ) and b ( 1 )) and ( ( n o t a ( 0 )) and ( n o t b ( 0 ))) ;
p 3 <= ( a ( 1 ) and b ( 1 )) and ( a ( 0 ) and b ( 0 )) ;
end sop - arch ;
63

Structural Description: To build a large system from simpler or predesigned components. VHDL provides a mechanism, known as
component instantiation.
2-bit comparator is to utilize 1-bit comparators as the building
blocks.
architecture struc-arch of eq2 is
begin
Signal e0, el: std-logic;
eq-bit0-unit : entity work. eql (sop-arch) -- instantiate two 1-bit comparators
port map (i0=>a(0), i1=>b(0), eq=>e0);
eq-bitl-unit : entity work. eql (sop-arch)
port map (i0=>a(1), i1=>b(1), eq=>e1);
aeqb <= e0 and el;
end struc-arch;
64
32
Combinational Circuits : Verification

Simulation is performed to verify the correctness of the circuit
operation and can be synthesized to a physical device. Simulation is
usually performed within the same HDL framework by creating a
special program, known as a test-bench, to mimic a physical lab
bench.
Test bench for a 2-bit comparator.
The uut block is the unit under test, the test vector generator block generates
testing input patterns, and the monitor block examines the output responses.
65
Combinational Circuits : Verification

Test-bench for a 2-bit comparator
66
33

RT-LEVEL COMBINATIONAL CIRCUIT
HDL description of module-level circuits, which are composed
of intermediate-sized components, such as adders,
comparators, and multiplexers; uses these components as the
basic building blocks in register transfer methodology, referred
to as RT-level design.
RT-LEVEL COMPONENTS: In addition to the logical
operators, relational operators and several arithmetic operators
can also be synthesized automatically. These operators
correspond to intermediate-sized module-level components,
such as comparators and adders.
67
Combinational Circuits: RTL

Operators and data types of VHDL-93 and IEEE std-logic-I164 package
68
34

Overloaded operators and data types in the IEEE numeric.std package
69

Type conversions between std-logic-vector and numeric data types
Concatenation operator : The concatenation operator, &, combines segments of

elements and small arrays to form a large array.
70
35

CONCURRENT ASSIGNMENT STATEMENTS
Conditional signal assignment Statements
Selected signal assignment Statements
Syntax and conceptual implementation: The simplified syntax of a

conditional signal assignment statement is
signal-name <= value-expr-1 when boolean-expr-1 else
value-expr-2 when boolean-expr-2 else
value-expr-n ;
The conditional signal assignment statement implies a cascading priority
routing network.
r <= a + b + c when m = n else
a - b when m > n else
c+1;
71

Implementation of a conditional signal assignment statement.
72
36

concurrent ASSIGNMENT STATEMENTS
Selected signal assignment Statements
Syntax and conceptual implementation: The simplified syntax of a selected
signal assignment statement is
with sel select
sig <= value-expr-1 when choice-1,
value-expr-2 when choice-2,
value-expr-3 when choice-3,
value-expr-n when others ;
The selected signal assignment statement implies a multiplexing structure.
signal sel : std-logic-vector (1 downto 0 ) ;
...
with sel select
r <= a + b + c when 00 ,
a - b when 11' ,
c + l when others ;
73

Implementation of a selected signal assignment statement.
74
37
Sequential Statements: Process

Process: VHDL contains a number of sequential statements, to execute these
statements, they are encapsulated inside a process.
A process itself is a concurrent statement. It can be thought of as a black box
whose behavior is described by sequential statements. Generally process is used
for two purposes:
Describe routing structures with i f and case statements.
Construct templates for memory elements
The simplified syntax of a process with a sensitivity list is
process (sensitivity-list)
begin
sequential statement;
sequential statement;
...
end process ;
Sensitivity-list: List of signals to which the process responds (i.e., is "sensitive to"). For a
combinational circuit, all the input signals should be included in this list. The body of a process is
composed of any number of sequential statements.
75
Sequential Statements: Process

process (a, b)
begin
c <= a and b ;
c <= a or b ;
end process ;
--is the same as
process (a, b)
begin
c <= a or b ;
end process ;
if they are concurrent signal assignment

statements, as in
-- n o t within a process
c <= a and b ;
c <= a or b ;
not allowed in most device technology
and thus is a design error
76
38
Sequential Statements:
IF AND CASE STATEMENTS: If and case statements are two other
commonly used sequential statements. Conceptually, they can be used to
describe routing structures.
If statement: Syntax
if boolean-expr_1
then
sequential_statements;
elsif boolean_expr-2 then
sequential_statements;
elsif boolean_expr-3 then
sequential_statements ;
...
else
sequential_statements ;
end i f ;
The Boolean expressions are evaluated sequentially

until an expression is evaluated as true or the else
branch is reached, and the statements in the
corresponding branch will be executed.
Note: The if statement must be encapsulated inside a process.
77
Case statement: Case statement uses the sel signal to select a
set of sequential statements for execution. Conceptually, case
statement infers a similar multiplexing structure during synthesis.
Syntax :
case sel is
when choice_1 =>
sequential statements;
when choice_2 =>
sequential statements ;
when others =>
sequential statements;
end case ;
78
39
Comparison to concurrent statements
The simple if and case statements are equivalent to the
conditional and selected signal assignment statements.
However, an if or case statement allows any number and any
type of sequential statements in their branches and thus is
more flexible and versatile.
79

CONSTANTS AND GENERICS
Constants: HDL code frequently uses constant values in
expressions and array boundaries. One good design practice is to
replace the hard literals with symbolic constants. It makes code
clear and helps future maintenance and revision.
Syntax:
constant const-name : data_type := value_expression;
For example, we can declare two constants as
constant DATA_BIT: integer := 8;
constant DATA-RANGE: integer : = 2**DATA_BIT - 1;
80
40

Constant:
Adder using a hard literal
Adder using a constant

81

a Generics: Construct generic, is to pass information into an entity
and component.
Syntax:
entity entity-name is
generic (
generic-name : data-type : = default-values ;
generic-name : data-type : = default-values ;
generic-name : data-type : = default-values
);
port (
port-name : mode data-type ;
);
end entity-name;
82
41
Adder using a generic
83
42

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Definitions

An Embedded System is a computer based

Embedded Systems are the electronic systems

Evolution of digital devices

Source : The Design Warriors guide to FPGAs by Clive Maxfield,

Classes of the Embedded Systems

Small scale system Single 8 or 16 bit microcontroller, little

Classes of the Embedded Systems

Processing Element in Embedded Systems

Example of Embedded System Hardware Elements

Processor in the Embedded Systems

General purpose microprocessor

Commonly used Microcontrollers

Commonly used Embedded Processors

Final application requirements

Main Processor Vendors

Main PLD Vendors

PLD design tool by Vendors

Typical PLD Design Flow

Design of Digital systems:

Logic Circuit Design Concepts

Designing Combinational Circuits

= a.b + a.c + b.c(a + a )

Designing Combinational Circuits

Designing Combinational Circuits

The G output becomes 1 if is greater than Logically, this means

Designing Combinational Circuits

Designing Combinational Circuits

Single bit Mux

8-bit- 4-to-1 Mux

A multiplexer is like an n-position switch that selects one of its n

Designing Combinational Circuits

Decoder: A combinational circuit

Designing Combinational Circuits

Designing Combinational Circuits

Designing Combinational Circuits

Logic Design Concepts

Setting and Resetting the Basic Latch

Storage Elements/Memory Circuits

when clock is 1 a 1 on D causes s to become 1 which causes Q to set to 1,

Storage Elements/Memory Circuits

Latch Feedback Causes Unpredictable Results

Master-Slave D Flip Flop: isolated input and output

Flip-flops with Synchronous and Asynchronous Control

Flip-Flops Control / Register

Designing Sequential Circuits

Finite State Machine (FSM)

Finite State Machine (FSM)

Huffman Model of a Sequential Circuit

Designing State Machines

Designing State Machines

Each state has a name

State Diagram for the 1011 Detector

Designing State Machines

Designing State Machines

Designing State Machines

Transition Table for the 1011 Detector

Designing State Machines

Designing State Machines

Flip-flop Excitation Table

Designing State Machines

Designing State Machines

The four-inputs (x, y2, y1, and