1

A Robust Design of SRAM Sense Amplifier for

Submicron Technology
1

Ziou Wang*, 2Yiping Zhang, 1Lijun Zhang, 3Xiaoyu Song

School of Electronics & Information Engineering, Soochow University, Suzhou 215001, China
2

Aicestar Technology Co, ltd3 Portland State University, USA

*Email: wziou@suda.edu.cn


AbstractSRAM sense amplifier plays a key role in memory
design. With technology scaling to the nanometer, the device
mismatch increases and the distribution effect induces unstable
signal injection, thus affecting the reliability of memory system.
This paper presents a new method for SRAM sense amplifier
design. It incorporates reasonable delay between the passgate
and enable signals to effectively mitigates the failure ratio and
keep the ratio less sensitive to signal slope. The novel amplifier
structure is both simple and easy to control. A reliable design is
given by considering both intrinsic and extrinsic offsets with
reasonable speed and power consumption. A failure ratio
analysis is performed. The result is validated using UMC 65nm
process model.

BL/BLB make BL potential rise quicker than BLB. This will

make the coupling unbalanced: more charge will be coupled to
the lower potential side, and the SA initial signal is suffered.
When SAEN becomes steeper, the coupling becomes more
serious.

Index Termssense amplifier, offset, slope, SRAM, memory.

I. INTRODUCTION

S CMOS process technology continues to scale down,

the performance gap between memory and CPU is
increasing. This results in the need of faster and larger scale
on-chip memories. Sense amplifier (SA) is the key component
of memory on the critical path and will impact on memory
performance [1] [2]. Signal and charge coupling effect will
cause offset voltage and make SA sensing fail. This effect will
be more serious with the technology scale down due to more
capacitor coupling. Figure 1 shows SA structure.
The basic function of SRAM SA is to amplify small signal
to full swing. The intrinsic offset includes Differential Charge
Injection (DCI) and Differential Signal Injection (DSI) [3].

A. DCI
In SRAM SA, assume BL is at a lower potential than BLB
which is kept at Vdd. When SA enable signal (SAEN) begins
to rise, the parasitical capacity will couple the signal to the SA
internal nodes SL (SLB) and raise the potential. But the
different resistive conduction of M1/M2 between SL/SLB and

978-1-4244-5798-4/10/$26.00 2010 IEEE

Fig. 1. Basic SA structure

B. DSI
When SAEN goes high, since BL has a lower node potential,
the equivalent resistance of M2 is smaller than that of M1.
High potential node SLB has a stronger signal injection. When
SAEN goes high enough, M1 will cut off earlier than M2,
extra signal will injects to SLB. This effect helps to sense and
is valid during SAEN rising. Clearly DSI is stronger when
SAEN rise slowly due to a longer extra signal injection time.

II. A NEW DESIGN FOR SRAM SA

A. Basic Principle
Here we present a new kind of SA with a lower failure ratio
not affected by SAEN slope[4]. From the figure 2, we can see
M5 are added. M5 is first turned on and the SA operates like a
DRAM SA. M5 contributes an additional current access to
GND. Because of the positive feedback, differential voltage of

2
SL/SLB increases. But speed is limited by large bit-line
capacity. After a short delay, M1/M2 are cut off to keep high
speed and low power consumption like a normal SRAM SA.
At the same time M6 is active to improve speed.

Fig.2. New SA structure and work principle

B. The Intrinsic Offset of the New SA

The DCI is eliminated by the pre-amplifying stage. Assume
BL has a little lower potential while BLB keeps high. When
SL/SLB are coupled by SAEN through the parasitical capacity,
the potential lifts. If there is not any other current path, the
coupled high signal will be shared with BL/BLB through
M1/M2. But Vgs of M1 is smaller than M2s. So I2 > I1 makes
SLB a faster sharing speed. The unbalanced currents cause a
reduction of differential voltage. At the first stage the
activation of current source M5 forms two additional currents
I3/ I4. Although coupled, M3 still has a higher Vgs, which
makes I3>I4. The additional differential currents can
compensate differential voltage reduction due to DCI. In this
way, SA sets up a safe path through M3/M4 to dissipate the
coupled signal instead of the dangerous path through M1/M2
completely. DSI effect is almost the same likes that of the
original SA, its valid time has only a little decrease.
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weakened when SAEN transition slows down. It can reduce

DCI and strengthen DSI to make the offset drop. So the failure
ratio of SA falls when SAEN slows down. In the new design,
SA failure ratio drops a little when SAEN slows down. On one
hand DCI is eliminated, on the other hand DSI becomes strong.
When the slope of SAEN is even, DCI can be ignored and only
DSI exist. At the very initial stage new SA works without the
help of DSI, traditional SA has a lower offset. But in practical
design, this kind of scheme is not easy to apply or in another
word, hard to control.
The safe design of the pre-amplifying stage is decided by
the offset current and technology mismatch. In order to
compensate DCI induced differential current I2- I1, we need
(1)
I 3  I 4 ! I 2  I1
Assume SL/SLB couples a higher Vcp. After M5 works, the
source potential of M3/M4 is at Vs, SL is at a potential Vn.
M1, M2 works in triode region:
(2)
I1 P p Cox (W / L) p [(Vn  Vcp  Vt )Vcp  0.5(Vcp ) 2 ]
I2

P pCox (W / L ) p [(Vn  Vcp  Vt  Vdiff )Vcp  0.5(Vcp ) 2 ]

M3, M4 works in saturation region:

I3

0.5P nCox (W / L ) n (Vn  Vcp  Vt  Vs ) 2

(4)

I4

0.5P nCox (W / L ) n (Vn  Vcp  Vt  Vs  Vdiff ) 2

(5)

For example, Vcp=10mv, Vt=0.22v, Vdd=1v, n/p=3,

(W/L)3/(W/L)1=3, Vn=1v, differential voltage Vdiff=0.1v, to
satisfy I3- I4> I2- I1,
(6)
Vn  Vt  Vs ! 4.9mv
only a 4.9mv fall is needed for Vs .
The calculation indicates that a slightly drop of Vs can
effectively eliminate DCI. With the differential voltage Vdiff
decreases, the Vs drop needed also reduces.
C. The Extrinsic Offset of the New SA
The requirement of I3- I4> I2- I1 is not enough for a safe
design when extrinsic offset is considered. First, we check a
MOSFET current distribution by applying Monte Carlo model
from UMC. We choose a NMOS width=1u, length=65n,
simulation 10000 times.
If Vs drops not enough, DCI will harm SA. But excessive drop
of Vs also suffered. Vs potential has other impact on offset
current due to the threshold voltage and mobility shift [3]. The
saturation current and its current differential are
(19)
I d E (Vgs  Vt )D W / L
'I d














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Fig.3. Offset failure rate comparison between New SA and traditional design

From the figure 3, we can find that the failure ratio of the
new SA can be free from SAEN slope effect. Comparing with
traditional design, new SA performs well when SAEN has a
steep transition, a little worse when SAEN has an even
transition. In traditional SRAM SA, the coupling effect is

(3)

'E (Vgs  Vt )D W / L  'Vt EDW / L (Vgs  Vt )D 1

(20)

is speed saturation coefficient. Id is the offset current.

We can see that Id rises with Vgs . From the figure 4, a
tradeoff width of M5 exists.
When SAEN slope is steep, the tradeoff is obvious. We can
easily find the optimum point from figure4 when slope is 10ps.
We need a 0.2/65n~0.5/65n size M5. Figure 5 shows new
SA failure ratio varies with the SAEN slope at different
NMOS size. Further increase width of M5, extrinsic offset
current will dominate the offset and failure ratio increase.

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Fig. 7. New SA power varies with SAEN slope

Fig. 4. New type SA offset failure rate varies with the width of M5

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We set initial SA differential voltage 100mv as in practical

(BL 1v BLB 0.9v). Simulation use UMC 65nm SPRVT model
typical corner, temperature 25. Set delay 50ps. In the new
SA, speed and power are sacrificed a little. It is because in the
first amplifying stage, the large capacity of bit-line is not
detached from internal node. Only when the SAEN has a very
long transition time, the power consumption of new SA can be
better than traditional SA. But it is worthy for a safe design. A
tradeoff sized NMOS is favored when speed and power
sacrificed a little while offset is almost eliminated.

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III. CONCLUSION









        

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Fig. 5. failure rate varies with the SAEN slope

When SAEN transition becomes slower, DCI is weakened

and the optimum point moves to smaller size. Especially when
DCI is ignored, offset will only be dominated by Vs potential.
Failure ratio drops slowly when size of M5 is reduced. We can
see the phenomenon in figure 6 when SAEN slope is 500ps.
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This paper presented a robust method for SRAM sense

amplifier design. By incorporating reasonable delay between
the passgate and enable signals, and with the help of the
additional grounded NMOS, the new SA has shown its
advantage in reducing the failure ratio by effect of offset and
keeps the ratio less sensitive to signal slope. A reliable design
is given by considering both intrinsic and extrinsic offsets. A
failure ratio analysis was performedwith reasonable speed
and power consumption, a satisfied failure ratio can be
obtained by a tradeoff sized grounded NMOS, meanwhile it
has simpler adjustment and control method compared with
some previous work. The result was validated using UMC
65nm process model.



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REFERENCES



[1]



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Fig. 6. New SA speed varies with SAEN slope

[3]

D. Speed and Power

Applying various SAEN slope and M5 size, we get the
curve of speed and power, shown in figure 6, 7.

[4]

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