ECE 250 EXAM # 2

Name:

Closed book, multiple choice exam. Choose the one best answer.
1.

______
Lab Section: ________

If QDQCQBQA = 1101 initially, what are the contents of the shift register below after the input
sequence SI = 10 is applied? (Assume 2 clock pulses are used.)
1) 1111
2) 1001
3) 0110
4) 1101
5) 1110

2.

What frequency clock source will produce clock waveforms having a period equal to 2.0 m sec?
1)
2)
3)
4)
5)

3.

50 kHz
2.0 MHz
2 kHz
.05 MHz
500 kHz

2) two

3) three

4) four

=
=
=
=

10-6
10-3
10+3
10+6

5) none

3) OUTPUT LOGIC BLOCK

Region A
Region B
Region C
Region D
Region E

The sequential logic circuit shown above represents most closely the basic architecture of a:
1)
2)
3)
4)
5)

7.

micro
milli
kilo
Mega

Qn-1 is stable over which of the following clock regions?

1)
2)
3)
4)
5)

6.

=
m =
k =
M=

In general, the Present State of a sequential logic circuit is determined by the:

1) MEMORY ELEMENTS 2) INPUT LOGIC BLOCK
4) INPUTS only
5) OUTPUTS only

5.

How many transient states does a 4-bit ripple counter transit through between count = 1011 and
count = 1100?
1) one

4.

Note:

Data-latch register
Ripple counter
Synchronous counter
Shift register
Up/Down counter

A circuit which translates n input lines into 2n output lines is defined as a

1) MUX
2) DeMUX 3) Decoder
4) Encoder
5) ROM

8.

Which of the following will correctly complete the JK flip-flop truth table shown below?

9.

Given the (partial) nMOS ROM decoder shown, where A 2 A 1 A 0 are address inputs (A 0 is least
significant), identify the decoder output (select line) Y :
1) Y = Y 0
2) Y = Y 2
3) Y = Y 3
4) Y = Y 4
5) Y = Y 7

10. Suppose Q 1 = 1 and Q 2 = 1 is the initial state of the two flip-flop (M/S) circuit shown. What is
the state of the circuit after application of two complete clock pulses to the first flip-flop?
1) Q 1 = 0, Q 2 = 0
2) Q 1 = 0, Q 2 = 1
3) Q 1 = 1, Q 2 = 0
4) Q 1 = 1, Q 2 = 1
11. Which of the following waveforms can be generated by the output QA of the synchronous counter
shown? (QA is least significant)
CLOCK - - - - - - - - 1) QA ___--__--__--__--__--__--__-2) QA
--------------3) QA
---------4) QA
-----------5) QA
------------12. A ROM having 12 address lines and 4 outputs is given. What is the total capacity of the ROM?
1) 12 K
2) 13 K
3) 14 K
4) 15 K
5) 16 K (Note: K = 1024 = 2 1 0)

13. Where should the left and right arrows be directed in

order that the state diagram illustrated detect the
sequence X = 1111 with overlap?
1) Left: a Right: a
2) Left: c Right: a
3) Left: a Right: c
4) Left: c Right: d
5) Left: a Right: d
14. What is the logic equation for the output Z for the state diagram of the previous question, if the
following state assignments are given: a = 00, b = 01, c = 11, d = 10.
1) Z = X Y1 Y2
2) Z = X Y1 Y2
3) Z = X Y1 Y2
4) Z = X Y1 Y2
5) Z = X Y1 Y2
15. Indicate the programming connections required (1 to 8) to implement a OR function using the PLD
AND array shown below:
1) 1, 7 (only)
2) 1, 7, 3, 4
3) 2, 4
4) 2, 8
5) 6, 8
16. Given the state table below, the output sequence generated by an input sequence X = 0111000 and
starting state c is
1) Z = 0111011
2) Z = 1001001
3) Z = 0110010
4) Z = 1001101
5) Z = 1001100

Note:
PS = Present State
X = Input
NS = Next State
Z = Output

PS
a
a
b
b
c
c
d
d

X
0
1
0
1
0
1
0
1

NS
b
a
d
a
c
d
c
a

Z
1
1
0
1
1
0
1
0

17

A 3-line to 8-line decoder is connected as shown,

where x,y and z are inputs (z is least significant)
and F is a output. Which of the following
expressions corectly describes F?

1) F = x
2) F = y
3) F = x y
4) F = y z
5) F = x z
18

The logic circuit shown represents most closely the architecture of a:

1) Simple Latch
2) SRflip-flop
3) D Latch with Enable (Correction)
4) JK flip-flop
5) T flip-flop

19.

Which of the following modifications to the SLC block diagram would most likely lead to nonsequential behavior?
1) Remove the OUTPUT LOGIC BLOCK so Z = Y
2) Remove all inputs except the CLOCK
3) Remove the INPUT LOGIC BLOCK, so the INPUTS go directly to the MEMORY
4) Open the feedback path.
5) None of the above modifications could lead to nonsequential behavior.

20.

Given the variablesY1n, Y2n, and input X, which of the following represent the correct contents
of the K2 K-map given the next state mapY2n+1z?

1)

2
d

4
0

3)
d

)
0

5)
0

Form A