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Phys. Status Solidi C 11, No. 34, 906 910 (2014) / DOI 10.1002/pssc.201300490
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Comparison of AlGaN/GaN
MISHEMT powerbar designs
Steve Stoffels*, Nicol Ronchi, Rafael Venegas, Brice De Jaeger, Denis Marcon,
and Stefaan Decoutere
Imec Leuven, Kapeldreef 75, 3001 Leuven, Belgium
Received 23 August 2013, revised 7 October 2013, accepted 12 December 2013
Published online 11 February 2014
Keywords AlGaN/GaN powerbar, MISHEMT, design, modelling
* Corresponding author: e-mail steve.stoffels@imec.be, Phone: +32 16 288506, Fax: +32 16281844
b)
a)
c)
Figure 1 Schematic drawing of the a) LGF, b) SGF, c) 3DI designs.
2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim
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Phys. Status Solidi C 11, No. 34 (2014)
Figure 2 Lumped equivalent circuit representation of the interconnect parasitics of an AlGaN/GaN PowerHEMT.
907
work. It was assumed that the distributed network consisted of purely resistive components, and secondly it was
assumed that for each port all the connections of the interconnect elements to the active region were equipotential,
which were then referenced to ground. An example of a cut
out of a lumped circuit for a portion of the SGF design is
shown in Fig. 3.
Figure 3 Distributed resistance network for a portion of the gatebus for the SGF design.
The geometry of each of the designs was analysed and partitioned in sections through which the current could only
flow in one direction. The resistance (R) of each partition
could be calculated, using the value for the sheet resistance
(Rsh):
R = Rsh W/L ,
(1)
(2)
(3)
(4)
where 0 is vacuum permittivity, r is the relative permittivity of the dielectric, dn is the thickness of the dielectric,
2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim
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have performed gate resistance and capacitance measurements, with an impedance analyzer and LCR meter. The Rg
was measured by biasing the device in the on-state. It is assumed that the gate-source branch acts as a series resistance (Rs), dominated by (Rg), and series capacitance (Cs),
the values can be determined from the measured impedance data. The extraction is done internally in the LCR meter. It can be seen from Fig. 5 that there is a good agreement between the analytical calculations and the measured
gate resistance. Furthermore, it can be seen that the 3DI
and LGF design have Rg values which are about 10x lower
than the original LGF design, reaching our design goal.
This demonstrates the capabilities of the modelling methodology presented in this work.
Calculating the different values for the capacitances revealed that the parasitic impedances are mainly caused by
the vertical interconnect overlap capacitances and the interconnect to substrate capacitances (Table 1). Also the
source field plate plays an important role in the contribution to the parasitic capacitance. For the power transistor
designs the lateral separation is large enough that fringing
field capacitances and horizontal overlap capacitance only
has a negligible influence.
gate-source
gate-drain
source-drain
Fringing
Bulk
Overlap
1.410-15
1.410-15
210-15
510-12
510-12
1.210-11
1.310-11
0
0
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Phys. Status Solidi C 11, No. 34 (2014)
The on-state capacitances were measured with an LCR meter, with the transistor biased in the on-state. The extraction
of the capacitance value was achieved by using a series
Rs-Cs model. As can be seen in Fig. 7, an accuracy between
measurement and simulation of better than 20% was
achieved. Furthermore, the SGF design has a value for the
on-state capacitance, which is very similar to the LGF design. For the designs where there is much overlap between
the interconnects (as is the case for the 3DI and LGF-W
design), the capacitance is slightly higher.
5 Figures of merit As was demonstrated in previous
section, the modelling framework allowed us to design
power transistors with a lowered gate resistance, with a
minimal impact on the capacitance. In this section several
key figure of merits will be compared.
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6 Conclusions For this work we have shown a modelling framework which can, from simple analytical models, give a good description of the interconnect parasitics.
For each of the analysed topologies a good agreement was
achieved between simulated values and measurements. The
SGF/3DI power bar designs reached the design goal of reducing the gate resistance with a factor of 4 to 8 with respect to the long gate finger designs, while having limited
impact on the FOMs Ron,sp, RonCg,son and V 2BD/Ron,sp. The
3DI did exhibited a reduced value for the FOM V 2BD/Ron,sp
due to vertical breakdown at the interconnect crossings.
However, this was expected as no optimization was performed on the inter-metal dielectrics (IMD) and will be
addressed in future process iterations.
References
[1] D. Ueda et al., AlGaN/GaN devices for future power
switching systems, Tech. Digests of IEDM, Dec. 2005, pp.
377-380.
[2] S. Decoutere et al., GaN-on-Si:A scalable material system
to realize cost effective next-generation solid state lighting
and power devices, Symposium on VLSI Technology, 2010,
pp. 151-152.
[3] T. Imada et al., Enhancement-mode GaN MIS-HEMTs for
power supplies, in: IPEC, 2010 IEEE, Jun. 2010, pp. 10271033.
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