COUNTERS

AIM
Realization of 3-bit counters as a sequential circuit and Mod-N counter design (7476, 7490,
74192, 74193).

APPARATUS REQUIRED
1. Digital Trainer Kit.
2. IC 7408, IC 7476, IC 7490, IC 74192, IC 74193, IC 7400, IC 7416, IC 7432.
3. Power Cables.
4. Connecting Probes.
THEORY
Only synchronous counters will be described because of their simplicity. A synchronous
counter is one in which all the flip-flops change state simultaneously since all the clocks inputs
are tied together. Counters are usually constructed of T flip-flops since the flip-flops only have to
toggle at a given sequence. A 3-bit synchronous counter is shown below.
C

T
C

Q
Q

FIGURE 29. 3-Bit synchronous counter.

The equations for the flip-flops are T1 = 1; T2 = Q1; T3 = Q1 Q2. Thus T1 toggles at every
clock pulse, T2 toggles only when Q1 is high, on every other clock pulse, and finally T3 toggles
when both Q1 and Q2 are high, or every fourth clock pulse. The counting sequence is shown
below:

STATE
Count

r e p e

a t

This type of counter can be extended by the following set of equations.

T1 = 1
T2 = T1
T3 = T1T2
Tn = T1T2Tn-1
Counter Designs
The 'Detect and Steer' method works by constructing the appropriate combinational control
logic at the input of each flip-flop so that the counter progresses through the desired states. A list
of general steps used to design a counter by this method is shown below.
1.
2.
3.
4.

Start by writing the desired counting sequence.

From 1 determine which flip-flop must change when going from the last state to the first.
Generate the control circuitry for each flip-flop from the analysis done in 2.
This can best be shown by the following design of a Mod-11 synchronous binary counter.

STATE

Inhibit D,
Force A & C

A is the most significant bit

Count

Decimal

10

10

11

0
r

12

0
e

D is the least significant bit

C changes
B,C change
C changes
A,B,C change
C changes
A,C change

To find the expression for the T flip-flop inputs, note that there are several unused states that will
add dont cares to the K-map. These are ABCD = 1011, 1100, 1101, 1110 & 1111. For the T 4
input for A, this flip-flop should change (T 4 = 1) when ABCD = 0111 & 1010. The K-map with
the dont cares will be:
CD
AB

00
00
01
11
10

01

11

1
d
d

10

d
1

d = dont care
T4 = BCD + AC

Similarly, T3 for B needs to be 1 when ABCD = 0011 & 0111. The corresponding K-map is:
CD
AB

00
00
01
11
10

01

11
1
1
d
d

10

d = dont care
T3 = CD

You should work out the expression for Cs T2 flip-flop, noting that there will be six 1s in the Kmap. The T1 expression for D could also be done this way, but since D changes almost every
time, it is easier to look at the case when it doesnt change. Instead of filling up the K-map with
all 1s except for the lower right corner, we will put a 0 in for the ABCD = 1010 state and find the
inverse (NOT) expression. Now the K-map will look like:

CD
AB
00
01
11
10

00
1
1
d
1

01
1
1
d
1

11
1
1
d
d

10
1
1
d
0

d = dont care
T1 = AC

Once we detect the 1010 state for D (detecting AC) we can summarize all the T flip-flop input
expressions:
A C

D = T1 =
C = T2 = D + A C
B= T3 = C D
A = T4 = B C D + A C

inhibits only on A C; otherwise 1

A C is the force term
A C is the force term

PROCEDURE
1. Connections are made as per circuit diagram.
2. Clock pulses are applied one by one at the clock I/P and the O/P is observed at QA, QB & QC
for IC 7476.
3. Truth table is verified.
Procedure (IC 74192, IC 74193):1. Connections are made as per the circuit diagram except the connection from output of NAND
gate to the load input.
2. The data (0011) = 3 is made available at the data i/ps A, B, C & D respectively.
3. The load pin made low so that the data 0011 appears at QD, QC, QB & QA respectively.
4. Now connect the output of the NAND gate to the load input.
5. Clock pulses are applied to count up pin and the truth table is verified.
6. Now apply (1100) = 12 for 12 to 5 counter and remaining is same as for 3 to 8 counter.
CIRCUIT DIAGRAM

3-BIT ASYNCHRONOUS UP COUNTER

3-BIT ASYNCHRONOUS DOWN COUNTER

MOD -5 ASYNCHRONOUS COUNTER

MOD -3 ASYNCHRONOUS COUNTER

3-BIT SYNCHRONOUS COUNTER

IC 7490 (MOD 8 COUNTER)

CIRCUIT DIAGRAM TO COUNT 3 TO 8 DECODER(IC 74193)

CIRCUIT DIAGRAM TO COUNT FROM 8 TO 3 DECODER(IC 74193)

FUNCTION TABLE FOR 7490

RESULT