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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 62, NO. 8, AUGUST 2015

PVT-Aware Design of Dopingless Dynamically

Configurable Tunnel FET
Avinash Lahgere, Chitrakant Sahu, Student Member, IEEE, and Jawar Singh, Senior Member, IEEE

Abstract This paper presents a new design of dopingless

dynamically configurable double-gate tunnel FET (TFET)
for processvoltagetemperature (PVT)-aware applications. The
dopingless FETs have recently been explored and showed
very good electrostatic control over the channel with reduced
thermal budget and process complexity. The proposed device
makes use of the dopingless concept, but instead of charge
plasma, electrostatic doping is used for carrier concentration
under the source/drain region that allows dynamic configuration.
The 2-D device simulation results show that the proposed device
has promising switching behavior and offers significant reduction
in PVT variations on different performance metrics, such as
subthreshold swing and drive current as compared with a
conventional TFET.
Index Terms Band-to-band tunneling (BTBT), charge
plasma, CMOS, dopingless, processvoltagetemperature (PVT),
random dopant fluctuation (RDF), tunnel FETs (TFETs).

I. I NTRODUCTION
S WE are moving toward a sub-20-nm CMOS
technology regime, short-channel effects (SCEs) and
processvoltagetemperature (PVT)-induced variations, such
as random dopant fluctuation (RDF), thickness of silicon thin
film, and gate oxide with temperature, enormously affect the
device electrical parameters [1]. These variations significantly
increase the chances of failure and cut down the reliability
margins of the devices [2][5]. Among many possible devices,
tunnel FETs (TFETs) are captivating broad attention because
of their low-leakage current, low power consumption, and
scalable subthreshold swing (SS) [6][13]. However, the
requirements of higher doping concentration and abrupt
doping profile at junctions in these devices further exaggerate
the SCEs and RDF [14], [15].
While considering the potential merits of TFETs,
we have proposed a PVT-aware dopingless dynamically
configurable TFET. In a dopingless FET (DL-FET) [16][18],
source/drain (S/D) regions were formed with metal work
function engineering, referred to charge plasma, and showed
very good control over SCEs and RDF. In the proposed
device, dopingless (or lightly doped) Si is used, and the
formation of drain (D)channelsource (S) is achieved with

Manuscript received January 26, 2015; revised March 20, 2015,

April 24, 2015 and June 6, 2015; accepted June 15 2015. Date of publication
June 7, 2015; date of current version July 21, 2015. The review of this paper
was arranged by Editor H. Jaouen.
The authors are with the Department of Electronics and Communication Engineering, PDPM Indian Institute of Information
Technology Design and Manufacturing, Jabalpur, 482005, India (e-mail:
avinash.lahgere@iiitdmj.ac.in; chitrakant@iiitdmj.ac.in; jawar@iiitdmj.ac.in).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2015.2446615

Fig. 1. Cross-sectional view of (a) conventional TFET [7] and (b) proposed
ED-TFET.

the application of appropriate bias at polarity gates (PGs)

(i.e., electrically doped) yield p+ and n+ S/D regions;
hence, the device becomes dynamically configurable to
switch between n- and p-type TFETs. These unique
features eliminate the requirements of abrupt doping profile at
junctions, higher thermal budget, and ion-implantation process
for device fabrications. The combination of junctionless and
dopingless mechanisms in the proposed device yields a
simpler fabrication process and very good electrostatic
control over the channel [19], [20].
The dynamically configurable devices may play a crucial
role to only realize the complementary Boolean functionality,
and higher packaging and integration density when one can
guarantee the symmetric I D VG characteristics for both
n- and p-type of devices, and scalable SS at room temperature.
In [21][24], configurable logic gates with polarity controlled
silicon nanowire (SiNW) FETs have been demonstrated;
however, they have the limitations of asymmetric I D VG characteristics and nonscalable SS at room temperature. Therefore,
our proposed device provides full benefits of configurability
by yielding symmetric I D VG characteristics, scalable SS,
low-leakage current, and PVT insensitivity. These features
are indispensable for configurable logic gates based on
complementary Boolean functionality and other applications.
II. D EVICE G EOMETRY AND S IMULATION PARAMETERS
Fig. 1(a) shows the cross-sectional view of a conventional TFET, and the simulation parameters adapted

0018-9383 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.

LAHGERE et al.: PVT-AWARE DESIGN OF DOPINGLESS DYNAMICALLY CONFIGURABLE TFET

from [7] are as follows: 1) ultrathin silicon film thickness

(TSI ) = 10 nm; 2) effective gate-oxide thickness
(TOX ) = 0.8 nm; 3) channel length (L g ) = 50 nm;
4) channel region doping = 1 1017 cm3 ; 5) p+ source
doping N A = 1 1020 cm3 ; 6) n+ drain doping
N D = 5 1018 cm3 ; and 7) metal control-gate (CG)
work function = 4.5 eV. Fig. 1(b) shows the cross-sectional
view of the proposed electrically doped TFET (ED-TFET)
structure, and the simulation parameters are considered as
the same as for the conventional TFET, except for doping
concentration. In the ED-TFET, p+ source and n+ drain
regions are formed using the PG concept [21], [22].
Furthermore, for creating a n+ drain region having electron
concentration similar to a reference device, sufficient positive
bias is applied at PG-1 (50 nm). Similarly, for a p+ source
region having hole concentration equivalent to the reference
device, sufficient negative bias is applied at PG-2 (50 nm).
In addition, metal work function for PGs are the same as CG,
and S/D contact made up of nickel silicide (NiSi) with a
barrier height of 0.45 eV [21]. Spacer thickness at the source
side (SGAP, S ) is kept 5 nm between CG and PG-2, and spacer
thickness at the drain side (SGAP,D ) is kept 20 nm between
PG-1 and CG.
The conventional TFET and the proposed ED-TFET
are
simulated
using
a
2-D
device
simulator,
Atlas Silvaco V5.19.20 [25]. The nonlocal band-to-band
tunneling (BTBT) model is enabled in order to account
tunneling mechanism given in [7] and [18]. To calculate
the tunneling probability using an electron-hole wave vector
throughout the tunneling path, the nonlocal model uses the
WentzelKramerBrillouin approximation. The trap-assisted
tunneling is also enabled given by Schenk. For a better
comparison, we have not included the bandgap narrowing
model, because it is used for higher channel doping [18].
Since we are using NiSi contacts at the drain and the
source terminals, we have enabled the universal Schottky
tunneling model. In addition, for observing the impact of
temperature, we have enabled the Klaassen and the analytic
physical models for relating low-field carrier mobility with
temperature.

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Fig. 2. (a) Electron and hole concentration and (b) energy band diagram
of ED-TFET (VDS = 1 V, VPG1 = 1.2 V, and VPG2 = 1.2 V) in
OFF-state (VCG = 0 V) and ON -state (VCG = 1.2 V).

III. S IMULATION R ESULTS AND D ISCUSSION

To realize an n+ -i-p+ like structure in the proposed
ED-TFET, appropriate biases need to apply across PGs; as a
result, carrier concentration in different regions and conditions
can be achieved, as shown in Fig. 2(a). In the ED-TFET,
the carrier concentration along the horizontal cutline near the
top surface of a silicon film is equivalent to the conventional
TFET, as reported in [7], except fall down at the S/D contact
due to NiSi. It is worth mentioning that, on applying
VCG = 1.2 V, the electron concentration in the intrinsic (I )
region becomes of the order of 1019 cm3 , which is equivalent
to n+ region. Hence, the proposed approach ensures an abrupt
p-n junction for the tunneling of electron carriers from the
valence band (VB) of p+ to the conduction band (CB) of
the I region.
To further investigate the tunneling mechanism in the
proposed structure, CB and VB energies in OFF- and ON-states

Fig. 3. I D VG characteristics of the conventional and the proposed TFETs

for VDS = 1 V. Inset: I D VG characteristic for p-type ED-TFET.

are shown in Fig. 2(b). In OFF-state, it can be observed that

the probability of electron tunneling from the VB of p+ to
the CB of I is very low because of a high-energy barrier
width at CG and PG-2 junction. Two different PG biases are
applied to separate the energy bands near the source and the
drain regions, and to accumulate the charge carriers. When
a bias is applied to CG (i.e., ON-state), CB and VB in the
I region get aligned with the CB and the VB of n+ region; as a
result, energy barrier width is reduced, which makes higher
probability of electron tunneling from the VB of p+ into the
CB of I region.
Fig. 3 shows the I D VG characteristics of the n-type conventional TFET and the proposed ED-TFET, and it can be

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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 62, NO. 8, AUGUST 2015

Fig. 5. Impact of PG bias on (a) transfer characteristics and (b) OFF-state

band diagram.

Fig. 4.

I D VG characteristic of ED-TFET for different VDS .

observed that the proposed ED-TFET has followed the same

trend as the conventional TFET [7]. One can observe that
the ON-state current of the proposed ED-TFET is one order
of magnitude less than the conventional TFET. It is mainly
due to high ON-state resistance offered by the dopingless
architecture as compared with the conventional doped devices,
as reported in [17]. In the conventional TFETs, ON-state
resistive components are channel resistance (Rch ) and
tunneling width resistance (Rtunnel), whereas the ED-TFET
has two additional resistive components: 1) source-side
spacer resistance (RSGAP,S ) and 2) drain-side spacer resistance (RSGAP,S ). The ON-state current in the ED-TFET can
be improved by adapting low-bandgap materials, strain
technology, heterostructures, and so on.
However, the OFF-state current in the ED-TFET is very less
(order of 1019 A/m) as compared with the conventional
TFET (order of 1016 A/m). This happens because of
lightly doped Si film and the absence of p-n junctions in
thermal equilibrium. In addition, the proposed ED-TFET
possess a potential advantage of very steep SS of the
order of 12 mV/dec, whereas, for the conventional TFET,
it is of the order of 24 mV/dec. Furthermore, to guarantee the
dynamic configurability and symmetric I D VG characteristics
of the proposed device, we reversed the bias across
PGs that represent p-type ED-TFET and observed the
I D VG characteristics, as shown in Fig. 3 (inset). The
symmetric I D VG characteristics, very low-leakage current,
and steep SS of the proposed device make it a suitable
candidate for dynamically configurability. For the sub-0.5 V
operation, supply voltage (VDS ) is scaled down from
0.5 to 0.3 V that reduces ION slightly (80%) because of
the decrement in the lateral direction electric field, as shown
in Fig. 4. However, supply voltage scaling has insignificant
effect on leakage current and paves the way for low-power
applications.
Fig. 5(a) and (b) shows the impact of PG bias on transfer
characteristics and the OFF-state band diagrams of the
proposed ED-TFET. One can infer from Fig. 5(a) that the
scaling of PG bias causes the increment in the OFF-state
current, which is coherent with the previously reported
results [22]. This is happening due to the reduced energy

Fig. 6.
Impact of gate-length scaling on transfer characteristics.
(a) Conventional TFET. (b) ED-TFET.

barrier at the drain side that allows the flow of carriers from the
drain to the channel side. In other words, the reduced PG bias
results in the reduced number of accumulation carriers due to
lower vertical electric field. In addition, the decrease in carrier
concentration lower the bend edges in the drain side that can
be seen in Fig. 5(b), consequently higher OFF-state current.
Fig. 6(a) and (b) shows the effect of gate-length scaling on
the I D VG characteristics of the conventional TFET and the
proposed ED-TFET. For the scaling of gate length, we have
kept both the spacer thicknesses and the overall device length
constant. It can be inferred that the scaling of gate length
causes the increment in the IOFF current for both the devices.
This happens due to the reduction in barrier width at source
junction, which is consistent with the previously reported
result [26]. Moreover, one can observe that the variation in the
IOFF current for the conventional TFET is significantly higher
as compared with the proposed ED-TFET with gate-length
scaling. It is mainly due to gate-length scaling causes higher
reduction in effective channel length in the conventional
doped devices as compared with the DL-FETs [16], [17].
Furthermore, scale down the gate length from 50 to 20 nm, the
ION /IOFF ratio of the conventional TFET is approximately varied from 1011 to 108 , whereas for the ED-TFET, it is almost
constant of the order of 1012 . Hence, the proposed device can
easily be scaled down without affecting the ION /IOFF ratio.
Fig. 7(a) and (b) shows the output characteristics of the
conventional TFET and the proposed ED-TFET for different
values of VCG . In the triode region, as we increase VDS , the
higher number of carriers tunnels and establishes an exponential relationship with IDS due to drain-induced barrier thinning.
A very good saturation region is observed due to less reliant
tunneling width with VDS . Furthermore, to sustain higher ION
and steep SS at room temperature, it is indeed an important

LAHGERE et al.: PVT-AWARE DESIGN OF DOPINGLESS DYNAMICALLY CONFIGURABLE TFET

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Fig. 7. Output characteristics of (a) conventional TFET and (b) ED-TFET

for different CG voltages.

Fig. 9. ON-state current (ION ) and SS of ED-TFET for different source-side

spacer thickness (SGAP,S ).

Fig. 8. Effect of VCG over energy barrier width and electron tunneling rate
for ED-TFET.

requirement to keep minimum energy barrier width and highcarrier tunneling rate as VCG changes. In Fig. 8, we have
shown the effect of VCG over energy barrier width and electron
tunneling rate for the n-type ED-TFET. We can observe that,
as we increase VCG from 0 to 0.4 V, the energy barrier width
decreases exponentially from 20 to 10 nm till 0.4 V, afterward,
it is less reliant on VCG . In addition, the increased VCG pulls
down the energy of the intrinsic region (I ), which results in
the decrement in the energy barrier width and simultaneously
enhancement in the electron tunneling rate. Since the energy
barrier width is directly related to the electron tunneling rate,
lower the energy barrier width higher the electron tunneling
rate, and consequently, higher will be ION .
In the proposed device, energy barrier width and tunneling
rate can also be influenced by source-side spacer thickness (SGAP,S ), consequently ION and SS, as shown in Fig. 9.
An increment in SGAP,S causes a reduction in ION due to the
enhanced energy barrier width and the reduced tunneling
probability of electrons, which is consistent with the
previously reported results [7], [18]. Therefore, SGAP,S should
be as small as possible to get better tunneling efficiency;
As a result, very good ION and SS can be achieved.
IV. S ENSITIVITY A NALYSIS
In [7], [27], and [28], it is reported that the TFETs are
more sensitive toward variation in temperature and other
device parameters, such as dielectric thickness (TOX ) and TSI ,
than the conventional MOSFETs. Thus, small fluctuations in
temperature and TOX or TSI can cause major deterioration
in device performance that further exaggerated with variation

Fig. 10. ION and VTH fluctuation with variation in temperature for different
silicon thickness (6 and 8 nm) (a) conventional n-type TFET, and (b) n-type
ED-TFET and for different oxide thickness (0.5 and 1.5 nm) (c) conventional
n-type TFET, and (d) n-type ED-TFET.

in channel doping due to RDF in the conventional TFET. This

section presents, a detailed sensitivity analysis on different
device performance metrics, such as ION , VTH , and SS as a
function of temperature, TOX and TSI .
A. Sensitivity Toward Temperature
Ambient temperature has prominent effect on device
operation as it influences device electrical parameters, such
as VTH and ION . Hence, we have observed temperature
dependence on ION and VTH (keeping other device parameters
constant), as shown in Fig. 10(a)(d). It can be observed
that higher temperature causes the increment in ION and the
decrement in VTH , which is mainly due to bandgap narrowing.
Furthermore, simulation results show that the proposed device
has less sensitivity toward temperature as compared with the
conventional n-type TFET, for example, at TSI = 6 nm,
VTH increases 0.36 mV/K and ION changes 0.2026 A/K,
while in the n-type ED-TFET, these changes
remain 0.10 mV/K and 0.076 A/K, respectively, for
per kelvin change in temperature when scaled down from
500 to 100 K. Similarly, for TOX = 0.5 nm, the same
temperature change yields 0.1949 mV/K change in VTH and
0.3174 A/K change in ION , while in the n-type ED-TFET,

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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 62, NO. 8, AUGUST 2015

TABLE I
C OMPARISON OF T EMPERATURE VARIATION FOR n-T YPE

TABLE II
C OMPARISON OF P ERFORMANCE VARIATION W ITH PER

C ONVENTIONAL AND ED-TFETs

N ANOMETER C HANGE IN TOX AND TSI FOR n-T YPE

C ONVENTIONAL AND ED-TFETs

C. Sensitivity Toward Silicon Thickness

Fig. 11. (a) Oxide thickness and (b) silicon thickness sensitivity analysis of
the conventional TFET and the ED-TFET at VDS = 1 V.

these changes remain 0.0981 mV/K and 0.0248 A/K,

respectively, that are very small (1/10) in contrast with
the conventional n-type TFET, and these results are also
summarized in Table I. Higher variation in device parameters
with per kelvin change in temperature is due to the reduction
of energy bandgap at tunneling junction in case of highly
doped conventional TFET, which is more compared with
dopingless ED-TFET.
B. Sensitivity Toward Oxide Thickness
The oxide thickness (TOX ) is an important parameter
in MOSFETs, as it determines the gate capacitance (Cox ).
In the conventional MOSFETs, the ON current is inversely
proportional to the oxide thickness, but in the TFETs,
ION mainly depends on BTBT, as well as gate-oxide
capacitance [7]. Fig. 11(a) shows the sensitivity of ION and
SS for the conventional and the proposed devices for different
values of TOX . It can be observed that the reduction in TOX
enhances ION and SS in both the devices because of the
enhanced gate electric field that also reduces the SCEs [18].
Furthermore, the conventional TFET shows more variation
in SS and ION as compared with the proposed ED-TFET.
Hence, it is not necessary to scale TOX in the ED-TFET
as aggressively as in the conventional TFETs to improve
the short-channel characteristics; therefore, the ED-TFET
device exhibits better control over channel. For per nanometer
change in TOX (scaling from 2.5 to 0.5 nm) of the
conventional TFET, the SS and ION change by 11.2805 mV/dec
and 34.867 A/m, respectively, while in the ED-TFET, these
remain only 4.0963 mV/dec and 2.59 A/m, respectively.
Thus, the conventional TFET exhibits very high sensitivity
(10) toward device parameters, and these results are also
summarized in Table II. In addition, the presence of doped
S/D and channel regions under the influence of vertical
electrical field induce the RDF in the active region of the
devices, resulting significant variations in device electrical
characteristics [17], [29].

Another important device parameter that we have

considered is silicon thickness (TSI ), since, now a days,
a maximum number of devices are built on thin films. Hence,
we have observed that the effect of TSI scaling on ION and
SS (keeping other device parameters constant) can be seen
in Fig. 11(b). It can be observed that a thinner silicon layer
shows larger current due to higher tunneling rate, and it
also lowers the SS due to enhanced electrostatic control
over the device. Furthermore, the simulation results show
that the conventional TFET is more sensitive toward ION
and SS as compared with the ED-TFET. For example, ION
increases by 5.35 A/m and SS changes by 0.588 mV/dec,
but in conventional TFET, the changes occur in ION and SS
are 77.92 A/m and 2.68 mV/dec, respectively, for per
nanometer change in TSI when scaled down from 10 to 5 nm,
and these results are also summarized in Table II. Thus, the
proposed device demonstrates very less sensitivity toward
device parameter. This happens due to less reliant of RDF.
From the simulation results, it is observed that the ED-TFET
shows excellent control of SCEs and less sensitivity toward
ION , even in the presence of fluctuation in process parameters,
especially TSI and TOX , which are the most sensitive among
other device parameters. This idea can be extended to an
undoped SiNW with surrounding gate electrodes, making it
compatible with the future nanowire-based CMOS technology,
since the polarity-based SiNW MOSFET has already been
experimentally demonstrated [21].
V. C ONCLUSION
The concept of ED-TFET with PGs for dynamically configurable applications is affirmed using 2-D TCAD simulations.
The p+ and n+ are induced on a lightly doped silicon film via
PG biasing. The conduction mechanism in the ED-TFET can
be controlled by a tunneling barrier width similar to that of a
conventional TFET. This paper also highlighted the advantages
of the ED-TFET toward immunity to PVT, RDFs, and SCEs.
Furthermore, it is free from ion implantation and the thermal
annealing process. Hence, the proposed results may provide
incentives and guidelines for further research and experimental
exploration of the ED-TFET for circuit and system levels.
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Avinash Lahgere received the B.E. degree in electronics and telecommunication engineering from the
Shri Govindram Seksaria Institute of Technology
and Science, Indore, India, in 2013. He is currently pursuing the M.Tech. degree in electronics
and communication engineering with the PDPM
Indian Institute of Information Technology Design
and Manufacturing, Jabalpur, India.
His current research interests include physics of
nanoscale devices and configurable FETs.

Chitrakant Sahu received the B.E. degree in electrical and electronics engineering from Pt. Ravishankar
Shukla University, Raipur, India, in 2006, and the
M.Tech. degree in electronics engineering from the
University of Mumbai, Mumbai, India, in 2008.
He is currently pursuing the Ph.D. degree with
the Department of Electronics and Communication
Engineering, PDPM Indian Institute of Information
Technology Design and Manufacturing, Jabalpur,
India.

Jawar Singh received the Ph.D. degree from the

University of Bristol, Bristol, U.K., in 2010.
He is currently an Associate Professor with
the Department of Electronics and Communication
Engineering, PDPM Indian Institute of Information
Technology, Design and Manufacturing, Jabalpur,
India. His current research interests include exploration of classical and nonclassical device structures
for CMOS enhancement and replacement.